Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709096
Venkata N. K. Malladi, Monte Miller
This paper presents an analysis & comparison of GaAs and SOI processes for RF switch designs with applications aimed at 5G massive MIMO RF front end applications. An RF switch in SOI 130 nm process is presented. The switch operates from 0.1-3 GHz and achieves 48 dBm of 1 dB compression point (peak power), 0.5 dB Insertion Loss, 26 dB of isolation at 2.5 GHz.
{"title":"A 48 dBm peak power RF switch in SOI process for 5G mMIMO applications","authors":"Venkata N. K. Malladi, Monte Miller","doi":"10.1109/SIRF.2019.8709096","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709096","url":null,"abstract":"This paper presents an analysis & comparison of GaAs and SOI processes for RF switch designs with applications aimed at 5G massive MIMO RF front end applications. An RF switch in SOI 130 nm process is presented. The switch operates from 0.1-3 GHz and achieves 48 dBm of 1 dB compression point (peak power), 0.5 dB Insertion Loss, 26 dB of isolation at 2.5 GHz.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132582272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709088
Mikko Hietanen, J. Aikio, Rehman Akbar, T. Rahkonen, Aarno Pärssinen
A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. The circuit utilizes back-gate biasing which provides almost 4GHz additional output center frequency tuning range over other mechanisms leading to 21.3 to 30GHz operation range with 0dBm input signal. This covers 5G bands from 24.25 to 27.5GHz with good margin. Divider dissipates 11mW from 0.86V supply and occupies $800 {mu}m ^{2}$ of area. Small area allows to place divider-by-2 block next to IQ mixers in a direct conversion or sliding IF transmitter or receiver.
{"title":"A 28 GHz Static CML Frequency Divider with Back-Gate Tuning on 22-nm CMOS FD-SOI Technology","authors":"Mikko Hietanen, J. Aikio, Rehman Akbar, T. Rahkonen, Aarno Pärssinen","doi":"10.1109/SIRF.2019.8709088","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709088","url":null,"abstract":"A divide-by-2 frequency divider circuit was designed using 22-nm CMOS FD-SOI technology. The circuit utilizes back-gate biasing which provides almost 4GHz additional output center frequency tuning range over other mechanisms leading to 21.3 to 30GHz operation range with 0dBm input signal. This covers 5G bands from 24.25 to 27.5GHz with good margin. Divider dissipates 11mW from 0.86V supply and occupies $800 {mu}m ^{2}$ of area. Small area allows to place divider-by-2 block next to IQ mixers in a direct conversion or sliding IF transmitter or receiver.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115055176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709086
C. V. Vangerow, C. Bohn, H. Zwickel, C. Koos, T. Zwick
In this work an analog driver circuit for pulse amplitude modulated data signals with four amplitude levels (PAM-4) is investigated. The driver circuit is based on a distributed combining cell, which performs the PAM4 generation from binary input data streams. Due to the distributed topology, the driver core provides a high analog bandwidth and is well suited for high-speed operation. Since the amplification of both combiner paths can be adjusted individually, the combiner circuit offers predistortion capabilities when driving loads with a nonlinear transfer function. A one-stage prototype circuit using heterojunction bipolar transistors (HBTs) is implemented in a 130nm SiGe BiCMOS technology. Time-domain measurements prove PAM-4 signal generation at an output bitrate of 50GBit/s, while the driver consumes a DC power of 63mW. Additionally, predistortion of the circuit is demonstrated at 25GBit/s, leading to a variable vertical spacing of the amplitude levels.
{"title":"50GBit/s PAM-4 Driver Circuit Based on Variable Gain Distributed Power Combiner","authors":"C. V. Vangerow, C. Bohn, H. Zwickel, C. Koos, T. Zwick","doi":"10.1109/SIRF.2019.8709086","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709086","url":null,"abstract":"In this work an analog driver circuit for pulse amplitude modulated data signals with four amplitude levels (PAM-4) is investigated. The driver circuit is based on a distributed combining cell, which performs the PAM4 generation from binary input data streams. Due to the distributed topology, the driver core provides a high analog bandwidth and is well suited for high-speed operation. Since the amplification of both combiner paths can be adjusted individually, the combiner circuit offers predistortion capabilities when driving loads with a nonlinear transfer function. A one-stage prototype circuit using heterojunction bipolar transistors (HBTs) is implemented in a 130nm SiGe BiCMOS technology. Time-domain measurements prove PAM-4 signal generation at an output bitrate of 50GBit/s, while the driver consumes a DC power of 63mW. Additionally, predistortion of the circuit is demonstrated at 25GBit/s, leading to a variable vertical spacing of the amplitude levels.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129081172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709097
J. Qayyum, J. Albrecht, A. Ulusoy
This work demonstrates a 24-32 GHz upconverting mixer implemented in SiGe process technology. The mixer uses double-balanced Gilbert cell architecture with on-chip transformer-based baluns for the LO input and RF output ports. With LO power of 6 dBm, the mixer achieves a maximum conversion gain of 13.7 dB at 26.5 GHz, a 24-32 GHz 3-dB bandwidth, IF-bandwidth of 0.25-1.25 GHz on both side-bands with 27 GHz LO frequency and OP1dB of -1.5 dBm at 28 GHz. It occupies an area of $468-mu {m}times 465-mu{m}$ consuming 90 mW from a 2.5 V power supply. The performance is comparable to any state-of-the-art mixers in similar silicon technologies.
{"title":"A Compact 24-32 GHz Linear Upconverting Mixer with -1.5 dBm OP1dB using 0.13-μ SiGe BiCMOS Process","authors":"J. Qayyum, J. Albrecht, A. Ulusoy","doi":"10.1109/SIRF.2019.8709097","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709097","url":null,"abstract":"This work demonstrates a 24-32 GHz upconverting mixer implemented in SiGe process technology. The mixer uses double-balanced Gilbert cell architecture with on-chip transformer-based baluns for the LO input and RF output ports. With LO power of 6 dBm, the mixer achieves a maximum conversion gain of 13.7 dB at 26.5 GHz, a 24-32 GHz 3-dB bandwidth, IF-bandwidth of 0.25-1.25 GHz on both side-bands with 27 GHz LO frequency and OP1dB of -1.5 dBm at 28 GHz. It occupies an area of $468-mu {m}times 465-mu{m}$ consuming 90 mW from a 2.5 V power supply. The performance is comparable to any state-of-the-art mixers in similar silicon technologies.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122157169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709143
Radu Ciocovean, R. Weigel, A. Hagelauer, V. Issakov
This paper presents a 60 GHz highly efficient single-stage differential stacked Class AB power amplifier (PA) with second harmonic control. The circuit has been realized in a 45 nm PD-SOI CMOS technology. Measurement results show that the power amplifier achieves a maximum output power ($P_{max}$) of 15.3 dBm with a competitive maximum power-added efficiency ($PAE_{max}$) of 30.5 % at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a 1.8 V supply and the chip core size is 0. 36mmx0.35 mm.
{"title":"A 60 GHz 30.5% PAE Differential Stacked PA with Second Harmonic Control in 45 nm PD-SOI CMOS","authors":"Radu Ciocovean, R. Weigel, A. Hagelauer, V. Issakov","doi":"10.1109/SIRF.2019.8709143","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709143","url":null,"abstract":"This paper presents a 60 GHz highly efficient single-stage differential stacked Class AB power amplifier (PA) with second harmonic control. The circuit has been realized in a 45 nm PD-SOI CMOS technology. Measurement results show that the power amplifier achieves a maximum output power ($P_{max}$) of 15.3 dBm with a competitive maximum power-added efficiency ($PAE_{max}$) of 30.5 % at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a 1.8 V supply and the chip core size is 0. 36mmx0.35 mm.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133299493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709123
S. Arbabi, V. Rezaei, K. Entesari
This paper presents a digital phase modulator for a 2.4 GHz WLAN radio polar transmitter. It generates a constant envelope phase modulated signal suitable for a polar transmitter and supports a real-time wideband baseband digital signal. The phase modulator is based on an active vector-sum phase shifter with a 4 bit-DAC to generate binary weighted currents representing the digital input signal for I/Q branches and a 2-bit differential signed adder to vector-sum the quadrature currents and provide the phase at the output. With 6 control bits, 64 phase states with the resolution of 5.625$^{mathbf{o}}$ is achieved to cover the entire 360$^{mathbf{o}}$ phase range. To compensate for the output amplitude variations, I/Q currents are compensated for each phase state using a current correction block added to the DAC. The phase modulator is implemented in 0.18 um CMOS technology and measured with maximum baseband signal data rate for WLAN standard. The phase shifter output amplitude with the correction technique is approximately constant over the 64 states with maximum phase error of 1.45$^{mathbf{o}}$ and a maximum DNL of 0.257.
介绍了一种用于2.4 GHz无线局域网无线极极发射机的数字相位调制器。它产生一个适合于极性发射机的恒定包络相位调制信号，并支持实时宽带基带数字信号。相位调制器基于一个有源矢量和移相器，带有一个4位的dac，用于产生代表I/Q分支的数字输入信号的二进制加权电流，以及一个2位的差分符号加法器，用于矢量和正交电流并提供输出的相位。通过6个控制位，实现了分辨率为5.625$^{mathbf{o}}$的64个相位状态，覆盖了整个360$^{mathbf{o}}$相位范围。为了补偿输出幅度变化，使用添加到DAC的电流校正块对每个相态补偿I/Q电流。相位调制器采用0.18 um CMOS技术，并以WLAN标准的最大基带信号数据速率进行测量。采用校正技术的移相器输出幅值在64个状态下近似恒定，最大相位误差为1.45$^{mathbf{o}}$，最大DNL为0.257。
{"title":"A Constant Envelope Phase Modulator for 2.4 GHz WLAN Radio Polar Transmitters in 0.18 um CMOS","authors":"S. Arbabi, V. Rezaei, K. Entesari","doi":"10.1109/SIRF.2019.8709123","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709123","url":null,"abstract":"This paper presents a digital phase modulator for a 2.4 GHz WLAN radio polar transmitter. It generates a constant envelope phase modulated signal suitable for a polar transmitter and supports a real-time wideband baseband digital signal. The phase modulator is based on an active vector-sum phase shifter with a 4 bit-DAC to generate binary weighted currents representing the digital input signal for I/Q branches and a 2-bit differential signed adder to vector-sum the quadrature currents and provide the phase at the output. With 6 control bits, 64 phase states with the resolution of 5.625$^{mathbf{o}}$ is achieved to cover the entire 360$^{mathbf{o}}$ phase range. To compensate for the output amplitude variations, I/Q currents are compensated for each phase state using a current correction block added to the DAC. The phase modulator is implemented in 0.18 um CMOS technology and measured with maximum baseband signal data rate for WLAN standard. The phase shifter output amplitude with the correction technique is approximately constant over the 64 states with maximum phase error of 1.45$^{mathbf{o}}$ and a maximum DNL of 0.257.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124119749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/SIRF.2019.8709120
J. Rimmelspacher, R. Weigel, A. Hagelauer, V. Issakov
This paper presents a 60 GHz dual-core push-push VCO in a 45 nm partially depleted (PD) RF Silicon-on-Insulator (SOI) CMOS technology. The cores are coupled inductively via differential inductors. The best measured phase noise at 1 MHz offset from a 63 GHz carrier is -$94.4 dBc/Hz. The wideband continuous frequency-tuning-range (FTR) is 16 %. The DC power dissipation is 76 mW including fundamental 30 GHz and second harmonic (H2) 60 GHz output buffers at 1 V power supply voltage. The measurement results of a reference single-core VCO design proves the relative phase noise improvement of the implemented core-coupling technique. The chip area excluding pads is 0.09 mm2.
{"title":"LC Tank Differential Inductor-Coupled Dual-Core 60 GHz Push-Push VCO in 45 nm RF-SOI CMOS Technology","authors":"J. Rimmelspacher, R. Weigel, A. Hagelauer, V. Issakov","doi":"10.1109/SIRF.2019.8709120","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709120","url":null,"abstract":"This paper presents a 60 GHz dual-core push-push VCO in a 45 nm partially depleted (PD) RF Silicon-on-Insulator (SOI) CMOS technology. The cores are coupled inductively via differential inductors. The best measured phase noise at 1 MHz offset from a 63 GHz carrier is -$94.4 dBc/Hz. The wideband continuous frequency-tuning-range (FTR) is 16 %. The DC power dissipation is 76 mW including fundamental 30 GHz and second harmonic (H2) 60 GHz output buffers at 1 V power supply voltage. The measurement results of a reference single-core VCO design proves the relative phase noise improvement of the implemented core-coupling technique. The chip area excluding pads is 0.09 mm2.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"412 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124404770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIRF.2019.8709125
Zhibo Cao, A. Göritz, M. Wietstruck, S. Wipf, A. Trusch, M. Kaynak
A finite element method (FEM) wafer scale model considering all the process details, e.g. metal patterning, via etching, etc., is built for a state-of-the-art $0.13-mu m$ SiGe BiCMOS fully processed 8-inch wafer. Associated layer residual stress and wafer warpage are extracted and compared with hand calculation and experimental results. The comparison results show that the wafer warpage predicted by FEM model demonstrates only about $10 mu m$ maximum deviation over an $80 mu m -$bowed wafer. An accurate stress model for an 8-inch wafer including full BiCMOS process is successfully developed and validated.
{"title":"Finite-element modelling of stress induced wafer warpage for a full BiCMOS process","authors":"Zhibo Cao, A. Göritz, M. Wietstruck, S. Wipf, A. Trusch, M. Kaynak","doi":"10.1109/SIRF.2019.8709125","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709125","url":null,"abstract":"A finite element method (FEM) wafer scale model considering all the process details, e.g. metal patterning, via etching, etc., is built for a state-of-the-art $0.13-mu m$ SiGe BiCMOS fully processed 8-inch wafer. Associated layer residual stress and wafer warpage are extracted and compared with hand calculation and experimental results. The comparison results show that the wafer warpage predicted by FEM model demonstrates only about $10 mu m$ maximum deviation over an $80 mu m -$bowed wafer. An accurate stress model for an 8-inch wafer including full BiCMOS process is successfully developed and validated.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIRF.2019.8709121
Yuan Liang, C. Boon, D. Kissinger, Yong Wang
A novel D-type flip-flop (DFF) with active inductive peaking powered by 0.7 V supply is proposed and implemented for low power communication. Forward bias (FB) technique is introduced for both the DFF and the active inductor in the clock buffer to effectively reduce the transistor threshold voltage, thus increasing the output swing along the data path. To mitigate the potential of junction breakdown, deep N-well NMOS is utilized for forward biasing. As the clock buffer is loaded by the active inductor, the output common-mode voltage can be increased by FB as well. The subsequent DFF can be hereby biased at class AB for fast data sampling. A pseudo random binary sequence (PRBS) generator is implemented using the proposed DFF and the active inductor to verify the low power operation. Measured results show that the PRBS-4 can generates 8 Gb/s random data stream with 1.75 pJ/bit power efficiency under a 0.7 V power supply, achieving over 2X power efficiency improvement compared to the design operating at 1.2.
{"title":"A Low-Power D-type Flip-flop with Active Inductor and Forward Body Biasing Techniques in 40-nm CMOS","authors":"Yuan Liang, C. Boon, D. Kissinger, Yong Wang","doi":"10.1109/SIRF.2019.8709121","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709121","url":null,"abstract":"A novel D-type flip-flop (DFF) with active inductive peaking powered by 0.7 V supply is proposed and implemented for low power communication. Forward bias (FB) technique is introduced for both the DFF and the active inductor in the clock buffer to effectively reduce the transistor threshold voltage, thus increasing the output swing along the data path. To mitigate the potential of junction breakdown, deep N-well NMOS is utilized for forward biasing. As the clock buffer is loaded by the active inductor, the output common-mode voltage can be increased by FB as well. The subsequent DFF can be hereby biased at class AB for fast data sampling. A pseudo random binary sequence (PRBS) generator is implemented using the proposed DFF and the active inductor to verify the low power operation. Measured results show that the PRBS-4 can generates 8 Gb/s random data stream with 1.75 pJ/bit power efficiency under a 0.7 V power supply, achieving over 2X power efficiency improvement compared to the design operating at 1.2.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122715476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIRF.2019.8709117
M. Voelkel, R. Weigel, A. Hagelauer
In this paper, a fully integrated digital adjustable sixport receiver front-end working at 60GHz is presented. The circuit features two variable gain amplifier, the passive sixport network, four detectors and a SPI-interface. Application area are industrial radar or angle of arrival detection. The phase measurement is done by superposition and power detection of two millimeter wave signals. The integrated circuit has a power consumption of 88.44mW from a 3.3V supply voltage. It is fabricated in a $0.13 mu m$ SiGe BiCMOS process and has a size of $1560 mu times 1000 mu m$. The RF and reference input power can be adjusted in a 21dB range over a 12bit digital interface. The receiver exhibits a 1dB compression point of -21.9dB. RF signals down to -55dBm are detectable.
{"title":"A Digital Adjustable 60-GHz Integrated Sixport Receiver Front-End in a 130-nm BiCMOS Technology","authors":"M. Voelkel, R. Weigel, A. Hagelauer","doi":"10.1109/SIRF.2019.8709117","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709117","url":null,"abstract":"In this paper, a fully integrated digital adjustable sixport receiver front-end working at 60GHz is presented. The circuit features two variable gain amplifier, the passive sixport network, four detectors and a SPI-interface. Application area are industrial radar or angle of arrival detection. The phase measurement is done by superposition and power detection of two millimeter wave signals. The integrated circuit has a power consumption of 88.44mW from a 3.3V supply voltage. It is fabricated in a $0.13 mu m$ SiGe BiCMOS process and has a size of $1560 mu times 1000 mu m$. The RF and reference input power can be adjusted in a 21dB range over a 12bit digital interface. The receiver exhibits a 1dB compression point of -21.9dB. RF signals down to -55dBm are detectable.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121978269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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