Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347578
T. Xia, P. Song, K. Jenkins, Jien-Chung Lo
In this paper, we presents a programmable jitter generator. Different from the traditional jitter generator that uses the analog phase modulation (PM) technique to generate only non-Gaussian distributed jitter components, the proposed jitter generator uses digital techniques. It consists of a voltage controlled delay chain, jitter control block, and some basic digital components. It can generate not only the non-Gaussian distributed jitter component, but also the Gaussiandistributed jitter component. In addition, almost all jitter characteristics are controllable. This jitter generator can be used in jitter tolerance test and jitter transfer function measurement. A Xilinx XC4010 FPGA chip is used to validate this design.
{"title":"Delay chain based programmable jitter generator","authors":"T. Xia, P. Song, K. Jenkins, Jien-Chung Lo","doi":"10.1109/ETSYM.2004.1347578","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347578","url":null,"abstract":"In this paper, we presents a programmable jitter generator. Different from the traditional jitter generator that uses the analog phase modulation (PM) technique to generate only non-Gaussian distributed jitter components, the proposed jitter generator uses digital techniques. It consists of a voltage controlled delay chain, jitter control block, and some basic digital components. It can generate not only the non-Gaussian distributed jitter component, but also the Gaussiandistributed jitter component. In addition, almost all jitter characteristics are controllable. This jitter generator can be used in jitter tolerance test and jitter transfer function measurement. A Xilinx XC4010 FPGA chip is used to validate this design.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123841321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347612
O. Sinanoglu, A. Orailoglu
Attaining parallelism among core tests is of crucial importance to the reduction of SOC test costs. In this paper, we propose an SOC test methodology that enhances SOC testapplication throughput with no increase in test pin requirements. In the proposed methodology,the test vector of a core is formed in its scan chain by transforming the response of the preceding core; logic gates inserted between the core scan cells transform the response ofthe preceding core into the core test vector. The consequent core tests can be thought of as being pipelined, thus reducing the time spent for the delivery of the test vectors into the scan cells of the cores being tested in parallel, and hence increasing the throughput of SOC test application. The proposed algorithmic framework identifies the cost-effective hardware that maps the responses of the preceding core onto a maximal number of core test vectors through the utilization of effiient test vector and scan cell reordering heuristics; the impact of these techniques is modeled, enabling their utilization along with the aforementioned transformation techniques. We furthermore investigate various scan chain configuration techniques to enhance the pipeline efficiency, thus minimizing the pipeline period and theSOC test time. The efficacy of the proposed methodology translates into enhanced parallelism in testing SOC cores.
{"title":"Pipelined test of SOC cores through test data transformations","authors":"O. Sinanoglu, A. Orailoglu","doi":"10.1109/ETSYM.2004.1347612","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347612","url":null,"abstract":"Attaining parallelism among core tests is of crucial importance to the reduction of SOC test costs. In this paper, we propose an SOC test methodology that enhances SOC testapplication throughput with no increase in test pin requirements. In the proposed methodology,the test vector of a core is formed in its scan chain by transforming the response of the preceding core; logic gates inserted between the core scan cells transform the response ofthe preceding core into the core test vector. The consequent core tests can be thought of as being pipelined, thus reducing the time spent for the delivery of the test vectors into the scan cells of the cores being tested in parallel, and hence increasing the throughput of SOC test application. The proposed algorithmic framework identifies the cost-effective hardware that maps the responses of the preceding core onto a maximal number of core test vectors through the utilization of effiient test vector and scan cell reordering heuristics; the impact of these techniques is modeled, enabling their utilization along with the aforementioned transformation techniques. We furthermore investigate various scan chain configuration techniques to enhance the pipeline efficiency, thus minimizing the pipeline period and theSOC test time. The efficacy of the proposed methodology translates into enhanced parallelism in testing SOC cores.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129316894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347605
N. Dumas, F. Azaïs, L. Latorre, P. Nouet
The development of low-cost go/no-go procedures for MEMS production testing is one of the main issues of MEMS manufacturability. In particular, the generation of low-cost test stimuli is a real challenge. In this paper, we investigate the generation of electrically-induced thermal stimuli to test electro-mechanical structures. Static, transient and harmonic responses are studied and it is demonstrated that they can be used for efficient detection and classification of several faulty devices.
{"title":"Electrically-induced thermal stimuli forMEMS testing","authors":"N. Dumas, F. Azaïs, L. Latorre, P. Nouet","doi":"10.1109/ETSYM.2004.1347605","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347605","url":null,"abstract":"The development of low-cost go/no-go procedures for MEMS production testing is one of the main issues of MEMS manufacturability. In particular, the generation of low-cost test stimuli is a real challenge. In this paper, we investigate the generation of electrically-induced thermal stimuli to test electro-mechanical structures. Static, transient and harmonic responses are studied and it is demonstrated that they can be used for efficient detection and classification of several faulty devices.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125356041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ETSYM.2004.1347624
M. Negreiros, L. Carro, A. Susin
This work presents some results regarding the development of a BIST technique capable of noise figure evaluation. Noise figure is an important parameter in the specification and design of low noise systems, such as communications systems and biomedical instrumentation. A review of published techniques for noise figure evaluation is provided. A new technique aimed to estimate noise figure in a SoC environment is then proposed. The technique is based on the use of a simple and low cost noise generator. Simulation results are provided in order to make an initial evaluation of the feasibility of the proposed approach.
{"title":"Towards a BIST technique for noise figure evaluation","authors":"M. Negreiros, L. Carro, A. Susin","doi":"10.1109/ETSYM.2004.1347624","DOIUrl":"https://doi.org/10.1109/ETSYM.2004.1347624","url":null,"abstract":"This work presents some results regarding the development of a BIST technique capable of noise figure evaluation. Noise figure is an important parameter in the specification and design of low noise systems, such as communications systems and biomedical instrumentation. A review of published techniques for noise figure evaluation is provided. A new technique aimed to estimate noise figure in a SoC environment is then proposed. The technique is based on the use of a simple and low cost noise generator. Simulation results are provided in order to make an initial evaluation of the feasibility of the proposed approach.","PeriodicalId":358790,"journal":{"name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126158861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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