Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807722
N. Prokopenko, I. Pakhomov, A. Bugakova, N. Butyrlagin
The new architectures of the high-speed operational amplifier (op-amp) based on the complementary folded cascodes (FCs), which form the intermediate stage of op-amp, are suggested. In the folded cascode the circuit techniques, excluding the traditional limitations of its output current, which recharges the balancing capacitor of op-amp, are provided. It increases the maximum slew rate of op-amp (SR) by a factor of 4-5. It is recommended to use class AB differential amplifiers as an input stage of op-amp. When realizing the op-amp on the Zarlink process, the maximum slew rate is more than 20000 V/μs. Besides, other parameters of the transient (the stability, the oscillability, the maximum overshoot, the dependence of SR on the impulse input signal amplitude, etc.) don't worsen. The circuit of op-amps is realized within the classical technologies, including BiJ, BiFET, CMOS.
{"title":"The method of speeding of the operational amplifiers based on the folded cascode","authors":"N. Prokopenko, I. Pakhomov, A. Bugakova, N. Butyrlagin","doi":"10.1109/EWDTS.2016.7807722","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807722","url":null,"abstract":"The new architectures of the high-speed operational amplifier (op-amp) based on the complementary folded cascodes (FCs), which form the intermediate stage of op-amp, are suggested. In the folded cascode the circuit techniques, excluding the traditional limitations of its output current, which recharges the balancing capacitor of op-amp, are provided. It increases the maximum slew rate of op-amp (SR) by a factor of 4-5. It is recommended to use class AB differential amplifiers as an input stage of op-amp. When realizing the op-amp on the Zarlink process, the maximum slew rate is more than 20000 V/μs. Besides, other parameters of the transient (the stability, the oscillability, the maximum overshoot, the dependence of SR on the impulse input signal amplitude, etc.) don't worsen. The circuit of op-amps is realized within the classical technologies, including BiJ, BiFET, CMOS.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129072257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807662
Artur Ziarmand, D. Kucherenko, Tetiana Soklakova
The purpose of this article is a review of technologies, algorithms and models of monitoring and control systems of urban transportation systems, companies and their developments in this field in the world, as well as the study of currently existing methods of communication between vehicles, road infrastructure objects and the server or the cloud side where further processing of the data may take place and displaying it in real time. There are also considered available communication protocols necessary for the creation of cyber-physical systems for road traffic management.
{"title":"Transport monitoring and control systems","authors":"Artur Ziarmand, D. Kucherenko, Tetiana Soklakova","doi":"10.1109/EWDTS.2016.7807662","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807662","url":null,"abstract":"The purpose of this article is a review of technologies, algorithms and models of monitoring and control systems of urban transportation systems, companies and their developments in this field in the world, as well as the study of currently existing methods of communication between vehicles, road infrastructure objects and the server or the cloud side where further processing of the data may take place and displaying it in real time. There are also considered available communication protocols necessary for the creation of cyber-physical systems for road traffic management.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124169872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807646
C. C. Gürsoy, Abdullah Yildiz, Sezer Gören
Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing functional clock cycles of the test does not cause loss of detection of that fault. This paper presents a procedure that produces a multi-cycle test set by optimizing a single-cycle test set for fault coverage and test application time while considering stuck-at, bridging and transition faults at the same time.
{"title":"On optimization of multi-cycle tests for test quality and application time","authors":"C. C. Gürsoy, Abdullah Yildiz, Sezer Gören","doi":"10.1109/EWDTS.2016.7807646","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807646","url":null,"abstract":"Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing functional clock cycles of the test does not cause loss of detection of that fault. This paper presents a procedure that produces a multi-cycle test set by optimizing a single-cycle test set for fault coverage and test application time while considering stuck-at, bridging and transition faults at the same time.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121258151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807657
Seyyed Mohammad Saleh Samimi, Ehsan Aerabi, Arash Nejat, M. Fazeli, D. Hély, V. Beroulle
Fabless semiconductor business model includes different third party roles. Among these roles, untrusted fabrication foundries can take the opportunity to overbuild the layout or extract its IPs and resell them. Logic masking methods modify the IPs/ICs to harden them against such threats. Masked circuits have extra inputs and components (the so-called key-inputs, and keygates) which make two modes for the circuit: a functional mode and an incorrect masked one. Masked circuits work correctly/incorrectly (in the functional/locked mode) depending on the correctness of the key. A proper logic masking method aims at modifying a circuit such that for any wrong key, the hamming distance between the produced output and the correct output tends to 50% as much as possible. To this end, we propose a greedy algorithm that investigates the circuit signals to find the best candidates for inserting keygates. Simulation results show that the algorithm can mask the original functionality of circuits for 99.6% on average.
{"title":"High output hamming-distance achievement by a greedy logic masking approach","authors":"Seyyed Mohammad Saleh Samimi, Ehsan Aerabi, Arash Nejat, M. Fazeli, D. Hély, V. Beroulle","doi":"10.1109/EWDTS.2016.7807657","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807657","url":null,"abstract":"Fabless semiconductor business model includes different third party roles. Among these roles, untrusted fabrication foundries can take the opportunity to overbuild the layout or extract its IPs and resell them. Logic masking methods modify the IPs/ICs to harden them against such threats. Masked circuits have extra inputs and components (the so-called key-inputs, and keygates) which make two modes for the circuit: a functional mode and an incorrect masked one. Masked circuits work correctly/incorrectly (in the functional/locked mode) depending on the correctness of the key. A proper logic masking method aims at modifying a circuit such that for any wrong key, the hamming distance between the produced output and the correct output tends to 50% as much as possible. To this end, we propose a greedy algorithm that investigates the circuit signals to find the best candidates for inserting keygates. Simulation results show that the algorithm can mask the original functionality of circuits for 99.6% on average.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123657015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807699
S. Klevtsov
Model and algorithm of warning about the dangerous change in the parameter of the technical object designed. The algorithm is based on the diagrams constructed and operates in real time. Local array of time series points characterizing parameter chart forms. Each point on the graph the current value of the parameter and the following parameter value is formed. The time window is determined first. Array cut time window that moves along the time series. The sensor data in the process of forming a time series are used. Determination of dangerous changes in the parameters is carried out using a modified neural network.
{"title":"Determination jump monitored parameter using a neural network","authors":"S. Klevtsov","doi":"10.1109/EWDTS.2016.7807699","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807699","url":null,"abstract":"Model and algorithm of warning about the dangerous change in the parameter of the technical object designed. The algorithm is based on the diagrams constructed and operates in real time. Local array of time series points characterizing parameter chart forms. Each point on the graph the current value of the parameter and the following parameter value is formed. The time window is determined first. Array cut time window that moves along the time series. The sensor data in the process of forming a time series are used. Determination of dangerous changes in the parameters is carried out using a modified neural network.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121578498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807640
Hayk Chukhajyan
Most of modern system-on-chip (SoC) contain multiple hierarchy levels. This imposes specific requirements on the test solution, test access mechanism (TAM), and porting of core test patterns. Another challenge for multi-core hierarchical SoCs is the test integration time and automated generation of hierarchical test network and TAM. This paper presents a method for automated generation of core test description. The core test description file transfers the core test information required for automated generation of hierarchical test system. The test description file can contain bulky core-specific information on core test features necessary for hierarchical test. Automated generation of core test description allows drastically reduce hierarchical system generation and integration time.
{"title":"Automated generation of core test description file for hierarchical test","authors":"Hayk Chukhajyan","doi":"10.1109/EWDTS.2016.7807640","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807640","url":null,"abstract":"Most of modern system-on-chip (SoC) contain multiple hierarchy levels. This imposes specific requirements on the test solution, test access mechanism (TAM), and porting of core test patterns. Another challenge for multi-core hierarchical SoCs is the test integration time and automated generation of hierarchical test network and TAM. This paper presents a method for automated generation of core test description. The core test description file transfers the core test information required for automated generation of hierarchical test system. The test description file can contain bulky core-specific information on core test features necessary for hierarchical test. Automated generation of core test description allows drastically reduce hierarchical system generation and integration time.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117132969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807633
D. Efanov, V. Sapozhnikov, V. Sapozhnikov
The article provides a method of formation of the sum code with minimum total number of undetectable errors in data vectors. The idea of building this code is based on the principle of weighing of data vector bits, obtaining the weight of data vector and following modifications of its value. New code has the same number of bits in check vectors, as classic Berger code, however, it also has high detection ability and, that is by no means unimportant, in the area of low multiplicities. The article gives the description of modified weight-based sum code characteristics, as well as the results of experiments for organization of concurrent error detection (CED) systems for the set of reference combinational circuits LGSynth'89.
{"title":"On one method of formation of optimum sum code for technical diagnostics systems","authors":"D. Efanov, V. Sapozhnikov, V. Sapozhnikov","doi":"10.1109/EWDTS.2016.7807633","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807633","url":null,"abstract":"The article provides a method of formation of the sum code with minimum total number of undetectable errors in data vectors. The idea of building this code is based on the principle of weighing of data vector bits, obtaining the weight of data vector and following modifications of its value. New code has the same number of bits in check vectors, as classic Berger code, however, it also has high detection ability and, that is by no means unimportant, in the area of low multiplicities. The article gives the description of modified weight-based sum code characteristics, as well as the results of experiments for organization of concurrent error detection (CED) systems for the set of reference combinational circuits LGSynth'89.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116117208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807748
M. Mikheev, T. Zhashkova, E. N. Meshcheryakova, K. Gudkov, A. Grishko
With the aim of increasing the recognition precision of acoustic surface waves the analysis of physical properties of wave propagation has been proposed, and also the dependence of the wave structure on the geometric parameters of the object under study and material used for the object construction is described. The authors have determined the implementation characteristics of the subsystem for identifying and structuring acoustic surface wave sensor data. They also have modelled the reference signals of the training sample for the recognition of the type of acoustic surface waves. They have reached the conclusions on the dependence between the structure of acoustic surface waves and the probability of recognition.
{"title":"Imitation modelling for the subsystem of identification and structuring data of signal sensors","authors":"M. Mikheev, T. Zhashkova, E. N. Meshcheryakova, K. Gudkov, A. Grishko","doi":"10.1109/EWDTS.2016.7807748","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807748","url":null,"abstract":"With the aim of increasing the recognition precision of acoustic surface waves the analysis of physical properties of wave propagation has been proposed, and also the dependence of the wave structure on the geometric parameters of the object under study and material used for the object construction is described. The authors have determined the implementation characteristics of the subsystem for identifying and structuring acoustic surface wave sensor data. They also have modelled the reference signals of the training sample for the recognition of the type of acoustic surface waves. They have reached the conclusions on the dependence between the structure of acoustic surface waves and the probability of recognition.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127909618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807670
V. Hahanov, Mazen Abdelrahman Abdelaziz Hussein, A. Hahanova, K. Man
Cyber culture of virtual-macro-micro-computing, which formulates, explains and predicts the current processes and phenomena monitoring and control technology in the physical and virtual space is proposed. The verbal and structural definitions of the main types of computing, based on current trends evolution of planet cyber ecosystem are represented. The universal model of MAT-computing: <;Memory, Address, Transactions>, which leverages three components to create a computational structure in technologically acceptable matter environment is proposed. The info-quantum direction of human expansion into space and the possibility of a similar penetration unearthly biotech objects in the ecosystem of our planet is shown. Computing model, which defines the structure of quasi-optimal digital monitoring and cloud control of scalable technical, biological, social and virtual processes is proposed.
{"title":"Cyber physical computing","authors":"V. Hahanov, Mazen Abdelrahman Abdelaziz Hussein, A. Hahanova, K. Man","doi":"10.1109/EWDTS.2016.7807670","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807670","url":null,"abstract":"Cyber culture of virtual-macro-micro-computing, which formulates, explains and predicts the current processes and phenomena monitoring and control technology in the physical and virtual space is proposed. The verbal and structural definitions of the main types of computing, based on current trends evolution of planet cyber ecosystem are represented. The universal model of MAT-computing: <;Memory, Address, Transactions>, which leverages three components to create a computational structure in technologically acceptable matter environment is proposed. The info-quantum direction of human expansion into space and the possibility of a similar penetration unearthly biotech objects in the ecosystem of our planet is shown. Computing model, which defines the structure of quasi-optimal digital monitoring and cloud control of scalable technical, biological, social and virtual processes is proposed.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127458881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807735
Y. Stepchenkov, V. Zakharov, Y. Rogdestvenski, Y. Diachenko, N. Morozov, D. Stepchenkov
Speed-independent fused multiply-add-subtract unit is offered together with test environment providing full verification of its performance and workability in all range of the environment conditions. It complies with IEEE 754 Standard, and performs double and single precision operations at three operands. The unit is implemented as a two-channel with a common input and output. Each channel is a pipeline with four stages. Multiplier is implemented on the modified Booth algorithm using self-timed redundant code. The unit was designed on a base of standard CMOS process with 65 nm design rules and has 3.15 Gigaflops performance and less than 2 ns latency.
{"title":"Speed-independent fused multiply add and subtract unit","authors":"Y. Stepchenkov, V. Zakharov, Y. Rogdestvenski, Y. Diachenko, N. Morozov, D. Stepchenkov","doi":"10.1109/EWDTS.2016.7807735","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807735","url":null,"abstract":"Speed-independent fused multiply-add-subtract unit is offered together with test environment providing full verification of its performance and workability in all range of the environment conditions. It complies with IEEE 754 Standard, and performs double and single precision operations at three operands. The unit is implemented as a two-channel with a common input and output. Each channel is a pipeline with four stages. Multiplier is implemented on the modified Booth algorithm using self-timed redundant code. The unit was designed on a base of standard CMOS process with 65 nm design rules and has 3.15 Gigaflops performance and less than 2 ns latency.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130531785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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