Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807657
Seyyed Mohammad Saleh Samimi, Ehsan Aerabi, Arash Nejat, M. Fazeli, D. Hély, V. Beroulle
Fabless semiconductor business model includes different third party roles. Among these roles, untrusted fabrication foundries can take the opportunity to overbuild the layout or extract its IPs and resell them. Logic masking methods modify the IPs/ICs to harden them against such threats. Masked circuits have extra inputs and components (the so-called key-inputs, and keygates) which make two modes for the circuit: a functional mode and an incorrect masked one. Masked circuits work correctly/incorrectly (in the functional/locked mode) depending on the correctness of the key. A proper logic masking method aims at modifying a circuit such that for any wrong key, the hamming distance between the produced output and the correct output tends to 50% as much as possible. To this end, we propose a greedy algorithm that investigates the circuit signals to find the best candidates for inserting keygates. Simulation results show that the algorithm can mask the original functionality of circuits for 99.6% on average.
{"title":"High output hamming-distance achievement by a greedy logic masking approach","authors":"Seyyed Mohammad Saleh Samimi, Ehsan Aerabi, Arash Nejat, M. Fazeli, D. Hély, V. Beroulle","doi":"10.1109/EWDTS.2016.7807657","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807657","url":null,"abstract":"Fabless semiconductor business model includes different third party roles. Among these roles, untrusted fabrication foundries can take the opportunity to overbuild the layout or extract its IPs and resell them. Logic masking methods modify the IPs/ICs to harden them against such threats. Masked circuits have extra inputs and components (the so-called key-inputs, and keygates) which make two modes for the circuit: a functional mode and an incorrect masked one. Masked circuits work correctly/incorrectly (in the functional/locked mode) depending on the correctness of the key. A proper logic masking method aims at modifying a circuit such that for any wrong key, the hamming distance between the produced output and the correct output tends to 50% as much as possible. To this end, we propose a greedy algorithm that investigates the circuit signals to find the best candidates for inserting keygates. Simulation results show that the algorithm can mask the original functionality of circuits for 99.6% on average.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123657015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807748
M. Mikheev, T. Zhashkova, E. N. Meshcheryakova, K. Gudkov, A. Grishko
With the aim of increasing the recognition precision of acoustic surface waves the analysis of physical properties of wave propagation has been proposed, and also the dependence of the wave structure on the geometric parameters of the object under study and material used for the object construction is described. The authors have determined the implementation characteristics of the subsystem for identifying and structuring acoustic surface wave sensor data. They also have modelled the reference signals of the training sample for the recognition of the type of acoustic surface waves. They have reached the conclusions on the dependence between the structure of acoustic surface waves and the probability of recognition.
{"title":"Imitation modelling for the subsystem of identification and structuring data of signal sensors","authors":"M. Mikheev, T. Zhashkova, E. N. Meshcheryakova, K. Gudkov, A. Grishko","doi":"10.1109/EWDTS.2016.7807748","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807748","url":null,"abstract":"With the aim of increasing the recognition precision of acoustic surface waves the analysis of physical properties of wave propagation has been proposed, and also the dependence of the wave structure on the geometric parameters of the object under study and material used for the object construction is described. The authors have determined the implementation characteristics of the subsystem for identifying and structuring acoustic surface wave sensor data. They also have modelled the reference signals of the training sample for the recognition of the type of acoustic surface waves. They have reached the conclusions on the dependence between the structure of acoustic surface waves and the probability of recognition.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127909618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807646
C. C. Gürsoy, Abdullah Yildiz, Sezer Gören
Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing functional clock cycles of the test does not cause loss of detection of that fault. This paper presents a procedure that produces a multi-cycle test set by optimizing a single-cycle test set for fault coverage and test application time while considering stuck-at, bridging and transition faults at the same time.
{"title":"On optimization of multi-cycle tests for test quality and application time","authors":"C. C. Gürsoy, Abdullah Yildiz, Sezer Gören","doi":"10.1109/EWDTS.2016.7807646","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807646","url":null,"abstract":"Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing functional clock cycles of the test does not cause loss of detection of that fault. This paper presents a procedure that produces a multi-cycle test set by optimizing a single-cycle test set for fault coverage and test application time while considering stuck-at, bridging and transition faults at the same time.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121258151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807688
M. Gromov, Aleksandr S. Tvardovskii, N. Yevtushenko
In this paper, we address the problem of deriving test suites for checking components of interacting finite state machines with timed guards (TFSMs). Given a component TFSM, a corresponding test is derived for the composition of TFSMs under the assumption that all other components are fault-free.
{"title":"Testing components of interacting timed finite state machines","authors":"M. Gromov, Aleksandr S. Tvardovskii, N. Yevtushenko","doi":"10.1109/EWDTS.2016.7807688","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807688","url":null,"abstract":"In this paper, we address the problem of deriving test suites for checking components of interacting finite state machines with timed guards (TFSMs). Given a component TFSM, a corresponding test is derived for the composition of TFSMs under the assumption that all other components are fault-free.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114892733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807682
Toral Shah, Virendra Singh, A. Matrosova
Traditional scan based transition delay fault tests can potentially miss variability induced delay faults on long interconnects. On the other hand, an ATPG may not be successful in deriving test patterns for all paths. The paper proposes a BDD based synthesis method where all the paths are testable under the path delay fault model without addition of extra inputs. Each ROBDD (Reduced-Ordered-Binary Decision Diagram) node is covered by an Invert-AND-OR sub-circuit. The paper proves that the synthesized circuit is fully testable for path delay faults, either by robust tests or validatable non-robust tests.
{"title":"ROBDD based path delay fault testable combinational circuit synthesis","authors":"Toral Shah, Virendra Singh, A. Matrosova","doi":"10.1109/EWDTS.2016.7807682","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807682","url":null,"abstract":"Traditional scan based transition delay fault tests can potentially miss variability induced delay faults on long interconnects. On the other hand, an ATPG may not be successful in deriving test patterns for all paths. The paper proposes a BDD based synthesis method where all the paths are testable under the path delay fault model without addition of extra inputs. Each ROBDD (Reduced-Ordered-Binary Decision Diagram) node is covered by an Invert-AND-OR sub-circuit. The paper proves that the synthesized circuit is fully testable for path delay faults, either by robust tests or validatable non-robust tests.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130304492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Delay defects can be detected using Launch-off-capture (LOC) and Launch-off-shift (LOS) based delay test techniques. In terms of delay test coverage and test set size, LOS is more effective compared to LOC. However, to exercise LOS test a high speed scan enable signal is required. The cost of implementing a high speed global scan enable signal is prohibitively high. In practice, most of the commercial designs employing full scan design support only LOC based delay test. In this paper, we propose a new scan flip-flop design that is capable of exercising both LOS and LOC based delay test with a slow scan enable signal. The proposed design can achieve much higher delay fault coverage by exercising both LOS and LOC test. Furthermore, in a mixed mode scan test environment the proposed scan flip-flop can be used both as a serial scan cell as well as a random access scan (RAS) cell.
{"title":"Enabling LOS delay test with slow scan enable","authors":"Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh","doi":"10.1109/EWDTS.2016.7807648","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807648","url":null,"abstract":"Delay defects can be detected using Launch-off-capture (LOC) and Launch-off-shift (LOS) based delay test techniques. In terms of delay test coverage and test set size, LOS is more effective compared to LOC. However, to exercise LOS test a high speed scan enable signal is required. The cost of implementing a high speed global scan enable signal is prohibitively high. In practice, most of the commercial designs employing full scan design support only LOC based delay test. In this paper, we propose a new scan flip-flop design that is capable of exercising both LOS and LOC based delay test with a slow scan enable signal. The proposed design can achieve much higher delay fault coverage by exercising both LOS and LOC test. Furthermore, in a mixed mode scan test environment the proposed scan flip-flop can be used both as a serial scan cell as well as a random access scan (RAS) cell.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130596980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807633
D. Efanov, V. Sapozhnikov, V. Sapozhnikov
The article provides a method of formation of the sum code with minimum total number of undetectable errors in data vectors. The idea of building this code is based on the principle of weighing of data vector bits, obtaining the weight of data vector and following modifications of its value. New code has the same number of bits in check vectors, as classic Berger code, however, it also has high detection ability and, that is by no means unimportant, in the area of low multiplicities. The article gives the description of modified weight-based sum code characteristics, as well as the results of experiments for organization of concurrent error detection (CED) systems for the set of reference combinational circuits LGSynth'89.
{"title":"On one method of formation of optimum sum code for technical diagnostics systems","authors":"D. Efanov, V. Sapozhnikov, V. Sapozhnikov","doi":"10.1109/EWDTS.2016.7807633","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807633","url":null,"abstract":"The article provides a method of formation of the sum code with minimum total number of undetectable errors in data vectors. The idea of building this code is based on the principle of weighing of data vector bits, obtaining the weight of data vector and following modifications of its value. New code has the same number of bits in check vectors, as classic Berger code, however, it also has high detection ability and, that is by no means unimportant, in the area of low multiplicities. The article gives the description of modified weight-based sum code characteristics, as well as the results of experiments for organization of concurrent error detection (CED) systems for the set of reference combinational circuits LGSynth'89.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116117208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807640
Hayk Chukhajyan
Most of modern system-on-chip (SoC) contain multiple hierarchy levels. This imposes specific requirements on the test solution, test access mechanism (TAM), and porting of core test patterns. Another challenge for multi-core hierarchical SoCs is the test integration time and automated generation of hierarchical test network and TAM. This paper presents a method for automated generation of core test description. The core test description file transfers the core test information required for automated generation of hierarchical test system. The test description file can contain bulky core-specific information on core test features necessary for hierarchical test. Automated generation of core test description allows drastically reduce hierarchical system generation and integration time.
{"title":"Automated generation of core test description file for hierarchical test","authors":"Hayk Chukhajyan","doi":"10.1109/EWDTS.2016.7807640","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807640","url":null,"abstract":"Most of modern system-on-chip (SoC) contain multiple hierarchy levels. This imposes specific requirements on the test solution, test access mechanism (TAM), and porting of core test patterns. Another challenge for multi-core hierarchical SoCs is the test integration time and automated generation of hierarchical test network and TAM. This paper presents a method for automated generation of core test description. The core test description file transfers the core test information required for automated generation of hierarchical test system. The test description file can contain bulky core-specific information on core test features necessary for hierarchical test. Automated generation of core test description allows drastically reduce hierarchical system generation and integration time.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117132969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807662
Artur Ziarmand, D. Kucherenko, Tetiana Soklakova
The purpose of this article is a review of technologies, algorithms and models of monitoring and control systems of urban transportation systems, companies and their developments in this field in the world, as well as the study of currently existing methods of communication between vehicles, road infrastructure objects and the server or the cloud side where further processing of the data may take place and displaying it in real time. There are also considered available communication protocols necessary for the creation of cyber-physical systems for road traffic management.
{"title":"Transport monitoring and control systems","authors":"Artur Ziarmand, D. Kucherenko, Tetiana Soklakova","doi":"10.1109/EWDTS.2016.7807662","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807662","url":null,"abstract":"The purpose of this article is a review of technologies, algorithms and models of monitoring and control systems of urban transportation systems, companies and their developments in this field in the world, as well as the study of currently existing methods of communication between vehicles, road infrastructure objects and the server or the cloud side where further processing of the data may take place and displaying it in real time. There are also considered available communication protocols necessary for the creation of cyber-physical systems for road traffic management.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124169872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807699
S. Klevtsov
Model and algorithm of warning about the dangerous change in the parameter of the technical object designed. The algorithm is based on the diagrams constructed and operates in real time. Local array of time series points characterizing parameter chart forms. Each point on the graph the current value of the parameter and the following parameter value is formed. The time window is determined first. Array cut time window that moves along the time series. The sensor data in the process of forming a time series are used. Determination of dangerous changes in the parameters is carried out using a modified neural network.
{"title":"Determination jump monitored parameter using a neural network","authors":"S. Klevtsov","doi":"10.1109/EWDTS.2016.7807699","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807699","url":null,"abstract":"Model and algorithm of warning about the dangerous change in the parameter of the technical object designed. The algorithm is based on the diagrams constructed and operates in real time. Local array of time series points characterizing parameter chart forms. Each point on the graph the current value of the parameter and the following parameter value is formed. The time window is determined first. Array cut time window that moves along the time series. The sensor data in the process of forming a time series are used. Determination of dangerous changes in the parameters is carried out using a modified neural network.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121578498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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