Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807736
A. Kamkin, M. Lebedev, S. Smolov
This paper describes a model-based functional test generation method for hardware designs. The main principles are as follows. Two models are extracted from an HDL description: a functional model, which represents the design under scrutiny, and a coverage model, which represents a set of testing goals. Each goal is specified in the negative form to force a model checker to find a counterexample - an execution of the functional model that violates the given property, and thus reaches the testing goal. The coverage criterion is defined on top of extended finite state machines derived from a design's source code. Experiments have shown the method flexibility and effectiveness.
{"title":"An EFSM-driven and model checking-based approach to functional test generation for hardware designs","authors":"A. Kamkin, M. Lebedev, S. Smolov","doi":"10.1109/EWDTS.2016.7807736","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807736","url":null,"abstract":"This paper describes a model-based functional test generation method for hardware designs. The main principles are as follows. Two models are extracted from an HDL description: a functional model, which represents the design under scrutiny, and a coverage model, which represents a set of testing goals. Each goal is specified in the negative form to force a model checker to find a counterexample - an execution of the functional model that violates the given property, and thus reaches the testing goal. The coverage criterion is defined on top of extended finite state machines derived from a design's source code. Experiments have shown the method flexibility and effectiveness.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122004474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807663
A. Makarevich
MOOCs (Massive Open Online Courses) have changed the approach to education forever. With all the benefits that they brought they also revealed a lot of problems in the brick-and-mortar universities. It turned out that the courses in the latter were often outdated, irrelevant or simply not as good as the online ones. MOOCs set up the natural competition between the educational institutions. Thus there emerged a need for the quality assessment systems that can help to evaluate and improve the current courses. The article describes the first stage of the implementation of such a system as a part of the Smart Cyber University project. The solution offered is a framework that allows measuring the efficiency of the educational process in real-time and make decisions based on the obtained results. The prototype is now being developed and tested at Kharkiv National University of Radio Electronics by Anastasia Makarevich and Roman Suvorov.
大规模在线开放课程(Massive Open Online Courses，简称MOOCs)已经彻底改变了教育方式。他们带来的好处，他们也暴露了许多问题在实体大学。事实证明，后者的课程往往是过时的、不相关的，或者根本没有在线课程好。mooc建立了教育机构之间的自然竞争。因此，有必要建立质量评估系统，以帮助评价和改进目前的课程。本文描述了该系统作为智能网络大学项目的一部分的第一阶段实施。提供的解决方案是一个框架，允许实时测量教育过程的效率，并根据获得的结果做出决策。样机目前正在哈尔科夫国立无线电电子大学由Anastasia Makarevich和Roman Suvorov开发和测试。
{"title":"Feedback cloud service for the smart cyber university","authors":"A. Makarevich","doi":"10.1109/EWDTS.2016.7807663","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807663","url":null,"abstract":"MOOCs (Massive Open Online Courses) have changed the approach to education forever. With all the benefits that they brought they also revealed a lot of problems in the brick-and-mortar universities. It turned out that the courses in the latter were often outdated, irrelevant or simply not as good as the online ones. MOOCs set up the natural competition between the educational institutions. Thus there emerged a need for the quality assessment systems that can help to evaluate and improve the current courses. The article describes the first stage of the implementation of such a system as a part of the Smart Cyber University project. The solution offered is a framework that allows measuring the efficiency of the educational process in real-time and make decisions based on the obtained results. The prototype is now being developed and tested at Kharkiv National University of Radio Electronics by Anastasia Makarevich and Roman Suvorov.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127774841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807622
D. Efanov, V. Sapozhnikov, V. Sapozhnikov
The article provides the method of concurrent error detection (CED) system organisation, based on the constant-weight 1/3-code, with outputs of testing logic circuit combined into groups by 3 outputs. The authors provide the calculation formulas of check functions of complements, that allow not only to form the set of testing combinations for «1-out-of-3»-code (1/3-code) checker, but also to form the set of testing combinations for all modulo-two adders in the structure of CED system. The article also gives the conditions of providing the total self-checking of the structure, as well as recommendations for using this method with the number of check circuit outputs m>3.
{"title":"Methods of organization of totally self-checking concurrent error detection system on the basis of constant-weight «1-out-of-3»-code","authors":"D. Efanov, V. Sapozhnikov, V. Sapozhnikov","doi":"10.1109/EWDTS.2016.7807622","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807622","url":null,"abstract":"The article provides the method of concurrent error detection (CED) system organisation, based on the constant-weight 1/3-code, with outputs of testing logic circuit combined into groups by 3 outputs. The authors provide the calculation formulas of check functions of complements, that allow not only to form the set of testing combinations for «1-out-of-3»-code (1/3-code) checker, but also to form the set of testing combinations for all modulo-two adders in the structure of CED system. The article also gives the conditions of providing the total self-checking of the structure, as well as recommendations for using this method with the number of check circuit outputs m>3.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120958124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807658
D. Babayan, E. Babayan, P. Petrosyan, A. Tumanyan, E. Kagramanyan, Tigran Hakhverdyan
Currently the advancement in widespread use of portable devices significantly increases importance of low power design of ICs using different low power techniques, such as power gating, multi voltage etc. Most of these techniques rely on different supply schemes for different areas and blocks of an IC to reduce dynamic and/or static (leakage) power. Thus these techniques are mostly applicable to Systems-On-Chip (SoCs) and their components, such as analog IPs and digital cores. This paper presents area and power optimization approach implemented on simple RISC core ready to be integrated into SoC. Proposed approach uses combination of several low power techniques to achieve desired result for custom-developed RISC core. Results present significant power reduction with acceptable high performance.
{"title":"1.9 GHz 1.05V 16-bit RISC core for high density and low power operation in 28nm technology","authors":"D. Babayan, E. Babayan, P. Petrosyan, A. Tumanyan, E. Kagramanyan, Tigran Hakhverdyan","doi":"10.1109/EWDTS.2016.7807658","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807658","url":null,"abstract":"Currently the advancement in widespread use of portable devices significantly increases importance of low power design of ICs using different low power techniques, such as power gating, multi voltage etc. Most of these techniques rely on different supply schemes for different areas and blocks of an IC to reduce dynamic and/or static (leakage) power. Thus these techniques are mostly applicable to Systems-On-Chip (SoCs) and their components, such as analog IPs and digital cores. This paper presents area and power optimization approach implemented on simple RISC core ready to be integrated into SoC. Proposed approach uses combination of several low power techniques to achieve desired result for custom-developed RISC core. Results present significant power reduction with acceptable high performance.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131144469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807741
A. Timoshenko, K. Lomovskaya, Aleksandr Levanov, E. Borodulin, E. Belousov
This article presents the design and analysis for a flexible antenna prototype. The polyimide-based flexible antenna was designed for the 5 GHz 802.11 standard. Worst-case scenario analysis with technological variables such as substrate thickness, loss tangent, relative dielectric constant, metal layer thickness, and configuration was used to prepare an adaptive process-independent technique for control and correction of the models used for parameter calculations.
{"title":"Analysis and design of planar flexible antenna prototype","authors":"A. Timoshenko, K. Lomovskaya, Aleksandr Levanov, E. Borodulin, E. Belousov","doi":"10.1109/EWDTS.2016.7807741","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807741","url":null,"abstract":"This article presents the design and analysis for a flexible antenna prototype. The polyimide-based flexible antenna was designed for the 5 GHz 802.11 standard. Worst-case scenario analysis with technological variables such as substrate thickness, loss tangent, relative dielectric constant, metal layer thickness, and configuration was used to prepare an adaptive process-independent technique for control and correction of the models used for parameter calculations.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"765 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116411409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807653
N. Fedorenko, L. Lutay, V. Kharchenko, Ye. Yehorova
The article describes the automated informational and analytical system of a decision support in neural network diagnosis of diseases. The operation of the system is based on multi-level method of accounting management, analysis, generalization and exchange of experience between hierarchically organized geographically distributed medical centers. The Selecting of necessary settings for relearning of networks is carried out with the participation of a physician and includes learning procedures, modification and filtering parameters used as input for the further learning of local and regional neural network modules. The procedure of relearning the network of adaptive neural network modules is based on information. The developed system allows considering regional factors of diseases and individual characteristics of diagnosed parameters of patients in the diagnosis of diseases.
{"title":"The processing of the diagnostic data in a medical information-analytical system using a network of neuro modules with relearning","authors":"N. Fedorenko, L. Lutay, V. Kharchenko, Ye. Yehorova","doi":"10.1109/EWDTS.2016.7807653","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807653","url":null,"abstract":"The article describes the automated informational and analytical system of a decision support in neural network diagnosis of diseases. The operation of the system is based on multi-level method of accounting management, analysis, generalization and exchange of experience between hierarchically organized geographically distributed medical centers. The Selecting of necessary settings for relearning of networks is carried out with the participation of a physician and includes learning procedures, modification and filtering parameters used as input for the further learning of local and regional neural network modules. The procedure of relearning the network of adaptive neural network modules is based on information. The developed system allows considering regional factors of diseases and individual characteristics of diagnosed parameters of patients in the diagnosis of diseases.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807713
D. Efanov, V. Sapozhnikov, V. Sapozhnikov
The authors of this article proposed a new universal algorithm of building modified sum codes, that generalizes known methods of code formation, as well as allows to build new sum codes, implementation of which might be useful for technical diagnostics problems solving. The algorithm is based on segregation of bits into a data vector and its division onto two subsets (possibly intersecting), on the following formation of two vectors and on the calculation of the total weight values for each vector using pre-established moduli (on determination of least non-negative residue of each vector's weight). The final step of this code formation is recording in binary form into the bits of check vector the obtained values of least non-negative residue of two vectors weights for bit subset of initial data vector. The proposed algorithm is analyzed using, as an example, the formation of a new sum code with 6 data bits.
{"title":"Generic two-modulus sum codes for technical diagnostics of discrete systems problems","authors":"D. Efanov, V. Sapozhnikov, V. Sapozhnikov","doi":"10.1109/EWDTS.2016.7807713","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807713","url":null,"abstract":"The authors of this article proposed a new universal algorithm of building modified sum codes, that generalizes known methods of code formation, as well as allows to build new sum codes, implementation of which might be useful for technical diagnostics problems solving. The algorithm is based on segregation of bits into a data vector and its division onto two subsets (possibly intersecting), on the following formation of two vectors and on the calculation of the total weight values for each vector using pre-established moduli (on determination of least non-negative residue of each vector's weight). The final step of this code formation is recording in binary form into the bits of check vector the obtained values of least non-negative residue of two vectors weights for bit subset of initial data vector. The proposed algorithm is analyzed using, as an example, the formation of a new sum code with 6 data bits.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122350454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807721
A. Tatarnikov
The paper proposes an approach to instruction stream generation for verification of microprocessor designs. The approach is based on using formal specifications of the instruction set architecture as a source of knowledge about the design under verification. This knowledge is processed with generic engines implementing an extensible set of generation strategies to produce stimuli in the form of instruction sequences. Generation tasks are formulated using high-level descriptions that specify target instructions and strategies of sequence construction and data generation. This provides a flexible way to generate deterministic, random and constraint-based stimuli for verification of arbitrary architectures with minimum effort. The proposed approach has been successfully applied in industrial projects for verification of ARMv8 and MIPS64 microprocessor designs.
{"title":"An approach to instruction stream generation for functional verification of microprocessor designs","authors":"A. Tatarnikov","doi":"10.1109/EWDTS.2016.7807721","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807721","url":null,"abstract":"The paper proposes an approach to instruction stream generation for verification of microprocessor designs. The approach is based on using formal specifications of the instruction set architecture as a source of knowledge about the design under verification. This knowledge is processed with generic engines implementing an extensible set of generation strategies to produce stimuli in the form of instruction sequences. Generation tasks are formulated using high-level descriptions that specify target instructions and strategies of sequence construction and data generation. This provides a flexible way to generate deterministic, random and constraint-based stimuli for verification of arbitrary architectures with minimum effort. The proposed approach has been successfully applied in industrial projects for verification of ARMv8 and MIPS64 microprocessor designs.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125055150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807724
O. Dvornikov, N. Prokopenko, I. Pakhomov, A. Bugakova
The array chip AC-1.3 (OJSC “Integral” Minsk, Belarus) is a base for construction of more than 20 integrated circuits (ICs) for the goals of tool engineering and diagnostics. The article presents the results obtained in experimental studies of the effects of low-temperatures (up to minus -190°C and radiation on the DC characteristics and the current gain (β) of n-p-n and p-n-p bipolar transistors and also JFETs, which contain AC-1.3 in their structure. The paper gives design recommendations for new semi custom microcircuits based on AC-1.3, operating in space conditions.
{"title":"The analog array chip AC-1.3 for the tasks of tool engineering in conditions of cryogenic temperature, neutron flux and cumulative radiation dose effects","authors":"O. Dvornikov, N. Prokopenko, I. Pakhomov, A. Bugakova","doi":"10.1109/EWDTS.2016.7807724","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807724","url":null,"abstract":"The array chip AC-1.3 (OJSC “Integral” Minsk, Belarus) is a base for construction of more than 20 integrated circuits (ICs) for the goals of tool engineering and diagnostics. The article presents the results obtained in experimental studies of the effects of low-temperatures (up to minus -190°C and radiation on the DC characteristics and the current gain (β) of n-p-n and p-n-p bipolar transistors and also JFETs, which contain AC-1.3 in their structure. The paper gives design recommendations for new semi custom microcircuits based on AC-1.3, operating in space conditions.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129038104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/EWDTS.2016.7807634
Vazgen Melikyan, E. Babayan, Tigran Khazhakyan, Sergey Manukyan
In modern System on Chips (SoCs) different blocks may use clock signals with different frequencies, in which case SoC is said to have multiple clock domains. The signal that travels from one clock domain to another needs to be synchronized in the receiving domain to prevent occurrence of metastability phenomenon, i.e. a degradation of a signal. Synchronization is implemented by so called synchronizing devices, which are a set of flip-flops in a certain configuration. This paper researches timing characteristics and power consumption of different types of synchronizers by using elements from SAED32/28nm Educational Design Kit (EDK).
{"title":"Analysis of the impact of metastability phenomenon on the latency and power consumption of synchronizer circuits","authors":"Vazgen Melikyan, E. Babayan, Tigran Khazhakyan, Sergey Manukyan","doi":"10.1109/EWDTS.2016.7807634","DOIUrl":"https://doi.org/10.1109/EWDTS.2016.7807634","url":null,"abstract":"In modern System on Chips (SoCs) different blocks may use clock signals with different frequencies, in which case SoC is said to have multiple clock domains. The signal that travels from one clock domain to another needs to be synchronized in the receiving domain to prevent occurrence of metastability phenomenon, i.e. a degradation of a signal. Synchronization is implemented by so called synchronizing devices, which are a set of flip-flops in a certain configuration. This paper researches timing characteristics and power consumption of different types of synchronizers by using elements from SAED32/28nm Educational Design Kit (EDK).","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129896522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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