Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727103
M. Strasser, R. Stradiotto, S. Aresu, K. Puschkarsky, Holger Poehle, W. Gustin
For the reliability assessment of HV depletion NMOS devices, the relevant off-state degradation mechanisms are discussed and quantified on the example of a transistor in a 130 nm power technology. It can be shown that depending on its construction, the transistor can suffer from combined gate and drain voltage stress and that the observed $mathrm{V}_{mathrm{t}mathrm{h}}$ shifts have to be attributed exclusively to the NBTI effect. Furthermore, it is explained by considering possible circuit applications that this NBTI degradation mechanism can be critical causing significant leakage increase or even unintended device turn-on over lifetime. Finally, as a prevention measure, fluorine implantation into the gate oxide for improving the device reliability with respect to the NBTI effect is investigated.
{"title":"Relevance of off-state NBTI degradation in depletion HVNMOS transistor for power application","authors":"M. Strasser, R. Stradiotto, S. Aresu, K. Puschkarsky, Holger Poehle, W. Gustin","doi":"10.1109/IIRW.2018.8727103","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727103","url":null,"abstract":"For the reliability assessment of HV depletion NMOS devices, the relevant off-state degradation mechanisms are discussed and quantified on the example of a transistor in a 130 nm power technology. It can be shown that depending on its construction, the transistor can suffer from combined gate and drain voltage stress and that the observed $mathrm{V}_{mathrm{t}mathrm{h}}$ shifts have to be attributed exclusively to the NBTI effect. Furthermore, it is explained by considering possible circuit applications that this NBTI degradation mechanism can be critical causing significant leakage increase or even unintended device turn-on over lifetime. Finally, as a prevention measure, fluorine implantation into the gate oxide for improving the device reliability with respect to the NBTI effect is investigated.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117225368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727081
M. Vandemaele, B. Kaczer, Z. Stanojević, S. Tyaginov, A. Makarov, A. Chasin, H. Mertens, D. Linten, G. Groeseneken
Hot-carrier degradation (HCD) is again becoming a growing VLSI reliability problem. This work reports hot-carrier simulations for Si nanowire field-effect transistors (NW FETs) based on the carrier energy distribution function (DF) and compares the results to measured data. The importance of impact ionization for HCD simulations is discussed. A 1-to-1 relation between the extent of interface defects generated by hot-carriers in the channel and the degradation of several FET parameters is observed.
{"title":"Distribution Function Based Simulations of Hot-Carrier Degradation in Nanowire FETs","authors":"M. Vandemaele, B. Kaczer, Z. Stanojević, S. Tyaginov, A. Makarov, A. Chasin, H. Mertens, D. Linten, G. Groeseneken","doi":"10.1109/IIRW.2018.8727081","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727081","url":null,"abstract":"Hot-carrier degradation (HCD) is again becoming a growing VLSI reliability problem. This work reports hot-carrier simulations for Si nanowire field-effect transistors (NW FETs) based on the carrier energy distribution function (DF) and compares the results to measured data. The importance of impact ionization for HCD simulations is discussed. A 1-to-1 relation between the extent of interface defects generated by hot-carriers in the channel and the degradation of several FET parameters is observed.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727093
P. Paliwoda, Z. Chbili, A. Kerber, T. Nigam, D. Singh, K. Nagahiro, P. P. Manik, S. Cimino, D. Misra
This paper discusses the impact of self-heating (SH) on ring-oscillator (RO) reliability and its correlation to hot carrier (HC) degradation. We show that HC degradation modulation due to SH is only significant for logic PFETs at highly accelerated conditions. We show that these SH effects on HC are greatly reduced at moderate acceleration. By stressing the ROs at extreme conditions, we show that the SH impact on HC does not affect RO degradation.
{"title":"Self-Heating Effects on Hot Carrier Degradation and its Impact on Ring-Oscillator Reliability","authors":"P. Paliwoda, Z. Chbili, A. Kerber, T. Nigam, D. Singh, K. Nagahiro, P. P. Manik, S. Cimino, D. Misra","doi":"10.1109/IIRW.2018.8727093","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727093","url":null,"abstract":"This paper discusses the impact of self-heating (SH) on ring-oscillator (RO) reliability and its correlation to hot carrier (HC) degradation. We show that HC degradation modulation due to SH is only significant for logic PFETs at highly accelerated conditions. We show that these SH effects on HC are greatly reduced at moderate acceleration. By stressing the ROs at extreme conditions, we show that the SH impact on HC does not affect RO degradation.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131011911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727106
Rui Zhang, Kexin Yang, Taizhi Liu, L. Milor
In this paper, a new EM model is proposed to describe the interconnect resistance change. This model consists of a time-dependent hydrostatic stress distribution and resistance shift calculations. Hydrostatic stress is obtained from the solution of material transport equations and suitable boundary conditions. The resistance shift is calculated from the stress distribution, atomic divergence, and a special resistance evaluation methodology. Then the calibrated EM model is applied to simulation for a FinFET SRAM array while considering process parameter variations. EM effects on SRAM performance degradation are analyzed.
{"title":"New Electromigration Model and Its Potential Application on Degradation Simulation for FinFET SRAM","authors":"Rui Zhang, Kexin Yang, Taizhi Liu, L. Milor","doi":"10.1109/IIRW.2018.8727106","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727106","url":null,"abstract":"In this paper, a new EM model is proposed to describe the interconnect resistance change. This model consists of a time-dependent hydrostatic stress distribution and resistance shift calculations. Hydrostatic stress is obtained from the solution of material transport equations and suitable boundary conditions. The resistance shift is calculated from the stress distribution, atomic divergence, and a special resistance evaluation methodology. Then the calibrated EM model is applied to simulation for a FinFET SRAM array while considering process parameter variations. EM effects on SRAM performance degradation are analyzed.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131122051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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