Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727079
M. Ring, B. Cowell, D. Moore, J. Gambino
Power semiconductors used in automotive applications are exposed to higher temperatures and higher currents than devices used in consumer products. The qualification of these devices includes power-temperature cycling (PTC) stresses on fully integrated structures. The PTC stresses are time consuming and can require device redesign if fails are observed. In this report, we show that PTC stresses using simple test structures can be used to quickly test the interconnects and wire bonds, and thereby highlight weak links in the process.
{"title":"Fast Power-Temperature Cycling of BEOL Test Structures for Power Devices","authors":"M. Ring, B. Cowell, D. Moore, J. Gambino","doi":"10.1109/IIRW.2018.8727079","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727079","url":null,"abstract":"Power semiconductors used in automotive applications are exposed to higher temperatures and higher currents than devices used in consumer products. The qualification of these devices includes power-temperature cycling (PTC) stresses on fully integrated structures. The PTC stresses are time consuming and can require device redesign if fails are observed. In this report, we show that PTC stresses using simple test structures can be used to quickly test the interconnects and wire bonds, and thereby highlight weak links in the process.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"38 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120982620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727088
J. M. Passage, S. Rogalskyj, N. Azhari, E. Wilcox, J. Lloyd
Accelerated electromigration (EM) testing generally utilizes a constant direct current (DC). However, in operation or “real life” the metal interconnect is commonly exposed to an alternating current (AC) or pulsed direct current (PDC). If at all, compensation for the use of PDC failure is measured by the ‘time-on’ current stress and then modeled as a linear multiple of the duty cycle (percentage of time-on current) [1], [2]. EM life-time is determined by an electromigration driving force as well as a current-induced mechanical stress gradient driving force. In the event current was interrupted or turned off for a period, the stress gradient driving force would continue to act. In the event a void is nucleated, the stress gradient that once opposed EM, would work in the same direction.We studied the failure of copper interconnects using a low frequency pulsed direct current, 10 Hz. We investigated the effects of the duty cycle, and current on the EM failure behavior using PDC and compared the results to accelerated testing preformed with constant direct current. From the comparison of PDC and DC accelerated testing, it is shown that at low current densities, PDC stressed devices show extended lifetime of interconnects and at high current densities (above 8 MA/cm2), they showed a reduced lifetime of the interconnects.
{"title":"Investigation of the effects of Pulsed Direct Current at low frequencies on the Electromigration Lifetime : Student Paper","authors":"J. M. Passage, S. Rogalskyj, N. Azhari, E. Wilcox, J. Lloyd","doi":"10.1109/IIRW.2018.8727088","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727088","url":null,"abstract":"Accelerated electromigration (EM) testing generally utilizes a constant direct current (DC). However, in operation or “real life” the metal interconnect is commonly exposed to an alternating current (AC) or pulsed direct current (PDC). If at all, compensation for the use of PDC failure is measured by the ‘time-on’ current stress and then modeled as a linear multiple of the duty cycle (percentage of time-on current) [1], [2]. EM life-time is determined by an electromigration driving force as well as a current-induced mechanical stress gradient driving force. In the event current was interrupted or turned off for a period, the stress gradient driving force would continue to act. In the event a void is nucleated, the stress gradient that once opposed EM, would work in the same direction.We studied the failure of copper interconnects using a low frequency pulsed direct current, 10 Hz. We investigated the effects of the duty cycle, and current on the EM failure behavior using PDC and compared the results to accelerated testing preformed with constant direct current. From the comparison of PDC and DC accelerated testing, it is shown that at low current densities, PDC stressed devices show extended lifetime of interconnects and at high current densities (above 8 MA/cm2), they showed a reduced lifetime of the interconnects.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126063405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727098
R. Lajmi, F. Cacho, V. Knopik, P. Cathelin, J. Lugo, P. Benech, E. L. Larroze, S. Bourdel, X. Federspiel
Due to its high power efficiency, Class A power amplifier (PA) is a good candidate for low-cost, high integration portable communication systems, Bluetooth applications and wireless networks. It's well known that the capability of the power amplifier to deliver the output power will change in time due to the effects of Hot Carrier Injection (HCI) in CMOS transistors. In this work, investigation of power amplifier aging will be shown in the first part and compensation scheme of degraded performance using a power detector will be illustrated in the second part.
{"title":"Aging control of power amplifier using power detector","authors":"R. Lajmi, F. Cacho, V. Knopik, P. Cathelin, J. Lugo, P. Benech, E. L. Larroze, S. Bourdel, X. Federspiel","doi":"10.1109/IIRW.2018.8727098","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727098","url":null,"abstract":"Due to its high power efficiency, Class A power amplifier (PA) is a good candidate for low-cost, high integration portable communication systems, Bluetooth applications and wireless networks. It's well known that the capability of the power amplifier to deliver the output power will change in time due to the effects of Hot Carrier Injection (HCI) in CMOS transistors. In this work, investigation of power amplifier aging will be shown in the first part and compensation scheme of degraded performance using a power detector will be illustrated in the second part.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727104
K. Beckmann, W. Olin-Ammentorp, Sierra Russell, Nadia Suguitan, C. Hobbs, M. Rodgers, N. Cady, G. Rose, J. V. Van Nostrand
Resistive random access memory (ReRAM) is a new form of non-volatile memory that has the potential to replace Flash memory or augment the current memory hierarchy. In addition, novel circuit architectures have been proposed that rely on newly discovered or predicted behavior of ReRAM devices. One such architecture is the memristive Dynamic Adaptive Neural Network Array (mrDANNA), developed to emulate the functionality of a biological neural network. This architecture relies on synapses which are capable of changing their resistance in an analog fashion by applying ultra-short pulses. We demonstrate ReRAM devices that show this tendency. The ReRAM devices shown here are based on an HfO2 switching layer that sits on a tungsten bottom electrode, is covered by a titanium oxygen scavenger layer, a titanium nitride top electrode, and are structured to a size of 100×100 nm2. In this work, we show devices that exhibit incremental resistance changes in a synaptic fashion and can switch using pulses as short as 5 ns. A major hurdle is the variability observed with these devices and its effect on the designed mrDANNA architecture. One focus of the ongoing work is a simulation on the effect of the observed variability. For this purpose, a Monte Carlo simulation with extracted variability data are being performed to demonstrate the impact on this neuromorphic architecture.
{"title":"Synaptic Behavior of Nanoscale ReRAM Devices for the Implementation in a Dynamic Neural Network Array","authors":"K. Beckmann, W. Olin-Ammentorp, Sierra Russell, Nadia Suguitan, C. Hobbs, M. Rodgers, N. Cady, G. Rose, J. V. Van Nostrand","doi":"10.1109/IIRW.2018.8727104","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727104","url":null,"abstract":"Resistive random access memory (ReRAM) is a new form of non-volatile memory that has the potential to replace Flash memory or augment the current memory hierarchy. In addition, novel circuit architectures have been proposed that rely on newly discovered or predicted behavior of ReRAM devices. One such architecture is the memristive Dynamic Adaptive Neural Network Array (mrDANNA), developed to emulate the functionality of a biological neural network. This architecture relies on synapses which are capable of changing their resistance in an analog fashion by applying ultra-short pulses. We demonstrate ReRAM devices that show this tendency. The ReRAM devices shown here are based on an HfO2 switching layer that sits on a tungsten bottom electrode, is covered by a titanium oxygen scavenger layer, a titanium nitride top electrode, and are structured to a size of 100×100 nm2. In this work, we show devices that exhibit incremental resistance changes in a synaptic fashion and can switch using pulses as short as 5 ns. A major hurdle is the variability observed with these devices and its effect on the designed mrDANNA architecture. One focus of the ongoing work is a simulation on the effect of the observed variability. For this purpose, a Monte Carlo simulation with extracted variability data are being performed to demonstrate the impact on this neuromorphic architecture.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115378115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727089
J. Franco, Z. Wu, G. Rzepa, L. Ragnarsson, H. Dekkers, A. Vandooren, G. Groeseneken, N. Horiguchi, N. Collaert, D. Linten, T. Grasser, B. Kaczer
We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the metal work function. However, experimental data show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metal stack with the dielectric, yielding different defect profiles depending on the process thermal budget. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy”, we also show that different metal work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.
{"title":"On the Impact of the Gate Metal Work-Function on the Charge Trapping Component of BTI","authors":"J. Franco, Z. Wu, G. Rzepa, L. Ragnarsson, H. Dekkers, A. Vandooren, G. Groeseneken, N. Horiguchi, N. Collaert, D. Linten, T. Grasser, B. Kaczer","doi":"10.1109/IIRW.2018.8727089","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727089","url":null,"abstract":"We investigate BTI charge trapping trends in high-k metal gate (HKMG) stacks with a variety of work function metals. Most BTI models suggest charge trapping in oxide defects is modulated by the applied oxide electric field, which controls the energy barrier for the capture process, irrespective of the metal work function. However, experimental data show enhanced or reduced charge trapping at constant oxide electric field for different work function metal stacks. We ascribe this to a different chemical interaction of the metal stack with the dielectric, yielding different defect profiles depending on the process thermal budget. Furthermore, by employing the imec/T.U. Wien physics-based BTI simulation framework “Comphy”, we also show that different metal work functions within a typical range of relevance (4.35-4.75eV) can yield a different charge state of the deep high-k defects, and can therefore have an impact on charge trapping kinetics during BTI stress, particularly in nMOSFETs.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122524641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727083
S. Tyaginov, M. Jech, G. Rzepa, A. Grill, A. El-Sayed, G. Pobegen, A. Makarov, T. Grasser
We experimentally and theoretically study the impact of interface and border traps on the transfer characteristics of 4H-SiC transistors measured over a wide temperature range of 200-350 K. Quite apparently, the experimental current-voltage characteristics have drain currents which are much lower than those obtained from simulations performed without traps. Moreover, currents increase with temperature over the entire gate voltage range, while the threshold voltage shifts towards lower values as temperature increases. We show that although interface traps can explain ${I}_{{mathrm {d}}}-{V}_{{mathrm {gs}}}$ curves measured at room temperature with good accuracy it fails for lower temperatures. Inclusion of border traps, on the other hand, results in good agreement between experimental and simulated current-voltage characteristics over the entire temperature range. For the first time we were able to successfully represent transfer characteristics of a 4H-SiC transistor at temperatures substantially below 300 K. Therefore, we conclude that border traps are responsible for the complicated behavior of $mathrm{I}_{{mathrm {d}}}-mathrm{V}_{{mathrm {gs}}}$ characteristics.
{"title":"Border Trap Based Modeling of SiC Transistor Transfer Characteristics","authors":"S. Tyaginov, M. Jech, G. Rzepa, A. Grill, A. El-Sayed, G. Pobegen, A. Makarov, T. Grasser","doi":"10.1109/IIRW.2018.8727083","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727083","url":null,"abstract":"We experimentally and theoretically study the impact of interface and border traps on the transfer characteristics of 4H-SiC transistors measured over a wide temperature range of 200-350 K. Quite apparently, the experimental current-voltage characteristics have drain currents which are much lower than those obtained from simulations performed without traps. Moreover, currents increase with temperature over the entire gate voltage range, while the threshold voltage shifts towards lower values as temperature increases. We show that although interface traps can explain ${I}_{{mathrm {d}}}-{V}_{{mathrm {gs}}}$ curves measured at room temperature with good accuracy it fails for lower temperatures. Inclusion of border traps, on the other hand, results in good agreement between experimental and simulated current-voltage characteristics over the entire temperature range. For the first time we were able to successfully represent transfer characteristics of a 4H-SiC transistor at temperatures substantially below 300 K. Therefore, we conclude that border traps are responsible for the complicated behavior of $mathrm{I}_{{mathrm {d}}}-mathrm{V}_{{mathrm {gs}}}$ characteristics.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114316723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727087
F. Sy, Q. Rafhay, C. Besset, G. Beylier, P. Grosse, D. Roy, J. Broquin
In this paper, the reliability of germanium photodiodes of the PIC25G technology for silicon photonic applications is experimentally studied. Using advanced characterization technics, it is shown that the dark current, the photonic current and the cut-off frequency of the photodiode can be degraded during voltage stress of 106 s, which could ultimately induce some device performance drift. The causes of these degradations are presently attributed to interface defects between germanium and SiO2, until more detailed investigation are pursued.
{"title":"Reliability of High Speed Photodetector for Silicon Photonic Applications","authors":"F. Sy, Q. Rafhay, C. Besset, G. Beylier, P. Grosse, D. Roy, J. Broquin","doi":"10.1109/IIRW.2018.8727087","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727087","url":null,"abstract":"In this paper, the reliability of germanium photodiodes of the PIC25G technology for silicon photonic applications is experimentally studied. Using advanced characterization technics, it is shown that the dark current, the photonic current and the cut-off frequency of the photodiode can be degraded during voltage stress of 106 s, which could ultimately induce some device performance drift. The causes of these degradations are presently attributed to interface defects between germanium and SiO2, until more detailed investigation are pursued.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122152654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727066
Deborah Noble, M. Ring, J. Lloyd
The anisotropic nature of tin, the principle component of Pb-free solder, can cause significant variations the physical characteristics of the solder bumps. Grain size and orientation in a solder bump can drastically change the properties of one bump, giving rise to multiple potential failure modes between bumps. Electromigration may take place via grain boundary diffusion in one bump and interstitial diffusion in another. The greater the number of bumps in a test structure, the greater the probability of early failure resulting from large grains oriented in a direction that enables fast diffusion. The lognormal probability of electromigration failures can be expected to follow a linear trend. Deviation from this linear trend for the earliest failures suggests multiple modes of electromigration failure in the solder bump daisy chain.
{"title":"Multiple Modes of Electromigration Failure in SAC Solder Alloys","authors":"Deborah Noble, M. Ring, J. Lloyd","doi":"10.1109/IIRW.2018.8727066","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727066","url":null,"abstract":"The anisotropic nature of tin, the principle component of Pb-free solder, can cause significant variations the physical characteristics of the solder bumps. Grain size and orientation in a solder bump can drastically change the properties of one bump, giving rise to multiple potential failure modes between bumps. Electromigration may take place via grain boundary diffusion in one bump and interstitial diffusion in another. The greater the number of bumps in a test structure, the greater the probability of early failure resulting from large grains oriented in a direction that enables fast diffusion. The lognormal probability of electromigration failures can be expected to follow a linear trend. Deviation from this linear trend for the earliest failures suggests multiple modes of electromigration failure in the solder bump daisy chain.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123259862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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