Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727085
J. Strand, A. Shluger
Spatially correlated defect generation process has been proposed to be responsible for TDDB Weibull slope measured in HfO2. We investigated possible mechanisms for correlated defect production in amorphous (a) HfO2 films under applied stress bias using ab initio simulations. During bias application, electron injection into these films leads to the localization of up to two electrons at intrinsic trapping sites present due to the structural disorder in amorphous structures and to formation of O vacancies. Trapping of two extra electrons at a pre-exiting O vacancy facilitate the formation of a new vacancies affecting TDDB statistics and its dependence on the film thickness.
{"title":"Correlated Defect Creation in HfO2 films","authors":"J. Strand, A. Shluger","doi":"10.1109/IIRW.2018.8727085","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727085","url":null,"abstract":"Spatially correlated defect generation process has been proposed to be responsible for TDDB Weibull slope measured in HfO2. We investigated possible mechanisms for correlated defect production in amorphous (a) HfO2 films under applied stress bias using ab initio simulations. During bias application, electron injection into these films leads to the localization of up to two electrons at intrinsic trapping sites present due to the structural disorder in amorphous structures and to formation of O vacancies. Trapping of two extra electrons at a pre-exiting O vacancy facilitate the formation of a new vacancies affecting TDDB statistics and its dependence on the film thickness.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125391402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727080
Shu-Han Hsu, Kexin Yang, Rui Zhang, L. Milor
Lifetime testing of circuits is challenging because of the need to design circuit-specific test structures and test patterns. The goal of this work is to find a ring oscillator that matches a circuit’s wearout behavior limited by time-dependent dielectric breakdown (TDDB), electromigration (EM), and stress-induced voiding (SIV) lifetime distributions, which can be used to foreworn circuit breakdown. The equivalent ring oscillator is easier to test, enabling the collection of more experimental lifetime data. Therefore, this paper aims to find the appropriate ring oscillator for a target circuit by mapping the lifetime of a circuit to a ring oscillator using analytical equations that involve layout parameters (area, length, width of device and interconnect) and operating conditions (supply voltage, temperature, probability of stress, current). Practical ring oscillator equations for lifetime estimation were derived, which describe relationships between stage number, oscillation frequency, characteristic lifetime, and Weibull parameters. The methodology is illustrated with example circuits that were implemented with 14nm FinFET technology.
{"title":"Lifetime Estimation Using Ring Oscillators for Prediction in FinFET Technology","authors":"Shu-Han Hsu, Kexin Yang, Rui Zhang, L. Milor","doi":"10.1109/IIRW.2018.8727080","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727080","url":null,"abstract":"Lifetime testing of circuits is challenging because of the need to design circuit-specific test structures and test patterns. The goal of this work is to find a ring oscillator that matches a circuit’s wearout behavior limited by time-dependent dielectric breakdown (TDDB), electromigration (EM), and stress-induced voiding (SIV) lifetime distributions, which can be used to foreworn circuit breakdown. The equivalent ring oscillator is easier to test, enabling the collection of more experimental lifetime data. Therefore, this paper aims to find the appropriate ring oscillator for a target circuit by mapping the lifetime of a circuit to a ring oscillator using analytical equations that involve layout parameters (area, length, width of device and interconnect) and operating conditions (supply voltage, temperature, probability of stress, current). Practical ring oscillator equations for lifetime estimation were derived, which describe relationships between stage number, oscillation frequency, characteristic lifetime, and Weibull parameters. The methodology is illustrated with example circuits that were implemented with 14nm FinFET technology.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126689290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727084
G. Yao, Z. Han, H. Yap, F. P. Yuen, C. Tan, P. Tan, P. Paliwoda, C. Eng
In this work, we explore the effect of different IMD deposition tools on the occurrence of early electromigration (EM) failure. The failure is revealed by the fast Wafer Level Reliability (fWLR) method. It is found that under the same embedded IMD scheme (i.e. HDP FSG and then TEOS USG), the initial HDP FSG film deposition condition is the main cause for fWLR-EM early failure. It deteriorates subsequent USG film stress and imposes the stress on metal layers. This is also confirmed by Package Level Reliability EM (PLR-EM). Moreover, by understanding reliability risk caused by initial FSG film quality, we performed recipe improvement experiments and obtained better EM performance. The fWLR method proves its fast and accurate characterization capabilities in process development and monitoring.
{"title":"Process Optimization in IMD Deposition: A Sucessful Application of Isothermal Fast Wafer-Level Electromigration","authors":"G. Yao, Z. Han, H. Yap, F. P. Yuen, C. Tan, P. Tan, P. Paliwoda, C. Eng","doi":"10.1109/IIRW.2018.8727084","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727084","url":null,"abstract":"In this work, we explore the effect of different IMD deposition tools on the occurrence of early electromigration (EM) failure. The failure is revealed by the fast Wafer Level Reliability (fWLR) method. It is found that under the same embedded IMD scheme (i.e. HDP FSG and then TEOS USG), the initial HDP FSG film deposition condition is the main cause for fWLR-EM early failure. It deteriorates subsequent USG film stress and imposes the stress on metal layers. This is also confirmed by Package Level Reliability EM (PLR-EM). Moreover, by understanding reliability risk caused by initial FSG film quality, we performed recipe improvement experiments and obtained better EM performance. The fWLR method proves its fast and accurate characterization capabilities in process development and monitoring.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131109647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727095
F. Puglisi, Marco Ghillini, L. Larcher, P. Pavan
In recent times many systems in a wide range of application fields (e.g., health, material science, security, and communications) exploit the mm- and sub-mm-wave spectrum, which dramatically sped up the growth of the BiCMOS technology integrating silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) and passives. Today, the reliability of such devices is of primary concern, and particular attention is given to the device self-heating (SH), the importance of which is supposed to increase with the device scaling. In this work we develop a TCAD model for SiGe HBT devices that is used to investigate the SH effects in SiGe HBTs both in operating and stress conditions. We underline the different role played by impact ionization and carriers’ and lattice heating on the device degradation. Results show the important role played by the backend-of-line (BEOL) and by the substrate thermal resistance in dissipating the heat generated by impact ionization and hotcarriers. Simulations of the SH effects in stress conditions excluded annealing as the possible reason for the degradation dynamics reported in the literature, while simulations of stressed devices in measurement conditions revealed the presence of a hole hot spot that suggests a possible physical mechanism involved in the degradation slowdown at long stress times reported in the literature.
{"title":"Self-Heating Effect in Silicon-Germanium Heterostructure Bipolar Transistors in Stress and Operating Conditions","authors":"F. Puglisi, Marco Ghillini, L. Larcher, P. Pavan","doi":"10.1109/IIRW.2018.8727095","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727095","url":null,"abstract":"In recent times many systems in a wide range of application fields (e.g., health, material science, security, and communications) exploit the mm- and sub-mm-wave spectrum, which dramatically sped up the growth of the BiCMOS technology integrating silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) and passives. Today, the reliability of such devices is of primary concern, and particular attention is given to the device self-heating (SH), the importance of which is supposed to increase with the device scaling. In this work we develop a TCAD model for SiGe HBT devices that is used to investigate the SH effects in SiGe HBTs both in operating and stress conditions. We underline the different role played by impact ionization and carriers’ and lattice heating on the device degradation. Results show the important role played by the backend-of-line (BEOL) and by the substrate thermal resistance in dissipating the heat generated by impact ionization and hotcarriers. Simulations of the SH effects in stress conditions excluded annealing as the possible reason for the degradation dynamics reported in the literature, while simulations of stressed devices in measurement conditions revealed the presence of a hole hot spot that suggests a possible physical mechanism involved in the degradation slowdown at long stress times reported in the literature.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114919663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727102
C. Zambelli, L. Crippa, R. Micheloni, P. Olivo
The cross-temperature effect in NAND Flash memories has always been a concern since the early developments of the planar technology. The sensing of the data at a temperature different from that used during programming is a source of a large number of failed bits, leading to unrecoverable data corruption even using well-known error correction codes. In this work, we show that this issue is still present in 3D NAND Flash technology, though with different peculiarities due to the different materials used for the channel in the memory cells. The characterization of the fail bits count distributions as a function of the temperature combinations of program and read will expose that the most critical condition is that where program temperature is higher than the read one, therefore requiring special care at system-level to handle the increased errors number (i.e., using secondary correction mechanisms like soft decoding or read retry).
{"title":"Cross-Temperature Effects of Program and Read Operations in 2D and 3D NAND Flash Memories","authors":"C. Zambelli, L. Crippa, R. Micheloni, P. Olivo","doi":"10.1109/IIRW.2018.8727102","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727102","url":null,"abstract":"The cross-temperature effect in NAND Flash memories has always been a concern since the early developments of the planar technology. The sensing of the data at a temperature different from that used during programming is a source of a large number of failed bits, leading to unrecoverable data corruption even using well-known error correction codes. In this work, we show that this issue is still present in 3D NAND Flash technology, though with different peculiarities due to the different materials used for the channel in the memory cells. The characterization of the fail bits count distributions as a function of the temperature combinations of program and read will expose that the most critical condition is that where program temperature is higher than the read one, therefore requiring special care at system-level to handle the increased errors number (i.e., using secondary correction mechanisms like soft decoding or read retry).","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126676133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727091
T. L. Tan, P. Zhou, L. Cao, P. Tan, P. Paliwoda, C. Eng
Plasma induced charging is known to cause gate oxide and MIM capacitor reliability degradation. However, the impact of plasma induced charging on metal/via is rarely reported. This paper highlights the importance of built-in-reliability during design of via connections to gate poly. Large gate oxide area per via is shown to impact via resistance and reliability. Thus, it is recommended to ground these via or design gate oxide area per via to be less than 600 $u {mathrm{ m}}^{mathbf {2}}$ to minimize the impact.
{"title":"Gate-to-via ratio design for reliability","authors":"T. L. Tan, P. Zhou, L. Cao, P. Tan, P. Paliwoda, C. Eng","doi":"10.1109/IIRW.2018.8727091","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727091","url":null,"abstract":"Plasma induced charging is known to cause gate oxide and MIM capacitor reliability degradation. However, the impact of plasma induced charging on metal/via is rarely reported. This paper highlights the importance of built-in-reliability during design of via connections to gate poly. Large gate oxide area per via is shown to impact via resistance and reliability. Thus, it is recommended to ground these via or design gate oxide area per via to be less than 600 $u {mathrm{ m}}^{mathbf {2}}$ to minimize the impact.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126639800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IIRW.2018.8727096
X. Federspiel, M. Rafik, M. Arabi, A. Cros, F. Cacho
non uniform field TTDB stress have been performed on 28nm FDSOI MOSfet devices. After analysis of thermal effects under increasing drain voltage, as well as potential TDDB-HCI interactions, a complete TTDB model, taking into account non uniform field and self-heating is confronted to experimental data.
{"title":"FDSOI Mosfet gate dielectric breakdown Vd dependancy","authors":"X. Federspiel, M. Rafik, M. Arabi, A. Cros, F. Cacho","doi":"10.1109/IIRW.2018.8727096","DOIUrl":"https://doi.org/10.1109/IIRW.2018.8727096","url":null,"abstract":"non uniform field TTDB stress have been performed on 28nm FDSOI MOSfet devices. After analysis of thermal effects under increasing drain voltage, as well as potential TDDB-HCI interactions, a complete TTDB model, taking into account non uniform field and self-heating is confronted to experimental data.","PeriodicalId":365267,"journal":{"name":"2018 International Integrated Reliability Workshop (IIRW)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125549703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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