Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567628
V. Steel
Commercial packaging of GaAs IC components such as Power Amplifiers requires special care to ensure proper thermal management while maintaining low cost. Several types of packages are investigated for electrical and thermal performance. Some examples of ICs which utilize various types of plastic packages are also discussed.
{"title":"Low cost packaging techniques for commercial GaAs IC components","authors":"V. Steel","doi":"10.1109/GAAS.1996.567628","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567628","url":null,"abstract":"Commercial packaging of GaAs IC components such as Power Amplifiers requires special care to ensure proper thermal management while maintaining low cost. Several types of packages are investigated for electrical and thermal performance. Some examples of ICs which utilize various types of plastic packages are also discussed.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125083291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567843
J. Kotz
This paper describes the measurement and modeling of gate capacitance for self-aligned, LDD GaAs EFETs and DFETs. An improved, scalable gate capacitance model is presented which is suitable for compact device simulation.
{"title":"An improved gate capacitance model for GaAs MESFETs","authors":"J. Kotz","doi":"10.1109/GAAS.1996.567843","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567843","url":null,"abstract":"This paper describes the measurement and modeling of gate capacitance for self-aligned, LDD GaAs EFETs and DFETs. An improved, scalable gate capacitance model is presented which is suitable for compact device simulation.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124507385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567870
K. Kobayashi, J. Cowles, T. Block, A. Oki, D. Streit
Here we report on a 2-50 GHz InAlAs/InGaAs-InP HBT Distributed Amplifier (DA) which demonstrates the highest frequency of operation so far reported for a wideband HBT amplifier and is a 10 GHz (25%) improvement over previous state-of-the-art. The amplifier features 1/spl times/4 /spl mu/m/sup 2/ single-emitter HBTs with a base under-cut structure for reducing the device's collector-base capacitance C/sub bc/, resulting in as much as a 20% improvement in device f/sub max/ performance. The MMIC is a 5-section coplanar waveguide distributed amplifier design which employs HBT cascode devices. Previous work using non-undercut HBTs has resulted in 5.5 dB gain and 2-32 GHz BW performance. In the present work, the HBT DA obtains a peak gain of 6.3 dB with a bandwidth beyond 50 GHz while operating from a 4 V supply and consuming only 89 mW of DC power. The gain is 4.1 dB at 30 GHz, 3.9 dB at 40 GHz and 4 dB at 50 GHz. An open circuit transimpedance of 45 dB-/spl Omega/ calculated from S-parameters is achieved with an upper band edge of >50 GHz. The corresponding effective 5O-/spl Omega/ loaded transimpedance is 39.2 dB-/spl Omega/ also has an upper band edge of >50 GHz. The wideband gain and transimpedance results here benchmark the highest bandwidths so far recorded for either HBT or BJT amplifiers and suggests the capability of InAlAs/InGaAs HBTs for millimeter-wave and high data rate (40 Gbps) IC applications.
{"title":"A 2-50 GHz InAlAs/InGaAs-InP HBT distributed amplifier","authors":"K. Kobayashi, J. Cowles, T. Block, A. Oki, D. Streit","doi":"10.1109/GAAS.1996.567870","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567870","url":null,"abstract":"Here we report on a 2-50 GHz InAlAs/InGaAs-InP HBT Distributed Amplifier (DA) which demonstrates the highest frequency of operation so far reported for a wideband HBT amplifier and is a 10 GHz (25%) improvement over previous state-of-the-art. The amplifier features 1/spl times/4 /spl mu/m/sup 2/ single-emitter HBTs with a base under-cut structure for reducing the device's collector-base capacitance C/sub bc/, resulting in as much as a 20% improvement in device f/sub max/ performance. The MMIC is a 5-section coplanar waveguide distributed amplifier design which employs HBT cascode devices. Previous work using non-undercut HBTs has resulted in 5.5 dB gain and 2-32 GHz BW performance. In the present work, the HBT DA obtains a peak gain of 6.3 dB with a bandwidth beyond 50 GHz while operating from a 4 V supply and consuming only 89 mW of DC power. The gain is 4.1 dB at 30 GHz, 3.9 dB at 40 GHz and 4 dB at 50 GHz. An open circuit transimpedance of 45 dB-/spl Omega/ calculated from S-parameters is achieved with an upper band edge of >50 GHz. The corresponding effective 5O-/spl Omega/ loaded transimpedance is 39.2 dB-/spl Omega/ also has an upper band edge of >50 GHz. The wideband gain and transimpedance results here benchmark the highest bandwidths so far recorded for either HBT or BJT amplifiers and suggests the capability of InAlAs/InGaAs HBTs for millimeter-wave and high data rate (40 Gbps) IC applications.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122948888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567824
R. Yu, R. Pierson, P. Zampardi, K. Runge, A. Campana, D. Meeker, K. Wang, A. Petersen, J. Bowers
Three packaged clock recovery integrated circuits: a differentiate/rectify circuit, a delay/multiply circuit, and a phase detector circuit, were implemented in an advanced AlGaAs-GaAs HBT process. The packaged ICs show performance adequate for clock recovery for optical communication links of up to at least 40 Gbit/s. With a 30 Gbit/s pseudo-random sequence input, a phase-locked loop incorporating these ICs readily acquired and maintained phase lock, demonstrating the excellent system performance of these components.
{"title":"Packaged clock recovery integrated circuits for 40 Gbit/s optical communication links","authors":"R. Yu, R. Pierson, P. Zampardi, K. Runge, A. Campana, D. Meeker, K. Wang, A. Petersen, J. Bowers","doi":"10.1109/GAAS.1996.567824","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567824","url":null,"abstract":"Three packaged clock recovery integrated circuits: a differentiate/rectify circuit, a delay/multiply circuit, and a phase detector circuit, were implemented in an advanced AlGaAs-GaAs HBT process. The packaged ICs show performance adequate for clock recovery for optical communication links of up to at least 40 Gbit/s. With a 30 Gbit/s pseudo-random sequence input, a phase-locked loop incorporating these ICs readily acquired and maintained phase lock, demonstrating the excellent system performance of these components.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130984889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567894
T. Daniel, R. Tayrani
This paper presents a detailed model which accurately predicts DC, small-signal and noise characteristics of AlGaAs-GaAs heterojunction bipolar transistors (HBTs). The features to the DC model are thermionic emission and tunneling effects at the base-emitter junction, calculation of various recombination currents, which contribute to the total base current. We introduce a new set of noise equations, which takes into account the correlation and frequency dependencies of the intrinsic noise sources. Compared to the SPICE noise model, this model provides further improvement in predicting small signal and large signal noise for HBT based circuits. These models can be easily implemented into any SPICE or harmonic balance simulators. The results of our study are validated using devices from different foundries.
{"title":"DC and high frequency models for heterojunction bipolar transistors","authors":"T. Daniel, R. Tayrani","doi":"10.1109/GAAS.1996.567894","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567894","url":null,"abstract":"This paper presents a detailed model which accurately predicts DC, small-signal and noise characteristics of AlGaAs-GaAs heterojunction bipolar transistors (HBTs). The features to the DC model are thermionic emission and tunneling effects at the base-emitter junction, calculation of various recombination currents, which contribute to the total base current. We introduce a new set of noise equations, which takes into account the correlation and frequency dependencies of the intrinsic noise sources. Compared to the SPICE noise model, this model provides further improvement in predicting small signal and large signal noise for HBT based circuits. These models can be easily implemented into any SPICE or harmonic balance simulators. The results of our study are validated using devices from different foundries.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115616430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567869
Y. Suzuki, H. Shimawaki, Y. Amamiya, K. Fukuchi, N. Nagano, H. Yano, K. Honjo
A preamplifier for 40-Gb/s optical transmission systems has been constructed using AlGaAs-InGaAs HBTs with p/sup +/ regrown extrinsic base layers. This preamplifier achieved a bandwidth of 34.6 GHz and a transimpedance gain of 41.6 dB/spl Omega/. This is the widest bandwidth in a preamplifier ever reported. These characteristics are suitable for use in a 40 Gb/s optical receiver. The results indicate that AlGaAs-InGaAs HBTs with p/sup +/ regrown extrinsic base layers are very promising for the implementation of 40 Gb/s optical transmission systems.
{"title":"An HBT preamplifier for 40-Gb/s optical transmission systems","authors":"Y. Suzuki, H. Shimawaki, Y. Amamiya, K. Fukuchi, N. Nagano, H. Yano, K. Honjo","doi":"10.1109/GAAS.1996.567869","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567869","url":null,"abstract":"A preamplifier for 40-Gb/s optical transmission systems has been constructed using AlGaAs-InGaAs HBTs with p/sup +/ regrown extrinsic base layers. This preamplifier achieved a bandwidth of 34.6 GHz and a transimpedance gain of 41.6 dB/spl Omega/. This is the widest bandwidth in a preamplifier ever reported. These characteristics are suitable for use in a 40 Gb/s optical receiver. The results indicate that AlGaAs-InGaAs HBTs with p/sup +/ regrown extrinsic base layers are very promising for the implementation of 40 Gb/s optical transmission systems.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"58 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123385713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567734
G. McMillian, W. Hallidy, M. Hood, G. Phan, Tan Chu, Kim Lau, M. Lawrence, J. Phan, A. Lee, C. Musgrove, M. Sanders, A. Morgan, G. Schmidt, G. Zreet
A single chip digital radio frequency memory (DRFM) modulator provides time delay, Doppler shifting, and phase/amplitude modulation of RF signals. The digital IC has been implemented in Vitesse Semiconductor's H-GaAs III technology for operation up to 500 MHz, and was designed with COMPASS Design Automation's CAE tools and SPEC's standard cell libraries.
{"title":"A 500 MHz GaAs digital RF memory modulator IC","authors":"G. McMillian, W. Hallidy, M. Hood, G. Phan, Tan Chu, Kim Lau, M. Lawrence, J. Phan, A. Lee, C. Musgrove, M. Sanders, A. Morgan, G. Schmidt, G. Zreet","doi":"10.1109/GAAS.1996.567734","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567734","url":null,"abstract":"A single chip digital radio frequency memory (DRFM) modulator provides time delay, Doppler shifting, and phase/amplitude modulation of RF signals. The digital IC has been implemented in Vitesse Semiconductor's H-GaAs III technology for operation up to 500 MHz, and was designed with COMPASS Design Automation's CAE tools and SPEC's standard cell libraries.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121046177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567647
S. Nati, I. Kyles
A gallium arsenide (GaAs) integrated circuit for measuring single shot time intervals with 500 picosecond resolution has been designed, fabricated and tested. The circuit contains a 12 bit counter that can be extended externally and control circuitry for the detection of multiple intervals. Options such as number of intervals, minimum interval time, and timing resolution are user programmable. The circuit employs a self contained 2.0 GHz phase locked loop (PLL) clock synthesizer with less than 5 picoseconds rms jitter, and a lock time of 2.5 microseconds. The circuit is packaged in a 14 mm/sup 2/, 52 pin thermally enhanced plastic package and operates from a single +5 Volt supply. The nominal power dissipation is 2.8 Watts. The circuit is fabricated in a 0.6 micron gate length, enhancement/depletion GaAs MESFET process utilizing 4 layers of gold interconnect metalization. Inductors, capacitors and thin film resistors can be fabricated in this process, enabling integrated analog circuitry. The die size is 3.28 mm by 3.15 mm. The circuit has applications in collision avoidance sensors, laser surveying, police radar, and test.
设计、制作并测试了一种分辨率为500皮秒的砷化镓(GaAs)单次射击时间间隔测量集成电路。该电路包含一个12位计数器，可以扩展到外部和控制电路，用于检测多个间隔。间隔数、最小间隔时间和定时分辨率等选项都是用户可编程的。该电路采用自包含的2.0 GHz锁相环(PLL)时钟合成器，其有效值小于5皮秒，锁定时间为2.5微秒。该电路封装在14 mm/sup 2/， 52引脚热增强塑料封装中，并从单个+5伏电源运行。标称功耗为2.8瓦。该电路采用0.6微米栅极长度，增强/耗尽GaAs MESFET工艺，利用4层金互连金属化。电感、电容器和薄膜电阻器可以在此过程中制造，从而实现集成模拟电路。模具尺寸为3.28 mm × 3.15 mm。该电路应用于防撞传感器、激光测量、警用雷达和测试等领域。
{"title":"A monolithic gallium arsenide interval timer IC with integrated PLL clock synthesis having five hundred picosecond single shot resolution","authors":"S. Nati, I. Kyles","doi":"10.1109/GAAS.1996.567647","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567647","url":null,"abstract":"A gallium arsenide (GaAs) integrated circuit for measuring single shot time intervals with 500 picosecond resolution has been designed, fabricated and tested. The circuit contains a 12 bit counter that can be extended externally and control circuitry for the detection of multiple intervals. Options such as number of intervals, minimum interval time, and timing resolution are user programmable. The circuit employs a self contained 2.0 GHz phase locked loop (PLL) clock synthesizer with less than 5 picoseconds rms jitter, and a lock time of 2.5 microseconds. The circuit is packaged in a 14 mm/sup 2/, 52 pin thermally enhanced plastic package and operates from a single +5 Volt supply. The nominal power dissipation is 2.8 Watts. The circuit is fabricated in a 0.6 micron gate length, enhancement/depletion GaAs MESFET process utilizing 4 layers of gold interconnect metalization. Inductors, capacitors and thin film resistors can be fabricated in this process, enabling integrated analog circuitry. The die size is 3.28 mm by 3.15 mm. The circuit has applications in collision avoidance sensors, laser surveying, police radar, and test.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125920880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567646
T. Schaffer, H.P. Warren, M. J. Bustamante, K. Kong
A 2 GHz 12-bit digital-to-analog converter (DAC) designed for use in a Direct Digital Synthesizer was demonstrated with spurious performance exceeding -60 dBc when synthesizing 1/8th of a 1 GHz clock. This exceeds the best documented results of which we are aware by more than 15 dB at this clock rate and fractional frequency. When synthesizing near 1/3rd the clock rate the carrier-adjacent spurious performance exceeds -58 dBc at a 1 GHz clock rate, exceeding the 500 MHz clock rate performance of other DACs we have evaluated by 5-10 dB. Although designed to operate well above 2 GHz, state-of-the-art test equipment limited full characterization of the device to a 1 GHz clock rate at the time of evaluation. Unlike that observed with other DACs, nearly constant measured performance versus clock rate up to 1 GHz promises sustained performance at higher clock rates. The 12 bit DAC architecture consists of the 3 most significant bits driving 7 equally weighted current segments while the remaining 9 bits drive identical current segments combined through a binary R2R ladder. This architecture represents the best tradeoff between performance considerations and circuit complexity. The primary focus on this first design iteration was on achieving good spurious performance with less emphasis on power dissipation and on providing key information for a subsequent design optimization. The DAC was fabricated using an integrated circuit process developed at Hughes Research Laboratories and consists of 1200 AlInAs/GaInAs HBTs lattice matched to an InP substrate. The smallest InP-based HBTs utilized emitters having 2/spl times/2 sq. micron emitters with Ft=75 GHz and Fmax=85 GHz. The high speed DAC dissipated 2.8 W.
{"title":"A 2 GHz 12-bit digital-to-analog converter for direct digital synthesis applications","authors":"T. Schaffer, H.P. Warren, M. J. Bustamante, K. Kong","doi":"10.1109/GAAS.1996.567646","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567646","url":null,"abstract":"A 2 GHz 12-bit digital-to-analog converter (DAC) designed for use in a Direct Digital Synthesizer was demonstrated with spurious performance exceeding -60 dBc when synthesizing 1/8th of a 1 GHz clock. This exceeds the best documented results of which we are aware by more than 15 dB at this clock rate and fractional frequency. When synthesizing near 1/3rd the clock rate the carrier-adjacent spurious performance exceeds -58 dBc at a 1 GHz clock rate, exceeding the 500 MHz clock rate performance of other DACs we have evaluated by 5-10 dB. Although designed to operate well above 2 GHz, state-of-the-art test equipment limited full characterization of the device to a 1 GHz clock rate at the time of evaluation. Unlike that observed with other DACs, nearly constant measured performance versus clock rate up to 1 GHz promises sustained performance at higher clock rates. The 12 bit DAC architecture consists of the 3 most significant bits driving 7 equally weighted current segments while the remaining 9 bits drive identical current segments combined through a binary R2R ladder. This architecture represents the best tradeoff between performance considerations and circuit complexity. The primary focus on this first design iteration was on achieving good spurious performance with less emphasis on power dissipation and on providing key information for a subsequent design optimization. The DAC was fabricated using an integrated circuit process developed at Hughes Research Laboratories and consists of 1200 AlInAs/GaInAs HBTs lattice matched to an InP substrate. The smallest InP-based HBTs utilized emitters having 2/spl times/2 sq. micron emitters with Ft=75 GHz and Fmax=85 GHz. The high speed DAC dissipated 2.8 W.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114875802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567839
S. Ohmi, T. Okamoto, M. Tagami, E. Tokumitsu, H. Ishiwara
Fabrications and characterizations of high electron-mobility transistors (HEMTs) with a ferroelectric gate (F-HEMTs) are presented. The F-HEMT is a memory device whose threshold voltage can be changed even after it is fabricated, by using remanent polarization of the ferroelectric gate. Furthermore, the F-HEMT is promising of neural network applications, because it can act as a high-speed analog memory which stores synaptic weights in a neuron circuit. From I/sub D/-V/sub G/ characteristic measurements of F-HEMTs, it is demonstrated that the threshold voltage is shifted by 0.3 V by remanent polarization. The result indicates that F-HEMTs are sufficiently applicable for the high-speed analog memory.
{"title":"Device characterization of high-electron-mobility transistors with ferroelectric-gate structures","authors":"S. Ohmi, T. Okamoto, M. Tagami, E. Tokumitsu, H. Ishiwara","doi":"10.1109/GAAS.1996.567839","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567839","url":null,"abstract":"Fabrications and characterizations of high electron-mobility transistors (HEMTs) with a ferroelectric gate (F-HEMTs) are presented. The F-HEMT is a memory device whose threshold voltage can be changed even after it is fabricated, by using remanent polarization of the ferroelectric gate. Furthermore, the F-HEMT is promising of neural network applications, because it can act as a high-speed analog memory which stores synaptic weights in a neuron circuit. From I/sub D/-V/sub G/ characteristic measurements of F-HEMTs, it is demonstrated that the threshold voltage is shifted by 0.3 V by remanent polarization. The result indicates that F-HEMTs are sufficiently applicable for the high-speed analog memory.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129775290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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