Pub Date : 1996-12-31DOI: 10.1109/GAAS.1996.567836
J. Zolper, A. Baca, M. Sherwin, V. Hietala, J. Shul
GaAs Junction Field Effect Transistors (JFETs) are reported with gate lengths down to 0.3 /spl mu/m. The structure is fully self-aligned and employs all ion implantation doping. p/sup +/-gate regions are formed with either Zn or Cd implants along with a P co-implantation to reduce diffusion. The source and drain implants are engineered with Si or SiF implants to minimize short channel effects. 0.3 /spl mu/m gate length JFETs are demonstrated with a subthreshold slope of 110 mV/decade along with an intrinsic unity current gain cutoff frequency as high as 52 GHz.
{"title":"Ion-implanted GaAs JFETs with f/sub t/>45 GHz for low-power electronics","authors":"J. Zolper, A. Baca, M. Sherwin, V. Hietala, J. Shul","doi":"10.1109/GAAS.1996.567836","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567836","url":null,"abstract":"GaAs Junction Field Effect Transistors (JFETs) are reported with gate lengths down to 0.3 /spl mu/m. The structure is fully self-aligned and employs all ion implantation doping. p/sup +/-gate regions are formed with either Zn or Cd implants along with a P co-implantation to reduce diffusion. The source and drain implants are engineered with Si or SiF implants to minimize short channel effects. 0.3 /spl mu/m gate length JFETs are demonstrated with a subthreshold slope of 110 mV/decade along with an intrinsic unity current gain cutoff frequency as high as 52 GHz.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130444970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/gaas.1996.567866
J. Muller, A. Bangert, T. Grave, M. Karner, H. Riechert, A. Schafer, H. Siweris, L. Schleicher, H. Tischer, L. Verweyen, W. Kellner, T. Meier
A production oriented GaAs HEMT MMIC chipset for a 77 GHz FMCW automotive radar system is reported. It differs mainly in two aspects from the GaAs MMIC solutions described earlier: (1) 0.12 /spl mu/m gatelength PHEMTs are fabricated by optical stepper lithography, (2) a coplanar design is used. A fully passivated PHEMT fabrication process is reported with current-gain and power-gain cutoff frequencies exceeding 115 and 220 GHz, respectively. The design and performance of the chipset consisting of four different MMICs (VCO, harmonic mixer, transmitter, receiver) is described. The great potential of this MMIC approach to meet all system requirements of an automotive radar sensor in a cost effective and production oriented way is shown.
{"title":"A GaAs HEMT MMIC chip set for automotive radar systems fabricated by optical stepper lithography","authors":"J. Muller, A. Bangert, T. Grave, M. Karner, H. Riechert, A. Schafer, H. Siweris, L. Schleicher, H. Tischer, L. Verweyen, W. Kellner, T. Meier","doi":"10.1109/gaas.1996.567866","DOIUrl":"https://doi.org/10.1109/gaas.1996.567866","url":null,"abstract":"A production oriented GaAs HEMT MMIC chipset for a 77 GHz FMCW automotive radar system is reported. It differs mainly in two aspects from the GaAs MMIC solutions described earlier: (1) 0.12 /spl mu/m gatelength PHEMTs are fabricated by optical stepper lithography, (2) a coplanar design is used. A fully passivated PHEMT fabrication process is reported with current-gain and power-gain cutoff frequencies exceeding 115 and 220 GHz, respectively. The design and performance of the chipset consisting of four different MMICs (VCO, harmonic mixer, transmitter, receiver) is described. The great potential of this MMIC approach to meet all system requirements of an automotive radar sensor in a cost effective and production oriented way is shown.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127202094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567744
P. Leber, W. Baumberger, M. Lang, M. Rieger-Motzer, W. Bronner, A. Hulsmann, B. Raynor
A completely integrated single-chip phase-locked loop was designed using a 0.2 /spl mu/m-enhancement/depletion AlGaAs/GaAs/AlGaAs-HEMT technology. The chip contains a VCO with 15 GHz center frequency, as well as a frequency divider, a phase detector, and a loop filter. The fabricated chip size is 1.5/spl times/1.5 mm/sup 2/. The power consumption is 0.5 W using a supply voltage of 5.0 V. The lock range is approximately /spl plusmn/270 MHz. The phase noise is -100 dBc/Hz at 100 kHz and -107 dBc/Hz at 1 MHz offset from the carrier, respectively.
{"title":"A completely integrated single-chip phase-locked loop with a 15 GHz VCO using 0.2 /spl mu/m E-/D-HEMT-technology","authors":"P. Leber, W. Baumberger, M. Lang, M. Rieger-Motzer, W. Bronner, A. Hulsmann, B. Raynor","doi":"10.1109/GAAS.1996.567744","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567744","url":null,"abstract":"A completely integrated single-chip phase-locked loop was designed using a 0.2 /spl mu/m-enhancement/depletion AlGaAs/GaAs/AlGaAs-HEMT technology. The chip contains a VCO with 15 GHz center frequency, as well as a frequency divider, a phase detector, and a loop filter. The fabricated chip size is 1.5/spl times/1.5 mm/sup 2/. The power consumption is 0.5 W using a supply voltage of 5.0 V. The lock range is approximately /spl plusmn/270 MHz. The phase noise is -100 dBc/Hz at 100 kHz and -107 dBc/Hz at 1 MHz offset from the carrier, respectively.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123298331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567874
R. Lai, M. Nishimoto, Y. Hwang, M. Biedenbender, B. Kasody, C. Geiger, Y.C. Chen, G. Zell
We present a unique high performance 0.15 /spl mu/m InGaAs/AlGaAs/GaAs HEMT MMIC power amplifier fabricated with a 2-mil thick GaAs substrate which operates at V-band. The 2-stage 59-64 GHz power MMIC amplifier exhibits 27% peak power added efficiency at 60 GHz with 275 mW output power (350 mW/mm) and 11 dB power gain. When biased for higher output power, 400 mW output power was achieved at 60 GHz with 24.5% power added efficiency. This is the highest reported combination of output power and power added efficiency reported to date at this frequency band. This amplifier also exhibits outstanding wideband power characteristics with 25.5/spl plusmn/0.5 dBm output power measured from 59-64 GHz.
{"title":"A high efficiency 0.15 /spl mu/m 2-mil thick InGaAs/AlGaAs/GaAs V-band power HEMT MMIC","authors":"R. Lai, M. Nishimoto, Y. Hwang, M. Biedenbender, B. Kasody, C. Geiger, Y.C. Chen, G. Zell","doi":"10.1109/GAAS.1996.567874","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567874","url":null,"abstract":"We present a unique high performance 0.15 /spl mu/m InGaAs/AlGaAs/GaAs HEMT MMIC power amplifier fabricated with a 2-mil thick GaAs substrate which operates at V-band. The 2-stage 59-64 GHz power MMIC amplifier exhibits 27% peak power added efficiency at 60 GHz with 275 mW output power (350 mW/mm) and 11 dB power gain. When biased for higher output power, 400 mW output power was achieved at 60 GHz with 24.5% power added efficiency. This is the highest reported combination of output power and power added efficiency reported to date at this frequency band. This amplifier also exhibits outstanding wideband power characteristics with 25.5/spl plusmn/0.5 dBm output power measured from 59-64 GHz.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128689754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567901
T. Weatherford, P. Marshall, C. Dale, D. McMorrow, A. Peczalski, S. Baier, M. Carts, M. Twigg
Implementation of a low temperature grown GaAs (LT GaAs) buffer layer beneath the complementary heterostructure field effect transistor (CHFET) GaAs integrated circuit (IC) process is shown to eliminate soft error susceptibility. With soft errors reduced by over 8 orders of magnitude, the CHFET digital GaAs technology can provide the highest overall radiation immunity for any GaAs or silicon FET-based technology.
{"title":"Soft error immune LT GaAs ICs","authors":"T. Weatherford, P. Marshall, C. Dale, D. McMorrow, A. Peczalski, S. Baier, M. Carts, M. Twigg","doi":"10.1109/GAAS.1996.567901","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567901","url":null,"abstract":"Implementation of a low temperature grown GaAs (LT GaAs) buffer layer beneath the complementary heterostructure field effect transistor (CHFET) GaAs integrated circuit (IC) process is shown to eliminate soft error susceptibility. With soft errors reduced by over 8 orders of magnitude, the CHFET digital GaAs technology can provide the highest overall radiation immunity for any GaAs or silicon FET-based technology.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130084521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567880
I. Ishida, K. Miyatsuji, T. Tanaka, H. Takenaka, H. Furukawa, M. Nishitsuji, A. Tamura, D. Ueda
We have developed wideband amplifier that can keep over 10 dB gain at the drain voltage/current of 2 V/10 mA in the frequency range from 100 MHz to 3 GHz. The fabricated IC achieved low noise figure and high IP3 (output) of 1.4 dB and 30 dBm at 800 MHz, respectively. The present IC employs 0.2 /spl mu/m gate delta-doped MODFET structure fabricated by using phase-shift lithography.
{"title":"Low current wideband amplifier using 0.2 /spl mu/m gate MODFET fabricated by using phase-shift lithography","authors":"I. Ishida, K. Miyatsuji, T. Tanaka, H. Takenaka, H. Furukawa, M. Nishitsuji, A. Tamura, D. Ueda","doi":"10.1109/GAAS.1996.567880","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567880","url":null,"abstract":"We have developed wideband amplifier that can keep over 10 dB gain at the drain voltage/current of 2 V/10 mA in the frequency range from 100 MHz to 3 GHz. The fabricated IC achieved low noise figure and high IP3 (output) of 1.4 dB and 30 dBm at 800 MHz, respectively. The present IC employs 0.2 /spl mu/m gate delta-doped MODFET structure fabricated by using phase-shift lithography.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131531015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567632
M. P. Dugan
High power GaAs integrated circuits operated at elevated temperatures display failure mechanisms which result from the high current densities through the FETs. Evidence of material growths or material accumulations on the drain contacts of high current FETs has been observed after the GaAs substrate material has been removed by chemical etching. These observations support the conclusion that these growths are responsible for end-of-life failures in the high current FETs.
{"title":"Direct observation of localized high current effects in gallium arsenide field effect transistors","authors":"M. P. Dugan","doi":"10.1109/GAAS.1996.567632","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567632","url":null,"abstract":"High power GaAs integrated circuits operated at elevated temperatures display failure mechanisms which result from the high current densities through the FETs. Evidence of material growths or material accumulations on the drain contacts of high current FETs has been observed after the GaAs substrate material has been removed by chemical etching. These observations support the conclusion that these growths are responsible for end-of-life failures in the high current FETs.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132849307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567649
I. Moussa, P. Lassen
Routing tables for communication networks can be designed using several approaches, including table look-up, content-addressable Memory (CAM), hashing, and tries. This paper presents a GaAs VLSI implementation of an efficient table lookup algorithm for 2.5 Gb/s ATM switching systems. This algorithm presents some very promising features such as the number of Virtual Channels which can reach 30000 possible connections. An extra header of three bytes is attached to the cell header which contains policing and priorities information for use inside the switch. Routing information is performed by using the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI) in the incoming cell to access the header translation table. The VLSI chip is fabricated using 0.6 /spl mu/m gate GaAs MESFETs, by VITESSE Semiconductor and it is housed in a 132 pin LDCC package. The Label Translator chip is expected to operate at 311 MHz with an associated power dissipation of 4 W.
{"title":"GaAs VLSI implementation of a 2.5 Gb/s ATM label translator","authors":"I. Moussa, P. Lassen","doi":"10.1109/GAAS.1996.567649","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567649","url":null,"abstract":"Routing tables for communication networks can be designed using several approaches, including table look-up, content-addressable Memory (CAM), hashing, and tries. This paper presents a GaAs VLSI implementation of an efficient table lookup algorithm for 2.5 Gb/s ATM switching systems. This algorithm presents some very promising features such as the number of Virtual Channels which can reach 30000 possible connections. An extra header of three bytes is attached to the cell header which contains policing and priorities information for use inside the switch. Routing information is performed by using the Virtual Path Identifier (VPI) and the Virtual Channel Identifier (VCI) in the incoming cell to access the header translation table. The VLSI chip is fabricated using 0.6 /spl mu/m gate GaAs MESFETs, by VITESSE Semiconductor and it is housed in a 132 pin LDCC package. The Label Translator chip is expected to operate at 311 MHz with an associated power dissipation of 4 W.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128918763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567833
T. Tokumitsu, M. Hirano, K. Yamasaki, C. Yamaguchi, M. Aikawa
A novel masterslice MMIC design approach employing a 3-D MMIC structure is described using a highly-integrated 17-24 GHz GaAs single-chip receiver and a 7-10 GHz Si reactive-impedance-matching amplifier, which are the most recent devices fabricated with our process. This approach considerably reduces TAT and manufacturing costs.
{"title":"Highly integrated 3-D MMIC technology being applied to novel masterslice GaAs- and Si-MMIC's","authors":"T. Tokumitsu, M. Hirano, K. Yamasaki, C. Yamaguchi, M. Aikawa","doi":"10.1109/GAAS.1996.567833","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567833","url":null,"abstract":"A novel masterslice MMIC design approach employing a 3-D MMIC structure is described using a highly-integrated 17-24 GHz GaAs single-chip receiver and a 7-10 GHz Si reactive-impedance-matching amplifier, which are the most recent devices fabricated with our process. This approach considerably reduces TAT and manufacturing costs.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"3 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128303558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-11-03DOI: 10.1109/GAAS.1996.567868
K. Kobayashi, A. Oki, D. Umemoto, T. Block, D. Streit
Here we report on the world's first monolithically integrated HEMT-HBT MMIC receiver. The S-band receiver MMIC is the first of its kind, integrating a 2-stage HEMT LNA RF amplifier and a HEMT LO amplifier with an HBT double-balanced Gilbert cell mixer using selective MBE. The MMIC achieves greater than 18 dB conversion gain over an RF input band from 1.4-2.6 GHz, a minimum DSB noise figure of 2.3 dB and an IF3 of -0.5 dBm with no IF amplification. In addition, LO-IF and RF-IF isolations in excess of 22 dB and a 2-2 Spur suppression of 40 dBc are obtained due to the use of the double balanced HBT Gilbert cell mixer. The compact MMIC is 7.7/spl times/2.9 mm/sup 2/ and is self-biased from /spl plusmn/5 V supplies with a total dc power consumption of 735 mW. This HEMT-HBT MMIC represents the highest complexity design achieved using the HEMT-HBT selective MBE IC technology and demonstrates size and RF performance advantages over single-technology MMIC and hybrid integrated approaches.
{"title":"A monolithic integrated HEMT-HBT S-band receiver","authors":"K. Kobayashi, A. Oki, D. Umemoto, T. Block, D. Streit","doi":"10.1109/GAAS.1996.567868","DOIUrl":"https://doi.org/10.1109/GAAS.1996.567868","url":null,"abstract":"Here we report on the world's first monolithically integrated HEMT-HBT MMIC receiver. The S-band receiver MMIC is the first of its kind, integrating a 2-stage HEMT LNA RF amplifier and a HEMT LO amplifier with an HBT double-balanced Gilbert cell mixer using selective MBE. The MMIC achieves greater than 18 dB conversion gain over an RF input band from 1.4-2.6 GHz, a minimum DSB noise figure of 2.3 dB and an IF3 of -0.5 dBm with no IF amplification. In addition, LO-IF and RF-IF isolations in excess of 22 dB and a 2-2 Spur suppression of 40 dBc are obtained due to the use of the double balanced HBT Gilbert cell mixer. The compact MMIC is 7.7/spl times/2.9 mm/sup 2/ and is self-biased from /spl plusmn/5 V supplies with a total dc power consumption of 735 mW. This HEMT-HBT MMIC represents the highest complexity design achieved using the HEMT-HBT selective MBE IC technology and demonstrates size and RF performance advantages over single-technology MMIC and hybrid integrated approaches.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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