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2009 IEEE MTT-S International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects最新文献

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Impact of ULK Dielectric Loss on Interconnect Response for 45 nm Node Integrated Circuits ULK介电损耗对45nm节点集成电路互连响应的影响
S. de Rivaz, T. Lacrevaz, M. Gallitre, A. Farcy, B. Blampey, C. Bermond, B. Fléchet
New materials such as dielectrics with ultra low permittivity are required to improve interconnect performance for future IC's technology nodes. Porous dielectric materials, as SiOCH, used for the 45 nm technology are very prone to damage during integration process, degrading their permittivity and severely increasing their loss tangent. Theses dielectric losses have to be precisely taken into account in order to accurately simulate the propagation effects along interconnects and to predict delay and crosstalk. Thus fine large-band extraction of complex permittivity must be achieved in respect to physical consistence of signals. This study aims at accurately evaluate the impact of dielectric degradation on interconnects electrical performance. Moreover it will be outlined, using two different IC's configurations, that the accurately on the prediction of interconnect performance needs adequate dielectric models.
为了提高未来集成电路技术节点的互连性能,需要新型材料,如具有超低介电常数的电介质。45纳米工艺中使用的多孔介质材料,如SiOCH,在集成过程中很容易损坏,导致介电常数降低,损耗正切值严重增加。为了准确地模拟沿互连线的传播效应和预测延迟和串扰,必须精确地考虑这些介电损耗。因此,必须在信号的物理一致性方面实现复介电常数的精细大波段提取。本研究旨在准确评估介电退化对互连电性能的影响。此外,它将概述,使用两种不同的集成电路结构,准确地预测互连性能需要适当的介电模型。
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引用次数: 4
Neural Network Techniques for High-Speed Electronic Component Modeling 高速电子元件建模的神经网络技术
Qi-jun Zhang, Lei Zhang
This paper provides an overview of neural network applications for high-speed electronic component modeling. Two neural network techniques, an electromagnetic (EM)-based neural modeling approach and a state-space dynamic neural network method, are presented. Accurate neural models are obtained to represent behaviors of EM component and nonlinear circuit. The neural models are used in signal integrity design of high-speed integrated circuits, helping to improve efficiency in circuit simulation and optimization.
本文综述了神经网络在高速电子元件建模中的应用。提出了两种神经网络技术,即基于电磁(EM)的神经网络建模方法和状态空间动态神经网络方法。得到了表征电磁元件和非线性电路行为的精确神经网络模型。将神经网络模型应用于高速集成电路的信号完整性设计,有助于提高电路仿真和优化的效率。
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引用次数: 5
High Frequency SU-8 Based Transmission Line for 3-D Millimeter-wave Antennas 基于高频SU-8的三维毫米波天线传输线
Sae-Won Lee, A. Parameswaran, R. Vaughan, A. Mahanfar
A fabrication method and characterization of transmission lines for 3-D millimeter-wave antennas are presented using a polymer micro-electro-mechanical-systems (MEMS) fabrication process. The fabrication process steps are performed at low temperatures and are compatible for on-chip CMOS integration. Blanket metal deposition is applied to the wafer to coat the structures with Au and Cr and electrical isolation is achieved by anchor designs.
介绍了一种利用聚合物微机电系统(MEMS)工艺制备三维毫米波天线传输线的方法和特性。制造工艺步骤在低温下进行,并且与片上CMOS集成兼容。在晶圆片上镀上金属层,用Au和Cr覆盖结构,并通过锚定设计实现电隔离。
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引用次数: 1
Fast Space Mapping with Variable Weight Coefficients for Microwave Device Modeling 基于变权系数的微波器件快速空间映射建模
S. Koziel, J. Bandler
We describe an improvement of a recent space mapping (SM) modeling approach that uses variable weight coefficients (SM-VWC). Our modification alleviates the main drawback of SM-VWC: the computational overhead related to a separate parameter extraction required for each evaluation of the surrogate model. In our new procedure, the output SM parameters of the surrogate model are obtained by solving a regression problem instead of being determined in the parameter extraction process. This dramatically reduces the evaluation time of the surrogate model. Moreover, the modeling accuracy of the modified technique is even better than the accuracy of the original SM-VWC approach. Examples demonstrate the robustness of our approach.
我们描述了最近使用变权系数(SM- vwc)的空间映射(SM)建模方法的改进。我们的修改减轻了SM-VWC的主要缺点:每次评估代理模型所需的单独参数提取相关的计算开销。在我们的新过程中,代理模型的输出SM参数是通过求解回归问题获得的,而不是在参数提取过程中确定的。这极大地减少了代理模型的评估时间。此外,改进后的方法的建模精度甚至优于原SM-VWC方法的建模精度。示例证明了我们方法的健壮性。
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引用次数: 2
Impact of the Configuration of Ground Vias on the Performance of Vertical Transitions Used in Electronic Packages 地过孔结构对电子封装中使用的垂直过渡性能的影响
S. C. Sejas-García, G. Romo, R. Torres‐Torres
The ground vias are used to interconnect the different ground planes existing in a package structure, but also to prevent the propagation of parasitic modes like the parallel-plate mode inside the structure. From a signal integrity perspective, these parasitic modes degrade and limit the performance of a package since they introduce undesired resonances in the electrical response of the structure. Thus, the distribution of the ground vias is of great importance in the design of advanced packages. Using full-wave simulators, we have observed the distribution of the electric and magnetic fields as a high-frequency signal propagates through vertical transitions surrounded by ground vias. The information from the distribution of fields and the corresponding S-parameters were obtained from simulations for different configurations of ground vias in a vertical transition; these are the bases of the paper. The purpose of the presented analysis is to understand the relationship between the frequency at which the resonances associated with the propagation of parasitic modes occur and the configuration of the ground vias.
接地通孔用于连接封装结构中存在的不同接地面,但也用于防止寄生模式(如平行板模式)在结构内部的传播。从信号完整性的角度来看,这些寄生模式会降低并限制封装的性能,因为它们会在结构的电响应中引入不希望的共振。因此,地通孔的分布在先进封装设计中具有重要意义。使用全波模拟器,我们已经观察到电场和磁场的分布,当高频信号通过被地面过孔包围的垂直过渡传播时。对垂直过渡中不同配置的地面通孔进行了模拟,得到了场的分布信息和相应的s参数;这些是这篇论文的基础。所提出的分析的目的是了解与寄生模式传播相关的共振发生的频率与地过孔的配置之间的关系。
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引用次数: 7
期刊
2009 IEEE MTT-S International Microwave Workshop Series on Signal Integrity and High-Speed Interconnects
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