Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675214
A. Timár, M. Rencz
This paper proposes an accurate temperature dependent delay model for logi-thermal simulations. During the logi-thermal simulation of digital integrated circuits the propagation delays of the standard cells can be calculated from delay-temperature functions. The delay-temperature functions contain exact and precise delay values for each input-output path and temperature value. Temperature characterization corners can be specified in arbitrary fine granularity and range. The model presented in this paper overcome the limitation of the classic SDF (Standard Delay Format) models in that propagation delay values can be given for arbitrary temperatures, not only a few corners. With classic SDF, temperature dependence of timing and thus power can only be taken into account for a few design corners. Between characterization corners, like supply voltage, process variation and temperature, linear interpolation must be used for intermediate data. With our proposed delay model temperature-aware timing simulations would produce more accurate results than the classic SDF model. This paper compares the classic SDF delay model with our temperature dependent detailed model and provides evidence through a simple example for the necessity of temperature-aware timing simulation. The logi-thermal simulations are carried out with the CellTherm[1] application developed in the Dept. of Electron Devices, BME, Hungary. A logi-thermal acceleration technique is also introduced in this paper.
{"title":"Logi-thermal simulation using high-resolution temperature dependent delay models","authors":"A. Timár, M. Rencz","doi":"10.1109/THERMINIC.2013.6675214","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675214","url":null,"abstract":"This paper proposes an accurate temperature dependent delay model for logi-thermal simulations. During the logi-thermal simulation of digital integrated circuits the propagation delays of the standard cells can be calculated from delay-temperature functions. The delay-temperature functions contain exact and precise delay values for each input-output path and temperature value. Temperature characterization corners can be specified in arbitrary fine granularity and range. The model presented in this paper overcome the limitation of the classic SDF (Standard Delay Format) models in that propagation delay values can be given for arbitrary temperatures, not only a few corners. With classic SDF, temperature dependence of timing and thus power can only be taken into account for a few design corners. Between characterization corners, like supply voltage, process variation and temperature, linear interpolation must be used for intermediate data. With our proposed delay model temperature-aware timing simulations would produce more accurate results than the classic SDF model. This paper compares the classic SDF delay model with our temperature dependent detailed model and provides evidence through a simple example for the necessity of temperature-aware timing simulation. The logi-thermal simulations are carried out with the CellTherm[1] application developed in the Dept. of Electron Devices, BME, Hungary. A logi-thermal acceleration technique is also introduced in this paper.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124388640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675252
T. Caroff, R. Mitova, B. Wunderle, J. Simon
This paper deals with the system design for integrating Si and SiC power dies along with thermo-electric coolers and phase change materials in order to thermally manage transient overloads occurring during operation for motor drive application. Different double-sided cooling designs are evaluated to take the best of each active stage. Multi-physic simulations are used to predict thermal performance and define the final architecture for such application taking into account final user specifications and sizing. This paper is a part of a series of planned publications on the ongoing work in the SMARTPOWER project.
{"title":"Transient cooling of power electronic devices using thermoelectric coolers coupled with phase change materials","authors":"T. Caroff, R. Mitova, B. Wunderle, J. Simon","doi":"10.1109/THERMINIC.2013.6675252","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675252","url":null,"abstract":"This paper deals with the system design for integrating Si and SiC power dies along with thermo-electric coolers and phase change materials in order to thermally manage transient overloads occurring during operation for motor drive application. Different double-sided cooling designs are evaluated to take the best of each active stage. Multi-physic simulations are used to predict thermal performance and define the final architecture for such application taking into account final user specifications and sizing. This paper is a part of a series of planned publications on the ongoing work in the SMARTPOWER project.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126917232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675191
S. Grauby, E. Puyoo, M. Muñoz Rojo, M. Martín‐González, W. Claeys, S. Dilhaire
We have investigated various kinds of nanowires (Si, Bi2Te3, SiGe) in order to evaluate the influence of the nanostructuration on their thermal conductivity. The method used is a 3ω-SThM (Scanning Thermal Microscopy) technique which enables to simultaneously measure the topography and the thermal conductivity on an assembly of NWs. We detail the procedure from the measurement itself to the nanowire thermal conductivity estimation. We show that the nanostructuration leads to a thermal conductivity reduction for the 3 materials we have studied and that Si and SiGe nanowire samples seem more promising than Bi2Te3 NWs in terms of thermoelectric applications.
{"title":"Effect of nanostructuration on the thermal conductivity of thermoelectric materials","authors":"S. Grauby, E. Puyoo, M. Muñoz Rojo, M. Martín‐González, W. Claeys, S. Dilhaire","doi":"10.1109/THERMINIC.2013.6675191","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675191","url":null,"abstract":"We have investigated various kinds of nanowires (Si, Bi2Te3, SiGe) in order to evaluate the influence of the nanostructuration on their thermal conductivity. The method used is a 3ω-SThM (Scanning Thermal Microscopy) technique which enables to simultaneously measure the topography and the thermal conductivity on an assembly of NWs. We detail the procedure from the measurement itself to the nanowire thermal conductivity estimation. We show that the nanostructuration leads to a thermal conductivity reduction for the 3 materials we have studied and that Si and SiGe nanowire samples seem more promising than Bi2Te3 NWs in terms of thermoelectric applications.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130672902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675202
Ningkang Li, G. Schlottig, Marco De-Fazio, C. Sharma, M. Tiwari, R. Brioschi, D. Poulikakos, T. Brunschwiler
In this paper, we propose a novel lid-integrated cold plate with distributed fluid delivery architecture to a silicon microchannel heat exchanger. The microchannels consist of a staggered fin array. The manifold topology tolerates the use of a one-component lid, compatible with high volume fabrication processes, such as injection molding. A multi-scale modelling methodology based on the porous media approximation is introduced and compared with experimental results. The fluid cavity of the heat exchanger in the full heat sink model is represented as a two-dimensional porous domain. This approximation reduces the computational cost to solve the conjugate heat and mass transfer problem significantly. The characteristic of the cold plate is discussed based onfull heat sink model results. The main pressure drop of 93%for the base-line case can be attributed to the losses in the staggered fin array. The flow non-uniformity in the heat exchanger is less than 1.2% A sensitivity analysis with the objective o.f reducing the pumping power for a nominal thermal performance was performed based on a lumped model. it is preferable to increase the number of sub-sections and to reduce the fin dimension in the heat exchanger. The increase in access slit width is of moderate importance. The optimal case computed has 100 pm wide microchannelfins, accessed by 8 manifold.fingers that have 400 pm wide slits at their bottom. This case requires 0.5 W pumping power for a thermal resistance of 12 Kmm2/W.
{"title":"Hybrid porous media and fluid domain modeling strategy to optimize a novel staggered fin heat sink design","authors":"Ningkang Li, G. Schlottig, Marco De-Fazio, C. Sharma, M. Tiwari, R. Brioschi, D. Poulikakos, T. Brunschwiler","doi":"10.1109/THERMINIC.2013.6675202","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675202","url":null,"abstract":"In this paper, we propose a novel lid-integrated cold plate with distributed fluid delivery architecture to a silicon microchannel heat exchanger. The microchannels consist of a staggered fin array. The manifold topology tolerates the use of a one-component lid, compatible with high volume fabrication processes, such as injection molding. A multi-scale modelling methodology based on the porous media approximation is introduced and compared with experimental results. The fluid cavity of the heat exchanger in the full heat sink model is represented as a two-dimensional porous domain. This approximation reduces the computational cost to solve the conjugate heat and mass transfer problem significantly. The characteristic of the cold plate is discussed based onfull heat sink model results. The main pressure drop of 93%for the base-line case can be attributed to the losses in the staggered fin array. The flow non-uniformity in the heat exchanger is less than 1.2% A sensitivity analysis with the objective o.f reducing the pumping power for a nominal thermal performance was performed based on a lumped model. it is preferable to increase the number of sub-sections and to reduce the fin dimension in the heat exchanger. The increase in access slit width is of moderate importance. The optimal case computed has 100 pm wide microchannelfins, accessed by 8 manifold.fingers that have 400 pm wide slits at their bottom. This case requires 0.5 W pumping power for a thermal resistance of 12 Kmm2/W.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132748274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675239
K. Górecki
The paper concerns the influence of thermal phenomena on the characteristics of power LEDs. The electrothermal model of the power LED for the SPICE software taking into account electric, thermal and optical properties of the considered devices, and particularly the mutual thermal coupling between the devices situated on the common heat-sink or in the LED module, is presented. Using the worked out model the current-voltage characteristics of the selected diodes, dependences of their junction temperature on the forward current and the illuminance of the area lighted by the investigated LED on its forward current are calculated. These characteristics were calculated at different cooling conditions of the investigated LED, and the results of calculations were compared with the results of measurements. The single diode, two diodes situated on the common heat-sink, and the LED module are considered. The good agreement between the results of calculations and measurements confirms the correctness of the worked out model.
{"title":"The influence of mutual thermal interactions between power LEDs on their characteristics","authors":"K. Górecki","doi":"10.1109/THERMINIC.2013.6675239","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675239","url":null,"abstract":"The paper concerns the influence of thermal phenomena on the characteristics of power LEDs. The electrothermal model of the power LED for the SPICE software taking into account electric, thermal and optical properties of the considered devices, and particularly the mutual thermal coupling between the devices situated on the common heat-sink or in the LED module, is presented. Using the worked out model the current-voltage characteristics of the selected diodes, dependences of their junction temperature on the forward current and the illuminance of the area lighted by the investigated LED on its forward current are calculated. These characteristics were calculated at different cooling conditions of the investigated LED, and the results of calculations were compared with the results of measurements. The single diode, two diodes situated on the common heat-sink, and the LED module are considered. The good agreement between the results of calculations and measurements confirms the correctness of the worked out model.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116096693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675230
A. Burenkov, V. Belko, J. Lorenz
Self-heating of fully-depleted SOI MOSFETs scaled according to ITRS specifications for the year 2015 is investigated using numerical TCAD simulations and the method of molecular dynamics. The local warming-up due to self-heating of SOI-based transistors can exceed 200 K and must be considered in the simulation. Thermal properties of the few-nanometer-thin silicon layers differ significantly from those of bulk silicon. Therefore, molecular dynamics simulations were applied to quantify thermal transport in the channel of the ultra-thin-silicon body SOI transistors.
{"title":"Self-heating of nano-scale SOI MOSFETs: TCAD and molecular dynamics simulations","authors":"A. Burenkov, V. Belko, J. Lorenz","doi":"10.1109/THERMINIC.2013.6675230","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675230","url":null,"abstract":"Self-heating of fully-depleted SOI MOSFETs scaled according to ITRS specifications for the year 2015 is investigated using numerical TCAD simulations and the method of molecular dynamics. The local warming-up due to self-heating of SOI-based transistors can exceed 200 K and must be considered in the simulation. Thermal properties of the few-nanometer-thin silicon layers differ significantly from those of bulk silicon. Therefore, molecular dynamics simulations were applied to quantify thermal transport in the channel of the ultra-thin-silicon body SOI transistors.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128673957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675249
J. Mizsei, J. Lappalainen, M. Bein
Most of the electrical components (transistors, resistors, etc.) are thermally sensitive elements. Thermal coupling between elements of integrated circuits is a well-known parasitic effect, which must be taken into account in the design process. Here we introduce a new principle for logic gate and logic system operation using thermally sensitive electrical switches, such as vanadium-dioxide (VO2) resistors capable for semiconductor-metal transition (SMT) and showing thyristor-like characteristics. A thermally sensitive resistor (formed of VO2 for example) integrated with a controllable heating element can be considered as a novel electro-thermal active device: phonsistor. In a thermal-electronic integrated circuit (TELC) formed of phonsistors both the electrical and thermal signals are treated as logic variables. As the thermal time constants decrease with shrinking the geometrical dimensions (scaling down), in the region of a few 10 nm linear measures their value can be comparable with the electrical time constants (100 picoseconds). The tunnel effect limits the scaling down of electron devices; this may stop the size reduction in 10-20 nm for a phonsistor device and 50 nm for complex logic gates. As a TELC gate is basically a bulk type device, it contains less interfaces compared to the conventional VLSI gates, thus scaling down is easier and more effective.
{"title":"Thermal-electronic integrated logic","authors":"J. Mizsei, J. Lappalainen, M. Bein","doi":"10.1109/THERMINIC.2013.6675249","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675249","url":null,"abstract":"Most of the electrical components (transistors, resistors, etc.) are thermally sensitive elements. Thermal coupling between elements of integrated circuits is a well-known parasitic effect, which must be taken into account in the design process. Here we introduce a new principle for logic gate and logic system operation using thermally sensitive electrical switches, such as vanadium-dioxide (VO2) resistors capable for semiconductor-metal transition (SMT) and showing thyristor-like characteristics. A thermally sensitive resistor (formed of VO2 for example) integrated with a controllable heating element can be considered as a novel electro-thermal active device: phonsistor. In a thermal-electronic integrated circuit (TELC) formed of phonsistors both the electrical and thermal signals are treated as logic variables. As the thermal time constants decrease with shrinking the geometrical dimensions (scaling down), in the region of a few 10 nm linear measures their value can be comparable with the electrical time constants (100 picoseconds). The tunnel effect limits the scaling down of electron devices; this may stop the size reduction in 10-20 nm for a phonsistor device and 50 nm for complex logic gates. As a TELC gate is basically a bulk type device, it contains less interfaces compared to the conventional VLSI gates, thus scaling down is easier and more effective.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125275594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675189
B. Wunderle, C. Manier, M. A. Ras, M. Springborn, D. May, H. Oppermann, M. Toepper, R. Mrossko, T. Xhonneux, T. Caroff, W. Maurer, R. Mitova
This paper deals with the system design, technology and test of a novel concept of integrating Si and SiC power dies along with thermo-electric coolers in order to thermally manage transients occurring during operation. The concept features double-sided cooling as well as new materials and joining technologies to integrate the dies such as transient liquid phase bonding/soldering and sintering. Coupled-field simulations are used to predict thermal performance and are verified by especially designed test stands to very good agreement. This paper is the second in a series of publications on the ongoing work.
{"title":"Double-sided cooling and thermo-electrical management of power transients for silicon chips on DCB-substrates for converter applications: Design, technology and test","authors":"B. Wunderle, C. Manier, M. A. Ras, M. Springborn, D. May, H. Oppermann, M. Toepper, R. Mrossko, T. Xhonneux, T. Caroff, W. Maurer, R. Mitova","doi":"10.1109/THERMINIC.2013.6675189","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675189","url":null,"abstract":"This paper deals with the system design, technology and test of a novel concept of integrating Si and SiC power dies along with thermo-electric coolers in order to thermally manage transients occurring during operation. The concept features double-sided cooling as well as new materials and joining technologies to integrate the dies such as transient liquid phase bonding/soldering and sintering. Coupled-field simulations are used to predict thermal performance and are verified by especially designed test stands to very good agreement. This paper is the second in a series of publications on the ongoing work.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"400 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132440646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675227
G. Nagy, P. Horváth, A. Poppe
Thermal Transient Testing is a method practically used to determine the thermal model of an integrated circuit's case and cooling facilities. The traditional measurement setup of this diagnostic examination does not allow in-circuit testing in case of fully digital semi-custom devices, such as complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs) and programmable system on a chip devices (PSoCs) because it demands an accessible on-chip p-n junction for temperature rise initiation and temperature monitoring. The article presents a proposed novel measurement setup of the thermal transient testing developed for programmable logic devices that implements the required measurement means exploiting the general purpose programmable logic fabric. The main objective of the research is to determine the effects of the interaction between a live digital circuit and the thermal transient testing environment in order to ascertain the feasibility of an on-chip thermal testing facility making possible in-circuit measurements. A simple test environment and the obtained measurement results are presented in order to prove the applicability of the proposed measurement method. The article also presents an application of the logi-thermal simulation method enabling designers to optimize the relative placement of the measurement elements and the user logic. Simulation results showing the application of the method are included in this paper as well.
{"title":"Practical aspects of thermal transient testing in live digital circuits","authors":"G. Nagy, P. Horváth, A. Poppe","doi":"10.1109/THERMINIC.2013.6675227","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675227","url":null,"abstract":"Thermal Transient Testing is a method practically used to determine the thermal model of an integrated circuit's case and cooling facilities. The traditional measurement setup of this diagnostic examination does not allow in-circuit testing in case of fully digital semi-custom devices, such as complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs) and programmable system on a chip devices (PSoCs) because it demands an accessible on-chip p-n junction for temperature rise initiation and temperature monitoring. The article presents a proposed novel measurement setup of the thermal transient testing developed for programmable logic devices that implements the required measurement means exploiting the general purpose programmable logic fabric. The main objective of the research is to determine the effects of the interaction between a live digital circuit and the thermal transient testing environment in order to ascertain the feasibility of an on-chip thermal testing facility making possible in-circuit measurements. A simple test environment and the obtained measurement results are presented in order to prove the applicability of the proposed measurement method. The article also presents an application of the logi-thermal simulation method enabling designers to optimize the relative placement of the measurement elements and the user logic. Simulation results showing the application of the method are included in this paper as well.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134039157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675233
S. Bhansali, W. Khunsin, J. Reparaz, M. R. Wagner, J. Roqueta, J. Santiso, B. Abad Mayor, P. Díaz-Chao, M. Martín‐González, C. M. Torres
In his work we investigate the thermoelectric performance of SrTiO3 thin films doped with Nb grown using pulsed laser deposition on crystalline LaAlO3 substrates. We show that a large enhancement of the Seebeck coefficient is observed for thin films with thicknesses below 10 nm in accordance with previous publications. In addition, we investigated the thermal conductivity of the thin films using the 3ω technique between 4 and 300 K. We show that the thermal conductivity is reduced by a factor of three with respect to the bulk value. This reduction originates mostly in structural defects and oxygen vacancies within the thin films. Finally, the figure of merit of the thinnest films at 300 K resulted in ZT=0.62.
{"title":"SrTiO3 thin films as high efficient thermoelectric materials","authors":"S. Bhansali, W. Khunsin, J. Reparaz, M. R. Wagner, J. Roqueta, J. Santiso, B. Abad Mayor, P. Díaz-Chao, M. Martín‐González, C. M. Torres","doi":"10.1109/THERMINIC.2013.6675233","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675233","url":null,"abstract":"In his work we investigate the thermoelectric performance of SrTiO3 thin films doped with Nb grown using pulsed laser deposition on crystalline LaAlO3 substrates. We show that a large enhancement of the Seebeck coefficient is observed for thin films with thicknesses below 10 nm in accordance with previous publications. In addition, we investigated the thermal conductivity of the thin films using the 3ω technique between 4 and 300 K. We show that the thermal conductivity is reduced by a factor of three with respect to the bulk value. This reduction originates mostly in structural defects and oxygen vacancies within the thin films. Finally, the figure of merit of the thinnest films at 300 K resulted in ZT=0.62.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123366878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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