Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675207
X. Jordà, X. Perpiñà, M. Vellvehí, W. Hertog, M. Peralvarez, J. Carreras
This paper analyses the influence of several error sources on the thermal impedance curve measurement of multi-LED boards designed for retrofit Solid State Lighting bulbs, using standard instrumentation and simple auxiliary circuitry. The obtained thermal impedance curve is then used for the extraction of compact thermal models, suitable for the prediction of the LED junction temperature under working conditions and for system-level simulation. The main results have shown the relevance of the correct board backside reference temperature measurement and the errors associated to the radiant flux estimation.
{"title":"Influence of different characterization parameters on the accuracy of LED board thermal models for retrofit bulbs","authors":"X. Jordà, X. Perpiñà, M. Vellvehí, W. Hertog, M. Peralvarez, J. Carreras","doi":"10.1109/THERMINIC.2013.6675207","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675207","url":null,"abstract":"This paper analyses the influence of several error sources on the thermal impedance curve measurement of multi-LED boards designed for retrofit Solid State Lighting bulbs, using standard instrumentation and simple auxiliary circuitry. The obtained thermal impedance curve is then used for the extraction of compact thermal models, suitable for the prediction of the LED junction temperature under working conditions and for system-level simulation. The main results have shown the relevance of the correct board backside reference temperature measurement and the errors associated to the radiant flux estimation.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"604 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117348124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675196
C. Zandén, Xin Luo, L. Ye, Johan Liu
Dealing with increasing power densities in high performance micro- and power -electronics applications is continuously becoming more challenging. Many applications today need thermal interface materials (TIMs) that can offer significantly higher performance than what is currently available. One of the main challenges for TIMs is to combine material properties that result in the thermo-mechanical characteristics required. Solder TIMs can provide excellent thermal transport, but high stiffness, causing lack of sufficient thermal-mechanical decoupling, limits their applicability. To mitigate these issues we pursue the development of a composite metal matrix based TIM technology concept with potential to combine high thermal conductivity with low joint stiffness. In this work we optimize the fabrication of an indium matrix polyimide fibre composite and investigate its thermal performance as an interface material. The fabricated composite is shown to have high effective thermal conductivity (up to 22 W/mK) and result in low contact resistance (<;1 Kmm<;sup>2<;/sup>/W).
{"title":"Fabrication and characterization of a metal matrix polymer fibre composite for thermal interface material applications","authors":"C. Zandén, Xin Luo, L. Ye, Johan Liu","doi":"10.1109/THERMINIC.2013.6675196","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675196","url":null,"abstract":"Dealing with increasing power densities in high performance micro- and power -electronics applications is continuously becoming more challenging. Many applications today need thermal interface materials (TIMs) that can offer significantly higher performance than what is currently available. One of the main challenges for TIMs is to combine material properties that result in the thermo-mechanical characteristics required. Solder TIMs can provide excellent thermal transport, but high stiffness, causing lack of sufficient thermal-mechanical decoupling, limits their applicability. To mitigate these issues we pursue the development of a composite metal matrix based TIM technology concept with potential to combine high thermal conductivity with low joint stiffness. In this work we optimize the fabrication of an indium matrix polyimide fibre composite and investigate its thermal performance as an interface material. The fabricated composite is shown to have high effective thermal conductivity (up to 22 W/mK) and result in low contact resistance (<;1 Kmm<;sup>2<;/sup>/W).","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129775874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675195
Ayse Gozde Ulu Soysal, C. Sert, A. G. Yazicioglu
In this work, the relation between heat transfer performance and interruption of microchannels was investigated. Experiments were conducted on uninterrupted and interrupted aluminium channel heat sinks of different channel widths. Two different types of interrupted channels were tested: channels having single interruption and 7 interruptions. Distilled water was used to remove a constant heat load of 40 W in the volumetric flow rate range of 0.5-1.1 lpm. The interruption of channels improved the thermal performance over the uninterrupted counterparts up to 20 % in average Nusselt number, for 600 micron-wide channels. The improvement of average Nusselt number between the single interrupted and multi interrupted channels reached a maximum value of 56 % for 500 micron-wide channels. This improvement did not cause a high pressure drop penalty. In the tests, maximum temperature difference between the inlet of the fluid and the base of the channel was observed as 32.8°C.
{"title":"Experimental investigation of uninterrupted and interrupted microchannel heat sinks","authors":"Ayse Gozde Ulu Soysal, C. Sert, A. G. Yazicioglu","doi":"10.1109/THERMINIC.2013.6675195","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675195","url":null,"abstract":"In this work, the relation between heat transfer performance and interruption of microchannels was investigated. Experiments were conducted on uninterrupted and interrupted aluminium channel heat sinks of different channel widths. Two different types of interrupted channels were tested: channels having single interruption and 7 interruptions. Distilled water was used to remove a constant heat load of 40 W in the volumetric flow rate range of 0.5-1.1 lpm. The interruption of channels improved the thermal performance over the uninterrupted counterparts up to 20 % in average Nusselt number, for 600 micron-wide channels. The improvement of average Nusselt number between the single interrupted and multi interrupted channels reached a maximum value of 56 % for 500 micron-wide channels. This improvement did not cause a high pressure drop penalty. In the tests, maximum temperature difference between the inlet of the fluid and the base of the channel was observed as 32.8°C.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128676375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675218
M. R. Wagner, E. Chávez‐Ángel, J. Gomis-Bresco, J. Reparaz, A. Shchepetov, M. Prunnila, J. Ahopelto, F. Alzina, C. Sotomayor‐Torres
We study the dynamics of acoustic phonons in ultra-thin free-standing silicon membranes both experimentally and theoretically. We discuss the impact of the lifetimes of the acoustic phonons on the thermal transport properties of the membranes with thicknesses ranging from 8 nm to 1.5 μm. The phonon lifetimes are determined by measuring the dynamic variation of the reflectivity using ultra-fast pump-probe spectroscopy. This is achieved by asynchronous optical sampling (ASOPS) of two actively coupled femto-second laser oscillators. The coherent acoustic phonon lifetime is obtained from the dynamical variations of the reflectivity with a sensitivity of 10-5 and a time resolution of about 50 fs. The experimental results are compared to theoretical calculations considering both intrinsic and extrinsic relaxation scattering processes.
{"title":"Nanoscale thermal transport and phonon dynamics in ultra-thin Si based nanostructures","authors":"M. R. Wagner, E. Chávez‐Ángel, J. Gomis-Bresco, J. Reparaz, A. Shchepetov, M. Prunnila, J. Ahopelto, F. Alzina, C. Sotomayor‐Torres","doi":"10.1109/THERMINIC.2013.6675218","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675218","url":null,"abstract":"We study the dynamics of acoustic phonons in ultra-thin free-standing silicon membranes both experimentally and theoretically. We discuss the impact of the lifetimes of the acoustic phonons on the thermal transport properties of the membranes with thicknesses ranging from 8 nm to 1.5 μm. The phonon lifetimes are determined by measuring the dynamic variation of the reflectivity using ultra-fast pump-probe spectroscopy. This is achieved by asynchronous optical sampling (ASOPS) of two actively coupled femto-second laser oscillators. The coherent acoustic phonon lifetime is obtained from the dynamical variations of the reflectivity with a sensitivity of 10-5 and a time resolution of about 50 fs. The experimental results are compared to theoretical calculations considering both intrinsic and extrinsic relaxation scattering processes.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132995413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675192
C. Sohrmann, A. Heinig, Michael Dittrich, R. Jancke, P. Schneider
We propose an innovative thermal modeling approach that takes into account different “levels-of-knowledge” as they become available during the design phases of microelectronic systems. There are many tools available for thermal simulations which are well-suited for high-precision modeling. However, their applicability severely diminishes if CAD models are not available or modeling time is limited. Especially for electro-thermal co-design, where several spins between modeling and simulation are required, modeling time quickly becomes prohibitively large. By a combination of different techniques our solution offers fast and intuitive modeling, continuous addition of detail, very short simulation times, and open interfaces. In this paper we present our thermal modeling approach based on constructive solid geometry (CSG). We discuss advantages and limits of this solution and demonstrate its performance on an example of industrially-relevant complexity.
{"title":"Electro-thermal co-design of chip-package-board systems","authors":"C. Sohrmann, A. Heinig, Michael Dittrich, R. Jancke, P. Schneider","doi":"10.1109/THERMINIC.2013.6675192","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675192","url":null,"abstract":"We propose an innovative thermal modeling approach that takes into account different “levels-of-knowledge” as they become available during the design phases of microelectronic systems. There are many tools available for thermal simulations which are well-suited for high-precision modeling. However, their applicability severely diminishes if CAD models are not available or modeling time is limited. Especially for electro-thermal co-design, where several spins between modeling and simulation are required, modeling time quickly becomes prohibitively large. By a combination of different techniques our solution offers fast and intuitive modeling, continuous addition of detail, very short simulation times, and open interfaces. In this paper we present our thermal modeling approach based on constructive solid geometry (CSG). We discuss advantages and limits of this solution and demonstrate its performance on an example of industrially-relevant complexity.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125614890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675245
R. Mrossko, C. Neeb, T. Hofmann, A. Neumann, J. Keller
The demand of cost reduction and limited installation space for automotive applications requires new and innovative approaches. One approach is to substitute DCB substrates with high current circuit boards. These circuit boards with fully embedded actives like IGBTs and Diodes allows to avoid the use of bonding wires at all and benefit from the less expensive standard circuit board technologies. Moreover it should be possible to use double sided cooling for such devices. In this paper we investigate the influence of several geometry and material parameter, like layer thicknesses, thermal conductivity and cooling power on the thermal performance of a fully embedded 650V class half bridge test board. As input for the simulations the thermal conductivity of prepreg materials were measured. It could be shown that layer thicknesses have a significant impact of the necessary cooling power. The embedding of chips directly into laminated substrates seems reliable regarding thermal loading. Further results will be obtained by thermal measurements.
{"title":"Thermal design of a high current circuit board for automotive applications","authors":"R. Mrossko, C. Neeb, T. Hofmann, A. Neumann, J. Keller","doi":"10.1109/THERMINIC.2013.6675245","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675245","url":null,"abstract":"The demand of cost reduction and limited installation space for automotive applications requires new and innovative approaches. One approach is to substitute DCB substrates with high current circuit boards. These circuit boards with fully embedded actives like IGBTs and Diodes allows to avoid the use of bonding wires at all and benefit from the less expensive standard circuit board technologies. Moreover it should be possible to use double sided cooling for such devices. In this paper we investigate the influence of several geometry and material parameter, like layer thicknesses, thermal conductivity and cooling power on the thermal performance of a fully embedded 650V class half bridge test board. As input for the simulations the thermal conductivity of prepreg materials were measured. It could be shown that layer thicknesses have a significant impact of the necessary cooling power. The embedding of chips directly into laminated substrates seems reliable regarding thermal loading. Further results will be obtained by thermal measurements.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115241162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675188
M. AboRas, G. Engelmann, D. May, M. Rothermund, R. Schacht, B. Wunderle, H. Oppermann, T. Winkler, S. Rzepka, B. Michel
This paper deals with the development und fabrication of a thermal test chip (TTC) to be used for thermal characterisation and qualification of materials and packages. The TTC is designed as a modular chip with the smallest full functional chip cell of 3.2mm × 3.2mm and consists of a heater structure and a temperature sensor. The chips can be applied in any required matrix. Heater and temperature sensors are realised by a 70 nm single Titanium layer as adhesion and barrier layer. The Titanium is structured a on 670μm silicon wafer by the cost efficient thin film technology. 3×3 matrix chips have been sawn, assembled on a FR4 substrate by flip chip technology and integrated into a test stand for characterisation of thermal interface materials (TIMA Tester). The calibration curves of the temperature sensors show 4-time higher sensitivity then Si diodes. The homogeneity of the surface temperature was checked by the Lock-In infra-red thermography and compared with a commercial thermo test chip.
{"title":"Development and fabrication of a thin film thermo test chip and its integration into a test system for thermal interface characterization","authors":"M. AboRas, G. Engelmann, D. May, M. Rothermund, R. Schacht, B. Wunderle, H. Oppermann, T. Winkler, S. Rzepka, B. Michel","doi":"10.1109/THERMINIC.2013.6675188","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675188","url":null,"abstract":"This paper deals with the development und fabrication of a thermal test chip (TTC) to be used for thermal characterisation and qualification of materials and packages. The TTC is designed as a modular chip with the smallest full functional chip cell of 3.2mm × 3.2mm and consists of a heater structure and a temperature sensor. The chips can be applied in any required matrix. Heater and temperature sensors are realised by a 70 nm single Titanium layer as adhesion and barrier layer. The Titanium is structured a on 670μm silicon wafer by the cost efficient thin film technology. 3×3 matrix chips have been sawn, assembled on a FR4 substrate by flip chip technology and integrated into a test stand for characterisation of thermal interface materials (TIMA Tester). The calibration curves of the temperature sensors show 4-time higher sensitivity then Si diodes. The homogeneity of the surface temperature was checked by the Lock-In infra-red thermography and compared with a commercial thermo test chip.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114165699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675181
N. Thierry-Jebali, R. Chiriac, C. Brylinski
This work reports on DSC measurements performed on Ti-Al metallic layers stacks deposited on n+-GaN. The aim is to get better understanding of the mechanisms leading to ohmic contact formation during the annealing stage. Two exothermic DSC peaks were found : one below 500°C and the other one around 660°C. They can be respectively attributed to Al3Ti and Al2Ti compounds formation. Lowest contact resistance is well correlated with the presence of Al3Ti compound, corresponding to Al(200nm) / Ti(50nm) stoichiometric ratio. Subsequently, Al (200 nm) / Ti(50 nm) stacks on n+-GaN were comparatively annealed from 400 °C to 650 °C. Specific Contact Resistivity (SCR) values stay in the mid 10-5 Ω.cm2 range for annealing temperatures between 450 °C and 650 °C. Such low-temperature annealed contacts on n+-GaN may open new device processing routes, simpler and cheaper, in which Ohmic and Schottky contacts are annealed together.
{"title":"Characterization and kinetic monitoring of the reactions between TixAly phases in Ti-Al based ohmic contacts on n-type GaN by Differential Scanning Calorimetry (DSC)","authors":"N. Thierry-Jebali, R. Chiriac, C. Brylinski","doi":"10.1109/THERMINIC.2013.6675181","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675181","url":null,"abstract":"This work reports on DSC measurements performed on Ti-Al metallic layers stacks deposited on n+-GaN. The aim is to get better understanding of the mechanisms leading to ohmic contact formation during the annealing stage. Two exothermic DSC peaks were found : one below 500°C and the other one around 660°C. They can be respectively attributed to Al3Ti and Al2Ti compounds formation. Lowest contact resistance is well correlated with the presence of Al3Ti compound, corresponding to Al(200nm) / Ti(50nm) stoichiometric ratio. Subsequently, Al (200 nm) / Ti(50 nm) stacks on n+-GaN were comparatively annealed from 400 °C to 650 °C. Specific Contact Resistivity (SCR) values stay in the mid 10-5 Ω.cm2 range for annealing temperatures between 450 °C and 650 °C. Such low-temperature annealed contacts on n+-GaN may open new device processing routes, simpler and cheaper, in which Ohmic and Schottky contacts are annealed together.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116050580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675217
C. Bailey
This paper details current status of modelling for power electronics modules and details the challenges in terms of electrical, thermal, reliability and robustness analysis. Multi-domain, multi-physics and multi-objective optimisation toolsets are urgently required for future integrated power electronics. The paper illustrates future trends in power module designs and provides examples of current modelling toolsets and developments in multi-domain (physics) analysis.
{"title":"Multi-physics modelling for power electronics modules - Current status and future challenges","authors":"C. Bailey","doi":"10.1109/THERMINIC.2013.6675217","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675217","url":null,"abstract":"This paper details current status of modelling for power electronics modules and details the challenges in terms of electrical, thermal, reliability and robustness analysis. Multi-domain, multi-physics and multi-objective optimisation toolsets are urgently required for future integrated power electronics. The paper illustrates future trends in power module designs and provides examples of current modelling toolsets and developments in multi-domain (physics) analysis.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121317950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-02DOI: 10.1109/THERMINIC.2013.6675232
W. Luiten
Solder joint reliability is one of the most important factors in the lifetime of electronic products. Typically solder joint lifetimes are expressed in numbers of cycles to failure, which are derived from accelerated temperature cycle tests. The extrapolation of test results from the test temperature range to the temperature range in operation is well known. In contrast, the effect of the time scale differences between the test and the operational condition is much more complicated and is often not taken into account. The present work addresses the effect of cycle-time on the solder fatigue. A 1D analytical model is made of a shear loaded solder joint, and a spreadsheet is used to calculate time dependent stress relaxation, including the highly nonlinear material behavior of lead free solder. The results are used to estimate safe engineering limits for lead free solder joints of LEDs driven in short time cycles typical for video signals in in a TV product. It is shown that above and below a certain threshold value the cycle time has no influence on the number of cycles to failure. When cycle times are very short, no solder creep occurs, and such cycles have no impact on the total number of cycles to failure. When cycles times are very long, solder creep occurs up to the stress free situation, and a maximum damage per cycle is incurred, corresponding to a minimum number of cycles to failure. Longer cycle times again do not impact this minimum number of cycles to failure. However when the cycle time allows for partial solder creep, the damage incurred in each cycle is less than the maximum and consequently the number of cycles to failure will be correspondingly higher, dependant on the cycle time.
{"title":"Solder joint lifetime of rapid cycled LED components","authors":"W. Luiten","doi":"10.1109/THERMINIC.2013.6675232","DOIUrl":"https://doi.org/10.1109/THERMINIC.2013.6675232","url":null,"abstract":"Solder joint reliability is one of the most important factors in the lifetime of electronic products. Typically solder joint lifetimes are expressed in numbers of cycles to failure, which are derived from accelerated temperature cycle tests. The extrapolation of test results from the test temperature range to the temperature range in operation is well known. In contrast, the effect of the time scale differences between the test and the operational condition is much more complicated and is often not taken into account. The present work addresses the effect of cycle-time on the solder fatigue. A 1D analytical model is made of a shear loaded solder joint, and a spreadsheet is used to calculate time dependent stress relaxation, including the highly nonlinear material behavior of lead free solder. The results are used to estimate safe engineering limits for lead free solder joints of LEDs driven in short time cycles typical for video signals in in a TV product. It is shown that above and below a certain threshold value the cycle time has no influence on the number of cycles to failure. When cycle times are very short, no solder creep occurs, and such cycles have no impact on the total number of cycles to failure. When cycles times are very long, solder creep occurs up to the stress free situation, and a maximum damage per cycle is incurred, corresponding to a minimum number of cycles to failure. Longer cycle times again do not impact this minimum number of cycles to failure. However when the cycle time allows for partial solder creep, the damage incurred in each cycle is less than the maximum and consequently the number of cycles to failure will be correspondingly higher, dependant on the cycle time.","PeriodicalId":369128,"journal":{"name":"19th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128352107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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