This paper discuss electrical characterization of new developed hybrid package, FusionQuad, that is converging QFN and TQFP type package to have good electrical performance with high I/O pin counts. Precise electrical modelling from wire-to-motherboard is performed by using simple organic based test die with de-embedding technique to cope with limits of assembly process. Measurements are done in the frequency domain to extract S-parameter up to 10 GHz.
{"title":"Novel electrical modelling and measurement technique of hybrid package (FusionQuad) for characterization of RF and high speed signals","authors":"Seungjae Lee, Kicheol Bae, Jiheon Yu, Youngsuk Chung, Chanha Hwang, Choonheung Lee","doi":"10.1109/EDAPS.2009.5404000","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404000","url":null,"abstract":"This paper discuss electrical characterization of new developed hybrid package, FusionQuad, that is converging QFN and TQFP type package to have good electrical performance with high I/O pin counts. Precise electrical modelling from wire-to-motherboard is performed by using simple organic based test die with de-embedding technique to cope with limits of assembly process. Measurements are done in the frequency domain to extract S-parameter up to 10 GHz.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130377371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403993
D. Lin, Chun-Te Wu, Kuo-Chiang Hung, Feng-Nan Wu
This paper presents a modified segmentation method that can be used in the fast algorithm to calculate the transfer impedance of an arbitrarily shaped power-bus at any port location. Being different from conventional studies that only discuss two rectangular shapes, the present study extends the segmentation method to cascade any number of power planes that contain triangular and rectangular shapes. The transfer impedance of an irregular power-bus is obtained by cascading a few rectangular and isosceles triangular power-buses. Good agreement between simulate and experimental results which indicates the validity of the modified segmentation method.
{"title":"Single summation expression in combination with modified segmentation method for calculating transfer impedance of an arbitrary shaped power bus","authors":"D. Lin, Chun-Te Wu, Kuo-Chiang Hung, Feng-Nan Wu","doi":"10.1109/EDAPS.2009.5403993","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403993","url":null,"abstract":"This paper presents a modified segmentation method that can be used in the fast algorithm to calculate the transfer impedance of an arbitrarily shaped power-bus at any port location. Being different from conventional studies that only discuss two rectangular shapes, the present study extends the segmentation method to cascade any number of power planes that contain triangular and rectangular shapes. The transfer impedance of an irregular power-bus is obtained by cascading a few rectangular and isosceles triangular power-buses. Good agreement between simulate and experimental results which indicates the validity of the modified segmentation method.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127877789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5404002
T. Ishimaru, T. Sekine, H. Asai
In this paper, a technique to simulate efficiently the power distribution network (PDN) is introduced. In the proposed approach, the circuit equation of the PDN is formulated by using the RLCG-MNA method. Then, the transient analysis of the PDN is performed by using the semi-implicit numerical integration method. The numerical results of the proposed approach are compared with those of SPICE-like simulator in order to verify the accuracy and the efficiency of the proposed method. As a result, it is confirmed that the fast and accurate simulation can be performed by the proposed approach.
{"title":"Fast simulation of power distribution networks based on semi-implicit numerical integration method and RLCG-MNA formulation","authors":"T. Ishimaru, T. Sekine, H. Asai","doi":"10.1109/EDAPS.2009.5404002","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404002","url":null,"abstract":"In this paper, a technique to simulate efficiently the power distribution network (PDN) is introduced. In the proposed approach, the circuit equation of the PDN is formulated by using the RLCG-MNA method. Then, the transient analysis of the PDN is performed by using the semi-implicit numerical integration method. The numerical results of the proposed approach are compared with those of SPICE-like simulator in order to verify the accuracy and the efficiency of the proposed method. As a result, it is confirmed that the fast and accurate simulation can be performed by the proposed approach.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122737663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403998
Yaojiang Zhang, E. Li, J. Fan
The drawbacks of conventional power-bus impedance, defined as an average Green's function integration over port areas, are discussed. A new definition is proposed in terms of cylindrical waves. The equivalence of the new definition and the conventional one is proved in the case of electrically small ports. Addition theorems of cylindrical waves are used to derive an analytical expression of power-bus impedance between ports in a circular plate pair with perfectly electric/magnetic conductor (PEC/PMC) boundaries as well as non-reflective perfectly matched layer (PML) for infinite plate pair. Numerical method has been used to validate the analytical expression derived.
{"title":"Closed-form expression of self/mutual power-bus impedances in a finite circular plate pair","authors":"Yaojiang Zhang, E. Li, J. Fan","doi":"10.1109/EDAPS.2009.5403998","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403998","url":null,"abstract":"The drawbacks of conventional power-bus impedance, defined as an average Green's function integration over port areas, are discussed. A new definition is proposed in terms of cylindrical waves. The equivalence of the new definition and the conventional one is proved in the case of electrically small ports. Addition theorems of cylindrical waves are used to derive an analytical expression of power-bus impedance between ports in a circular plate pair with perfectly electric/magnetic conductor (PEC/PMC) boundaries as well as non-reflective perfectly matched layer (PML) for infinite plate pair. Numerical method has been used to validate the analytical expression derived.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128727009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5404015
Xu-min Yu, Juan Wang, Xiaohong Tang
A new wide-band 180° micro-strip phase shifter network on TP-2 is presented in this paper. The network is composed of coupled lines and double 45° open and short stubs, which are shunted at the edge points of the main line respectively. To demonstrate the design methodology, a new structure 180° phase shifter network, operated at 3.5∼5.5GHz, were designed and fabricated using the design graphs, and were experimented. The measured performances of the phase shifter network were well in agreement with the corresponding the simulation ones over the operating bands, and showed broadband phase characteristics.
{"title":"A new wide-band 180° planar phase shifter network","authors":"Xu-min Yu, Juan Wang, Xiaohong Tang","doi":"10.1109/EDAPS.2009.5404015","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404015","url":null,"abstract":"A new wide-band 180° micro-strip phase shifter network on TP-2 is presented in this paper. The network is composed of coupled lines and double 45° open and short stubs, which are shunted at the edge points of the main line respectively. To demonstrate the design methodology, a new structure 180° phase shifter network, operated at 3.5∼5.5GHz, were designed and fabricated using the design graphs, and were experimented. The measured performances of the phase shifter network were well in agreement with the corresponding the simulation ones over the operating bands, and showed broadband phase characteristics.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129587630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403987
Jeonghyeon Cho, Eakhwan Song, J. Shim, Yujeong Shim, Joungho Kim
In this paper, we propose a fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCBs with arbitrary source and load terminations. The voltage transfer function of a channel is investigated as a quick measure of the signal integrity of a channel and the DDJ and eye-opening voltage values are precisely estimated by using a modified peak distortion analysis. The efficiency and the accuracy of the proposed eye-diagram estimation method were successfully verified through HSPICE simulations.
{"title":"A fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCB with arbitrary terminations","authors":"Jeonghyeon Cho, Eakhwan Song, J. Shim, Yujeong Shim, Joungho Kim","doi":"10.1109/EDAPS.2009.5403987","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403987","url":null,"abstract":"In this paper, we propose a fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCBs with arbitrary source and load terminations. The voltage transfer function of a channel is investigated as a quick measure of the signal integrity of a channel and the DDJ and eye-opening voltage values are precisely estimated by using a modified peak distortion analysis. The efficiency and the accuracy of the proposed eye-diagram estimation method were successfully verified through HSPICE simulations.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5404013
R. Lee, Hung-Ming Chen
In this paper, we propose an improved pin-block placer to optimize the objectives of shorter path length and equi-length on package routing. This placer keeps the same minimized package size as the recent work and ensure that signal integrity (SI), power delivery integrity (PI) and routability (RA) can still be considered with significant reduction in design cost. It is achieved by relaxing the restriction of pin-block side and order on the package, usually specified by package designers. The experimental results on industrial chipset design cases show that the average improvement of our pin-block planner is over 40% when comparing the design cost with the previous work, among which we have one case over a thousand pins.
{"title":"A package pin-block planner considering chip-package interconnects optimization","authors":"R. Lee, Hung-Ming Chen","doi":"10.1109/EDAPS.2009.5404013","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404013","url":null,"abstract":"In this paper, we propose an improved pin-block placer to optimize the objectives of shorter path length and equi-length on package routing. This placer keeps the same minimized package size as the recent work and ensure that signal integrity (SI), power delivery integrity (PI) and routability (RA) can still be considered with significant reduction in design cost. It is achieved by relaxing the restriction of pin-block side and order on the package, usually specified by package designers. The experimental results on industrial chipset design cases show that the average improvement of our pin-block planner is over 40% when comparing the design cost with the previous work, among which we have one case over a thousand pins.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128538573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403990
Hyunju Lee, Soonseo Park, Sung-Kyo Cho, Hyojong Kim, Shiho Kim
A thin film solid state cooler for COB direct assembly using supperlattice based thermoelectric material is reported. The embedded cooler attached between the die chip and metal plate can provide site-specific cooling as well as active on-demand cooling. This demonstration offers the possibility of thin film active cooling for the COB direct assembly. The high power density of chip-on-Board would be no longer be limited by cooling capability. This technology can be extended to the case of hot spot cooling for COB assembly that can be selectively switched on and off depending on which part of the chip is in critical need of cooling at any point of time.
{"title":"A thin film thermoelectric cooler for chip-on-board direct assembly","authors":"Hyunju Lee, Soonseo Park, Sung-Kyo Cho, Hyojong Kim, Shiho Kim","doi":"10.1109/EDAPS.2009.5403990","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403990","url":null,"abstract":"A thin film solid state cooler for COB direct assembly using supperlattice based thermoelectric material is reported. The embedded cooler attached between the die chip and metal plate can provide site-specific cooling as well as active on-demand cooling. This demonstration offers the possibility of thin film active cooling for the COB direct assembly. The high power density of chip-on-Board would be no longer be limited by cooling capability. This technology can be extended to the case of hot spot cooling for COB assembly that can be selectively switched on and off depending on which part of the chip is in critical need of cooling at any point of time.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403992
Sang-Gyu Kim, H. Kim, Hee-Do Kang, J. Yook
Transmission line method (TLM) is applied for analysis of a conventional electromagnetic bandgap (EBG) structure with arbitrary shaped power/ground plane. The fast and accurate modeling by TLM shows the computationally efficient results with respect to full-wave electromagnetic analysis. More-over it is shown that suppression bandwidth of a EBG structure can be easily analyzed by stepped impedance filter and the calculated bandwidth is identical to the measured.
{"title":"Modeling and analysis of electromagnetic bandgap structures on power distribution network","authors":"Sang-Gyu Kim, H. Kim, Hee-Do Kang, J. Yook","doi":"10.1109/EDAPS.2009.5403992","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403992","url":null,"abstract":"Transmission line method (TLM) is applied for analysis of a conventional electromagnetic bandgap (EBG) structure with arbitrary shaped power/ground plane. The fast and accurate modeling by TLM shows the computationally efficient results with respect to full-wave electromagnetic analysis. More-over it is shown that suppression bandwidth of a EBG structure can be easily analyzed by stepped impedance filter and the calculated bandwidth is identical to the measured.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130846824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5404005
J. Kho, C. I. Loh, Wui Hung Moo, C. Fong, M. Wong
Electronic devices are increasingly susceptible to simultaneous switching noise (SSN) as devices shrink in size and operate at lower voltage to achieve higher speed. This is a major concern in high-speed system designs as SSN causes voltage and timing variations which affect signal integrity. Consequently, it is imperative that electronic system designers pay strict attention to signal integrity whether it is on the chip level or on the system level. This paper analyzes the output buffer SSN effect on the phase-locked loop (PLL) input pins, PLL output pins, and PLL power supplies using an Altera FPGA device. Experimental results show that direct PLL jitter transfer principle cannot be applied in a straight forward manner because of the wide spectrum and asynchronous nature of SSN. However, the PLL circuit is still effective in filtering the noise that is attacking the PLL input signal. This paper also shows that SSN greatly affects the PLL power distribution network (PDN) especially when the noise coupled into the PDN have the same frequency as the PDN resonance. In addition, it is also shown that SSN do not directly attack the PLL circuit through its output. These findings assist Altera's customers and electronic system designers in optimizing PLL performance for error-free device designs. Furthermore, the findings provide a basis future PLL design improvements.
{"title":"Extended analysis of SSN effect on phase-locked loop (PLL) circuit","authors":"J. Kho, C. I. Loh, Wui Hung Moo, C. Fong, M. Wong","doi":"10.1109/EDAPS.2009.5404005","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404005","url":null,"abstract":"Electronic devices are increasingly susceptible to simultaneous switching noise (SSN) as devices shrink in size and operate at lower voltage to achieve higher speed. This is a major concern in high-speed system designs as SSN causes voltage and timing variations which affect signal integrity. Consequently, it is imperative that electronic system designers pay strict attention to signal integrity whether it is on the chip level or on the system level. This paper analyzes the output buffer SSN effect on the phase-locked loop (PLL) input pins, PLL output pins, and PLL power supplies using an Altera FPGA device. Experimental results show that direct PLL jitter transfer principle cannot be applied in a straight forward manner because of the wide spectrum and asynchronous nature of SSN. However, the PLL circuit is still effective in filtering the noise that is attacking the PLL input signal. This paper also shows that SSN greatly affects the PLL power distribution network (PDN) especially when the noise coupled into the PDN have the same frequency as the PDN resonance. In addition, it is also shown that SSN do not directly attack the PLL circuit through its output. These findings assist Altera's customers and electronic system designers in optimizing PLL performance for error-free device designs. Furthermore, the findings provide a basis future PLL design improvements.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125095456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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