Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403982
Xiaochun Li, Junfa Mao, M. Swaminathan
This paper introduces an accurate FDTD-based method for analysis of time domain response of frequency-dependent lossy transmission lines driven by CMOS gates. MOS transistors are modeled as the nonlinear alpha-power law model that includes the carriers' velocity saturation effect of short-channel devices. The dynamic behavior of CMOS gates during switching is defined in seven operation regions. Skin effects of lossy transmission line are included in the proposed method and analyzed with FDTD. The proposed method is accurate by comparison between the numerical results of the proposed method and the simulation results of SPICE.
{"title":"Analysis of frequency-dependent lossy transmission lines driven by CMOS gates","authors":"Xiaochun Li, Junfa Mao, M. Swaminathan","doi":"10.1109/EDAPS.2009.5403982","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403982","url":null,"abstract":"This paper introduces an accurate FDTD-based method for analysis of time domain response of frequency-dependent lossy transmission lines driven by CMOS gates. MOS transistors are modeled as the nonlinear alpha-power law model that includes the carriers' velocity saturation effect of short-channel devices. The dynamic behavior of CMOS gates during switching is defined in seven operation regions. Skin effects of lossy transmission line are included in the proposed method and analyzed with FDTD. The proposed method is accurate by comparison between the numerical results of the proposed method and the simulation results of SPICE.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115333943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403999
Huifen Huang, Qingxin Chu, Jiankang Xiao
In this paper, fractal power network has been proposed. The fractal structure is designed based on leaf vein. The simulated and measured results illustrate that the designed power network has greatly improved noise isolation, resistive and inductive voltage drop, and “Swiss Cheese” effect (There are many vias in the power plane just like many holes in Swiss Cheese. These via areas and their associated anti-pads forms high resistance areas and lead to the voltages or currents to the circuit — elements lower than design demand).
{"title":"A novel on-chip fractal power tree network based on leaf vein grids","authors":"Huifen Huang, Qingxin Chu, Jiankang Xiao","doi":"10.1109/EDAPS.2009.5403999","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403999","url":null,"abstract":"In this paper, fractal power network has been proposed. The fractal structure is designed based on leaf vein. The simulated and measured results illustrate that the designed power network has greatly improved noise isolation, resistive and inductive voltage drop, and “Swiss Cheese” effect (There are many vias in the power plane just like many holes in Swiss Cheese. These via areas and their associated anti-pads forms high resistance areas and lead to the voltages or currents to the circuit — elements lower than design demand).","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129919117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ECTC.2010.5490780
Ruonan Wang, Robin Lou, K. Cheng, Yeung Yeung, Lydia Leung, Jyh-Rong Lin, T. Chung
A thin-film on modified ceramic (TFoMC) based substrate technology for achieving high-accuracy and high-uniformity design has been developed and implemented. The integrated passive devices (IPDs), including capacitors, inductors, band-pass filters and Baluns, were realized based on the proposed TFoMC technology. The IPD characterization results were close to the HFSS simulation, and demonstrated good in-substrate uniformity at the same time. The thermal shock and unbiased autoclave measurements were also carried out to evaluate the reliability of the technology. After 1000-cycle thermal shock and 96-hour autoclave storage, the IPDs exhibited no performance degradation, indicating the excellent substrate reliability and making it a promising technology for the wireless-related applications.
{"title":"A low-cost high-density substrate technology for wireless-related applications","authors":"Ruonan Wang, Robin Lou, K. Cheng, Yeung Yeung, Lydia Leung, Jyh-Rong Lin, T. Chung","doi":"10.1109/ECTC.2010.5490780","DOIUrl":"https://doi.org/10.1109/ECTC.2010.5490780","url":null,"abstract":"A thin-film on modified ceramic (TFoMC) based substrate technology for achieving high-accuracy and high-uniformity design has been developed and implemented. The integrated passive devices (IPDs), including capacitors, inductors, band-pass filters and Baluns, were realized based on the proposed TFoMC technology. The IPD characterization results were close to the HFSS simulation, and demonstrated good in-substrate uniformity at the same time. The thermal shock and unbiased autoclave measurements were also carried out to evaluate the reliability of the technology. After 1000-cycle thermal shock and 96-hour autoclave storage, the IPDs exhibited no performance degradation, indicating the excellent substrate reliability and making it a promising technology for the wireless-related applications.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403997
Chih-Chun Tsai, Yung-Shou Cheng, Ting-Yi Huang, R. Wu
A wide-band microstrip-to-microstrip via transition used for connecting integrated circuits and antenna array in a multi-layered low-temperature co-fired ceramic substrate is investigated in this paper. The via transition is decomposed into external and internal segments to facilitate the design. The equivalent impedance of internal segment, consisting of multi-layered through-hole via with four ground vias, is calculated from the lump-circuit model generated by Ansoft Q3D Extractor. The electrical performance of the external segment, consisting of via to microstrip lines, is evaluated by the microstrip-to-coax transition to choose appropriate via physical parameters. Finally, the geometrical parameters of entire transition are obtained by combining the results of the external and internal segments. It has been demonstrated, through the simulation results by commercial software Ansoft HFSS, that the return loss is better than 19dB over a band from DC up to 70GHz with an in-band insertion loss better than 0.48dB.
{"title":"A wide-band microstrip-to-microstrip multi-layered via transition using LTCC technology","authors":"Chih-Chun Tsai, Yung-Shou Cheng, Ting-Yi Huang, R. Wu","doi":"10.1109/EDAPS.2009.5403997","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403997","url":null,"abstract":"A wide-band microstrip-to-microstrip via transition used for connecting integrated circuits and antenna array in a multi-layered low-temperature co-fired ceramic substrate is investigated in this paper. The via transition is decomposed into external and internal segments to facilitate the design. The equivalent impedance of internal segment, consisting of multi-layered through-hole via with four ground vias, is calculated from the lump-circuit model generated by Ansoft Q3D Extractor. The electrical performance of the external segment, consisting of via to microstrip lines, is evaluated by the microstrip-to-coax transition to choose appropriate via physical parameters. Finally, the geometrical parameters of entire transition are obtained by combining the results of the external and internal segments. It has been demonstrated, through the simulation results by commercial software Ansoft HFSS, that the return loss is better than 19dB over a band from DC up to 70GHz with an in-band insertion loss better than 0.48dB.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133023311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5404007
R. Lee, Hung-Ming Chen
While the advanced very large scale integration (VLSI) circuit is scaling to deep-submicrometer (DSM) technology, the I/O placement plays a key role in affecting the die size and interconnect. The flip-chip area-array ICs meet the requirements of higher I/O density and lower parasitic effects, but essentially need the optimized I/O and bump placement. In this paper we skip the redistribution layer (RDL) routing and design the specific I/O-bump tiles based on an innovative I/O-row scheme. By considering the package ball location, our proposed I/O-bump planning methodologies produce a package-aware I/O-bump location for chip-level core cell placement and package-level routing task. Thus, our algorithms provide the concurrent chip-package coplanning/codesign flow and dramatically speed up the design process. The experimental results show that our methods optimize the performance metrics in designing the interface between chip and package, such as the net crossing, total wirelength and length deviation.
{"title":"Novel I/O-bump design and optimization for chip-package codesign","authors":"R. Lee, Hung-Ming Chen","doi":"10.1109/EDAPS.2009.5404007","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404007","url":null,"abstract":"While the advanced very large scale integration (VLSI) circuit is scaling to deep-submicrometer (DSM) technology, the I/O placement plays a key role in affecting the die size and interconnect. The flip-chip area-array ICs meet the requirements of higher I/O density and lower parasitic effects, but essentially need the optimized I/O and bump placement. In this paper we skip the redistribution layer (RDL) routing and design the specific I/O-bump tiles based on an innovative I/O-row scheme. By considering the package ball location, our proposed I/O-bump planning methodologies produce a package-aware I/O-bump location for chip-level core cell placement and package-level routing task. Thus, our algorithms provide the concurrent chip-package coplanning/codesign flow and dramatically speed up the design process. The experimental results show that our methods optimize the performance metrics in designing the interface between chip and package, such as the net crossing, total wirelength and length deviation.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114751863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403975
Liang Wu, Yang Hou, R. Qian, Xiaowei Sun
This paper analyzes two of the most important discontinuity effects of the transmission line in MMIC design. Both the marginal effect and discontinued ground plane have been considered to avoid deterioration of the circuit. A fully integrated receiver front end MMIC chip which is constructed with a three stage low noise amplifier cascaded with a resistive mixer for millimeter wave down conversion application has been achieved by using above mentioned analysis results of discontinuity effects. This multifunctional chip operates at RF frequency range from 24GHz to 40GHz, IF frequency up to 1GHz.
{"title":"Analysis of discontinuity effects in development a fully integrated millimeter wave receiver front end","authors":"Liang Wu, Yang Hou, R. Qian, Xiaowei Sun","doi":"10.1109/EDAPS.2009.5403975","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403975","url":null,"abstract":"This paper analyzes two of the most important discontinuity effects of the transmission line in MMIC design. Both the marginal effect and discontinued ground plane have been considered to avoid deterioration of the circuit. A fully integrated receiver front end MMIC chip which is constructed with a three stage low noise amplifier cascaded with a resistive mixer for millimeter wave down conversion application has been achieved by using above mentioned analysis results of discontinuity effects. This multifunctional chip operates at RF frequency range from 24GHz to 40GHz, IF frequency up to 1GHz.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130983478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403981
Te-Chun Wang, Yin-Guang Zheng
Impedance control has been widely applied to PCB and IC packaging substrate manufacturing for better interconnect signal quality. In the IC packaging manufacturing using organic dielectric materials for the substrate, we have already found that a post-simulation with cross section geometry can give us an “effective dielectric constant” to bridge the gap between the simulation and the measurement of the characteristic impedance. We also found that the impedance monitoring not only can be a tool to control the electrical property of the products, it can also help non-destructively to control the quality of the production such as the uniformity of the dielectric thickness. In this report we show an example of the impedance-monitored production. The dielectric thickness-induced impedance variation has been investigated. The difference between two units in a same panel was pointed out. The impedance values of a specific trace set in all the units of the production panel were shown to have a clear correlation with the dielectric thickness variation. The impedance monitoring has proven to be an effective non-destructive method to provide direct information for the quality control of substrate or PCB production.
{"title":"Application of trace impedance monitoring on production quality control","authors":"Te-Chun Wang, Yin-Guang Zheng","doi":"10.1109/EDAPS.2009.5403981","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403981","url":null,"abstract":"Impedance control has been widely applied to PCB and IC packaging substrate manufacturing for better interconnect signal quality. In the IC packaging manufacturing using organic dielectric materials for the substrate, we have already found that a post-simulation with cross section geometry can give us an “effective dielectric constant” to bridge the gap between the simulation and the measurement of the characteristic impedance. We also found that the impedance monitoring not only can be a tool to control the electrical property of the products, it can also help non-destructively to control the quality of the production such as the uniformity of the dielectric thickness. In this report we show an example of the impedance-monitored production. The dielectric thickness-induced impedance variation has been investigated. The difference between two units in a same panel was pointed out. The impedance values of a specific trace set in all the units of the production panel were shown to have a clear correlation with the dielectric thickness variation. The impedance monitoring has proven to be an effective non-destructive method to provide direct information for the quality control of substrate or PCB production.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403985
Yoshiyuki Takasu, K. Kikuchi, H. Nakagawa, K. Koshiji, M. Aoyagi
High-speed signal transmission of over 10 Gbps is required even for the signal transmission line of printed circuit boards (PCBs). To realize high-speed signal transmission, we developed a PCB technology with a rectangular coaxial line structure. The coaxial line structure is suitable for high-speed signal transmission because of its realization of precise characteristic impedance control and low crosstalk. In this paper, we report the high-frequency characteristics of coaxial bend and via structures in comparison with those of a microstrip-line structure obtained using a three-dimensional electromagnetic field simulation.
{"title":"Simulated high-frequency characteristics of coaxial via connection structures in printed circuit boards using three-dimensional electromagnetic field analysis","authors":"Yoshiyuki Takasu, K. Kikuchi, H. Nakagawa, K. Koshiji, M. Aoyagi","doi":"10.1109/EDAPS.2009.5403985","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403985","url":null,"abstract":"High-speed signal transmission of over 10 Gbps is required even for the signal transmission line of printed circuit boards (PCBs). To realize high-speed signal transmission, we developed a PCB technology with a rectangular coaxial line structure. The coaxial line structure is suitable for high-speed signal transmission because of its realization of precise characteristic impedance control and low crosstalk. In this paper, we report the high-frequency characteristics of coaxial bend and via structures in comparison with those of a microstrip-line structure obtained using a three-dimensional electromagnetic field simulation.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116172481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403973
Yong-sheng Dai, Sheng-Lei Xiao, Zhong-Hua Ye, De-Long Lu, Wen-Kan Zhou, You-Fang Yao, Guang-Qiang Fu, Jie Zhang, Yu-Hong Guo, Shaozhong Chen
This paper presented a design and simulation result of a miniaturized complementary diplexer realized by low-temperature co-fired ceramic (LTCC) technology. The diplexer consisted of two pass-bands, a central frequency of 1.175GHz with bandwidth of 46.8% and a central frequency of 1.925GHz with bandwidth of 28.6% respectively. In the presented structure, we used transmission lines to realize the characteristics of lower pass-band, while lumped circular inductors were adopted to achieve the requirements of upper pass-band. The interaction of the two filters was handled very well by using a complementary schematic. We managed to make the VSWR on the antenna port less than 1.7. The final three-dimensional model occupied a volume of 3.2×2.5×1.95-mm.
{"title":"A miniaturized wideband complementary LTCC diplexer based on transmission lines and lumped elements","authors":"Yong-sheng Dai, Sheng-Lei Xiao, Zhong-Hua Ye, De-Long Lu, Wen-Kan Zhou, You-Fang Yao, Guang-Qiang Fu, Jie Zhang, Yu-Hong Guo, Shaozhong Chen","doi":"10.1109/EDAPS.2009.5403973","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403973","url":null,"abstract":"This paper presented a design and simulation result of a miniaturized complementary diplexer realized by low-temperature co-fired ceramic (LTCC) technology. The diplexer consisted of two pass-bands, a central frequency of 1.175GHz with bandwidth of 46.8% and a central frequency of 1.925GHz with bandwidth of 28.6% respectively. In the presented structure, we used transmission lines to realize the characteristics of lower pass-band, while lumped circular inductors were adopted to achieve the requirements of upper pass-band. The interaction of the two filters was handled very well by using a complementary schematic. We managed to make the VSWR on the antenna port less than 1.7. The final three-dimensional model occupied a volume of 3.2×2.5×1.95-mm.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124006722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/EDAPS.2009.5403989
K. Hoshino, R. Satomi, T. Sudo, H. Okano, M. Ishikawa, H. Shibayama, H. Aoyagi, H. Kushibe, K. Yamagishi
Power distribution network (PDN) of LSI has become one of important design parameters to reduce simultaneous switching noise for core circuits as well as I/O circuits. Power distribution network of LSI generally consists of meshed power and ground conductors and on-chip decoupling capacitors. For mobile communication and automotive applications, switching current of high-performance CMOS LSIs must be controlled to be low as possible in order to suppress associated electromagnetic interference (EMI). Therefore, on-chip decoupling capacitors must be properly arranged on a chip to optimize the amount of capacitor and to minimize the occupied area by on-chip capacitor. In this paper, a CMOS test chip has been developed which has several test element groups (TEGs) inside. MOS capacitor cells were distributed in each TEG in a different density. Then, an evaluation board was designed to measure the power supply switching current for the each TEG. Furthermore, the power supply switching current was simulated by using a commercial available EDA tool. Reduction level of the switching current was measured and simulated as a function of the value of on-chip decoupling capacitor. Based on both experimental and simulation results, it has been probed that proper density of decoupling capacitor on a chip has been well estimated.
{"title":"Experiment and simulation of power supply switching current dependency on on-chip capacitance","authors":"K. Hoshino, R. Satomi, T. Sudo, H. Okano, M. Ishikawa, H. Shibayama, H. Aoyagi, H. Kushibe, K. Yamagishi","doi":"10.1109/EDAPS.2009.5403989","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403989","url":null,"abstract":"Power distribution network (PDN) of LSI has become one of important design parameters to reduce simultaneous switching noise for core circuits as well as I/O circuits. Power distribution network of LSI generally consists of meshed power and ground conductors and on-chip decoupling capacitors. For mobile communication and automotive applications, switching current of high-performance CMOS LSIs must be controlled to be low as possible in order to suppress associated electromagnetic interference (EMI). Therefore, on-chip decoupling capacitors must be properly arranged on a chip to optimize the amount of capacitor and to minimize the occupied area by on-chip capacitor. In this paper, a CMOS test chip has been developed which has several test element groups (TEGs) inside. MOS capacitor cells were distributed in each TEG in a different density. Then, an evaluation board was designed to measure the power supply switching current for the each TEG. Furthermore, the power supply switching current was simulated by using a commercial available EDA tool. Reduction level of the switching current was measured and simulated as a function of the value of on-chip decoupling capacitor. Based on both experimental and simulation results, it has been probed that proper density of decoupling capacitor on a chip has been well estimated.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124872275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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