With increasing parameter variations in nanoscale technologies, computational blocks in Digital Signal Processing (DSP) hardware become increasingly vulnerable to variation-induced delay failures. These failures can significantly affect the Quality of Service (QoS) for a DSP chip leading to degradation in parametric yield. Existing post-silicon calibration and repair approaches, which rely on adaptation of circuit operating parameters such as voltage, frequency or body bias, typically incur large delay or power overhead in order to maintain QoS. In this paper, we present a novel low overhead approach of healing DSP chips by commensurately truncating the operand width based on its process corner. The proposed approach exploits the fact that critical timing paths in DSP data paths typically originate from the least significant bits (LSBs). This condition can also be satisfied by skewing the path delay distribution during logic synthesis or gate sizing. Hence, truncation of the LSBs, realized by setting them at constant values, can effectively reduce the delay of a unit, thereby avoiding delay failures. We also note that truncation of LSBs typically has minimal impact on QoS. Besides, efficient choice of truncation bits and values can minimize the impact on QoS. We propose appropriate design time modifications including insertion of low-overhead truncation circuit and gate sizing to maximize the delay improvement with truncation. Simulation results for a Discrete Cosine Transform (DCT) application at 45nm technology show large improvement in yield (41.6%) with up to 5X savings in power compared to existing healing approaches.
{"title":"VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width","authors":"Keerthi Kunaparaju, S. Narasimhan, S. Bhunia","doi":"10.1109/VLSID.2011.58","DOIUrl":"https://doi.org/10.1109/VLSID.2011.58","url":null,"abstract":"With increasing parameter variations in nanoscale technologies, computational blocks in Digital Signal Processing (DSP) hardware become increasingly vulnerable to variation-induced delay failures. These failures can significantly affect the Quality of Service (QoS) for a DSP chip leading to degradation in parametric yield. Existing post-silicon calibration and repair approaches, which rely on adaptation of circuit operating parameters such as voltage, frequency or body bias, typically incur large delay or power overhead in order to maintain QoS. In this paper, we present a novel low overhead approach of healing DSP chips by commensurately truncating the operand width based on its process corner. The proposed approach exploits the fact that critical timing paths in DSP data paths typically originate from the least significant bits (LSBs). This condition can also be satisfied by skewing the path delay distribution during logic synthesis or gate sizing. Hence, truncation of the LSBs, realized by setting them at constant values, can effectively reduce the delay of a unit, thereby avoiding delay failures. We also note that truncation of LSBs typically has minimal impact on QoS. Besides, efficient choice of truncation bits and values can minimize the impact on QoS. We propose appropriate design time modifications including insertion of low-overhead truncation circuit and gate sizing to maximize the delay improvement with truncation. Simulation results for a Discrete Cosine Transform (DCT) application at 45nm technology show large improvement in yield (41.6%) with up to 5X savings in power compared to existing healing approaches.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124032489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Computer architects aim to make embedded systems more powerful and space efficient. Code compression is traditionally used to reduce the code size by compressing the instructions with higher static frequency. However, it may introduce decompression overhead. Performance-aware compression techniques try to improve performance through reduction of cache misses by utilizing the dynamic instruction frequency, but it sacrifices code size. We propose a dual compression scheme that aims to simultaneously optimize both code size reduction and performance improvement. Experimental results show that our approach can simultaneously achieve best of both scenarios - achieves up to 40% compression efficiency and an average performance improvement of 50%.
{"title":"Dual Code Compression for Embedded Systems","authors":"K. Shrivastava, P. Mishra","doi":"10.1109/VLSID.2011.13","DOIUrl":"https://doi.org/10.1109/VLSID.2011.13","url":null,"abstract":"Computer architects aim to make embedded systems more powerful and space efficient. Code compression is traditionally used to reduce the code size by compressing the instructions with higher static frequency. However, it may introduce decompression overhead. Performance-aware compression techniques try to improve performance through reduction of cache misses by utilizing the dynamic instruction frequency, but it sacrifices code size. We propose a dual compression scheme that aims to simultaneously optimize both code size reduction and performance improvement. Experimental results show that our approach can simultaneously achieve best of both scenarios - achieves up to 40% compression efficiency and an average performance improvement of 50%.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128988280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 building block. Our inaccurate multipliers achieve an average power saving of 31.78% ? 45.4% over corresponding accurate multiplier designs, for an average error of 1.39%?3.32%. Using image filtering and JPEG compression as sample applications we show that our architecture can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods. We project the multiplier power savings to bigger designs highlighting the fact that the benefits are strongly design dependent. We compare this circuit-centric approach to power quality tradeoffs with a pure software adaptation approach for a JPEG example. We also enhance the design to allow for correct operation of the multiplier using a residual adder, for non error resilient applications.
{"title":"Trading Accuracy for Power with an Underdesigned Multiplier Architecture","authors":"Parag Kulkarni, Puneet Gupta, M. Ercegovac","doi":"10.1109/VLSID.2011.51","DOIUrl":"https://doi.org/10.1109/VLSID.2011.51","url":null,"abstract":"We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 building block. Our inaccurate multipliers achieve an average power saving of 31.78% ? 45.4% over corresponding accurate multiplier designs, for an average error of 1.39%?3.32%. Using image filtering and JPEG compression as sample applications we show that our architecture can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods. We project the multiplier power savings to bigger designs highlighting the fact that the benefits are strongly design dependent. We compare this circuit-centric approach to power quality tradeoffs with a pure software adaptation approach for a JPEG example. We also enhance the design to allow for correct operation of the multiplier using a residual adder, for non error resilient applications.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126800456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Muhammad Adeel Tajammul, M. A. Shami, A. Hemani, S. Moorthi
This paper presents a Network-on-Chip based distributed partitionable memory system for a Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to extend the Register File (RFile) interface with additional data handling capability. The proposed interconnect which enables the interaction between existing partition of computation fabric and the distributed memory system is programmable and partitionable. The system can modify its memory to computation element ratio at runtime. The interconnect can provide multiple interfaces that can support upto 8 GB/s per interface.
{"title":"NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture","authors":"Muhammad Adeel Tajammul, M. A. Shami, A. Hemani, S. Moorthi","doi":"10.1109/VLSID.2011.45","DOIUrl":"https://doi.org/10.1109/VLSID.2011.45","url":null,"abstract":"This paper presents a Network-on-Chip based distributed partitionable memory system for a Dynamic Reconfigurable Resource Array (DRRA). The main purpose of this design is to extend the Register File (RFile) interface with additional data handling capability. The proposed interconnect which enables the interaction between existing partition of computation fabric and the distributed memory system is programmable and partitionable. The system can modify its memory to computation element ratio at runtime. The interconnect can provide multiple interfaces that can support upto 8 GB/s per interface.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124468446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.
{"title":"A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS Technology","authors":"V. Chaturvedi, B. Amrutur","doi":"10.1109/VLSID.2011.41","DOIUrl":"https://doi.org/10.1109/VLSID.2011.41","url":null,"abstract":"Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"80 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131626238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Physical Unclonable Functions (PUFs) are on-chip identifiers which have found many applications related to security. However, such devices suffer from instability due to time varying noise. Variation in operating temperature is a chief contributor to instability in PUFs. In this paper, we propose two different approaches to increase the stability of the popular ring oscillator PUFs against variations in temperature. The first approach involves using non-feedback based optimization of key circuit topologies including the drive strength of transistors and the stage length of the ring oscillators. However, to improve the stability even further, we propose a feedback based supply voltage control scheme. In this scheme, the supply voltage of the PUF is varied based on the operating temperature of the PUF IC. The optimal supply voltage to be applied to the PUF at each of the operating temperature is identified during the evaluation stage of the PUFs and is stored in the form of a micro-code. Also, a novel architecture supporting this scheme is proposed. Experimental results show that a 40% reduction in hardware is achieved by using this novel architecture.
{"title":"Feedback Based Supply Voltage Control for Temperature Variation Tolerant PUFs","authors":"Vignesh Vivekraja, L. Nazhandali","doi":"10.1109/VLSID.2011.60","DOIUrl":"https://doi.org/10.1109/VLSID.2011.60","url":null,"abstract":"Physical Unclonable Functions (PUFs) are on-chip identifiers which have found many applications related to security. However, such devices suffer from instability due to time varying noise. Variation in operating temperature is a chief contributor to instability in PUFs. In this paper, we propose two different approaches to increase the stability of the popular ring oscillator PUFs against variations in temperature. The first approach involves using non-feedback based optimization of key circuit topologies including the drive strength of transistors and the stage length of the ring oscillators. However, to improve the stability even further, we propose a feedback based supply voltage control scheme. In this scheme, the supply voltage of the PUF is varied based on the operating temperature of the PUF IC. The optimal supply voltage to be applied to the PUF at each of the operating temperature is identified during the evaluation stage of the PUFs and is stored in the form of a micro-code. Also, a novel architecture supporting this scheme is proposed. Experimental results show that a 40% reduction in hardware is achieved by using this novel architecture.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114980576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Ganta, Vignesh Vivekraja, K. Priya, L. Nazhandali
In this paper, we propose a new silicon PUF using efficient analog components that can be fabricated on a standard CMOS process. Our proposed design is built using leakage sensors with each measuring the leakage current of a transistor. Multiple identical leakage sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different leakage values that can be compared in order to create a digital identification (ID) for the chip. Our results show that the proposed PUF is able to effectively identify a population of ICs. We also study the stability of our design with respect to temporary environmental variations like temperature and supply voltage. Our results show that nearly ideal stability can be achieved with minimal area overhead in our design. Comparing with a popular ring oscillator PUF architecture of the same entropy, our proposed PUF consumes about 80% less power, occupies about 85% less area, and has a high level of stability across a wide range of temperatures.
{"title":"A Highly Stable Leakage-Based Silicon Physical Unclonable Functions","authors":"D. Ganta, Vignesh Vivekraja, K. Priya, L. Nazhandali","doi":"10.1109/VLSID.2011.72","DOIUrl":"https://doi.org/10.1109/VLSID.2011.72","url":null,"abstract":"In this paper, we propose a new silicon PUF using efficient analog components that can be fabricated on a standard CMOS process. Our proposed design is built using leakage sensors with each measuring the leakage current of a transistor. Multiple identical leakage sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different leakage values that can be compared in order to create a digital identification (ID) for the chip. Our results show that the proposed PUF is able to effectively identify a population of ICs. We also study the stability of our design with respect to temporary environmental variations like temperature and supply voltage. Our results show that nearly ideal stability can be achieved with minimal area overhead in our design. Comparing with a popular ring oscillator PUF architecture of the same entropy, our proposed PUF consumes about 80% less power, occupies about 85% less area, and has a high level of stability across a wide range of temperatures.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129864485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With scaling of technology and increasing design sizes, thermal issues are emerging to be one of the major concerns for modern Very-Large-Scale Integration (VLSI) testing due to both increasing power densities and higher reliability requirements. However, in all existing thermal-aware test scheduling research, test schedule is computed a priori as a static schedule using an estimate of the power consumed by each test. Due to the popular peak power model and increasing process variations, estimated test power values can be far from the actual power consumption. Consequently, the thermal profile of the chip estimated during off-line scheduling can be substantially different from that during actual testing. In this paper, we propose a dynamic thermal-aware test scheduling method using on-chip temperature sensors. We first define a test architecture that supports dynamic test scheduling and then develop a scheduling algorithm. Next, we perform simulation studies on ITC’02 benchmarks. Our simulation results show that the performance of the thermal aware test scheduling can be substantially improved with the help of on-chip temperature sensors, especially for chips with many cores.
{"title":"Thermal-Aware Test Scheduling Using On-chip Temperature Sensors","authors":"Chunhua Yao, K. Saluja, P. Ramanathan","doi":"10.1109/VLSID.2011.22","DOIUrl":"https://doi.org/10.1109/VLSID.2011.22","url":null,"abstract":"With scaling of technology and increasing design sizes, thermal issues are emerging to be one of the major concerns for modern Very-Large-Scale Integration (VLSI) testing due to both increasing power densities and higher reliability requirements. However, in all existing thermal-aware test scheduling research, test schedule is computed a priori as a static schedule using an estimate of the power consumed by each test. Due to the popular peak power model and increasing process variations, estimated test power values can be far from the actual power consumption. Consequently, the thermal profile of the chip estimated during off-line scheduling can be substantially different from that during actual testing. In this paper, we propose a dynamic thermal-aware test scheduling method using on-chip temperature sensors. We first define a test architecture that supports dynamic test scheduling and then develop a scheduling algorithm. Next, we perform simulation studies on ITC’02 benchmarks. Our simulation results show that the performance of the thermal aware test scheduling can be substantially improved with the help of on-chip temperature sensors, especially for chips with many cores.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133835333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fully-analog, on-chip, low input offset, low noise, variable gain instrumentation amplifier with a new scheme for nonlinear and dynamic temperature compensation of sensor sensitivity and offset, is designed in 0.18?m commercial CMOS process. The system has a scalable system bandwidth up to 5kHz, a dynamic range of 84dB, and a maximum gain of 104dB. All the sensor non idealities and CMOS process mismatch have been incorporated in simulation. Using this interfacing circuit, a smart MEMS piezoresistive accelerometer has been designed subsequently.
{"title":"Low Offset, Low Noise, Variable Gain Interfacing Circuit with a Novel Scheme for Sensor Sensitivity and Offset Compensation for MEMS Based, Wheatstone Bridge Type, Resistive Smart Sensor","authors":"Anupam Dutta, T. K. Bhattacharyya","doi":"10.1109/VLSID.2011.39","DOIUrl":"https://doi.org/10.1109/VLSID.2011.39","url":null,"abstract":"A fully-analog, on-chip, low input offset, low noise, variable gain instrumentation amplifier with a new scheme for nonlinear and dynamic temperature compensation of sensor sensitivity and offset, is designed in 0.18?m commercial CMOS process. The system has a scalable system bandwidth up to 5kHz, a dynamic range of 84dB, and a maximum gain of 104dB. All the sensor non idealities and CMOS process mismatch have been incorporated in simulation. Using this interfacing circuit, a smart MEMS piezoresistive accelerometer has been designed subsequently.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114836572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, micro fluidic biochips are gaining much attention. Especially microchip-based capillary electrophoresis system is one of the techniques that are developed in the area of separation on a microchip. In this paper, we present an automated physical design methodology for microchip based capillary electrophoresis channel systems. The proposed methodology includes three stages: (1) placement of subsystems, (2) routing of auxiliary channels, and (3) placement of I/O wells. In the first stage, simulated annealing is applied to place the subsystems such that the chip area and the cost of routing the auxiliary channels are minimized. Then the second stage is applied to route the auxiliary channels from the ports of the subsystems to the boundaries of chip. The objective of this stage is to minimize the length and the number of bends of the auxiliary channels. Finally, the third stage places the I/O wells on the boundaries. The experimental results show that the proposed methodology can achieve better results of chip area as well as the total length and number of bends of auxiliary channels.
{"title":"Automated Physical Design of Microchip-Based Capillary Electrophoresis Systems","authors":"Yi-Ling Hsieh, Tsung-Yi Ho","doi":"10.1109/VLSID.2011.47","DOIUrl":"https://doi.org/10.1109/VLSID.2011.47","url":null,"abstract":"Recently, micro fluidic biochips are gaining much attention. Especially microchip-based capillary electrophoresis system is one of the techniques that are developed in the area of separation on a microchip. In this paper, we present an automated physical design methodology for microchip based capillary electrophoresis channel systems. The proposed methodology includes three stages: (1) placement of subsystems, (2) routing of auxiliary channels, and (3) placement of I/O wells. In the first stage, simulated annealing is applied to place the subsystems such that the chip area and the cost of routing the auxiliary channels are minimized. Then the second stage is applied to route the auxiliary channels from the ports of the subsystems to the boundaries of chip. The objective of this stage is to minimize the length and the number of bends of the auxiliary channels. Finally, the third stage places the I/O wells on the boundaries. The experimental results show that the proposed methodology can achieve better results of chip area as well as the total length and number of bends of auxiliary channels.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116707131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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