Continuous shrinking in feature size, increasing power density etc. increase the vulnerability of microprocessors against soft errors even in terrestrial applications. The register file is one of the essential architectural components where soft errors can be very mischievous because errors may rapidly spread from there throughout the whole system. Thus, register files are recognized as one of the major concerns when it comes to reliability. This paper introduces Self-Immunity, a technique that improves the integrity of the register file with respect to soft errors. Based on the observation that a certain number of register bits are not always used to represent a value stored in a register. This paper deals with the difficulty to exploit this obvious observation to enhance the register file integrity against soft errors. We show that our technique can reduce the vulnerability of the register file considerably while exhibiting smaller overhead in terms of area and power consumption compared to state-of-the-art in register file protection.
{"title":"Self-Immunity Technique to Improve Register File Integrity Against Soft Errors","authors":"H. Amrouch, J. Henkel","doi":"10.1109/VLSID.2011.68","DOIUrl":"https://doi.org/10.1109/VLSID.2011.68","url":null,"abstract":"Continuous shrinking in feature size, increasing power density etc. increase the vulnerability of microprocessors against soft errors even in terrestrial applications. The register file is one of the essential architectural components where soft errors can be very mischievous because errors may rapidly spread from there throughout the whole system. Thus, register files are recognized as one of the major concerns when it comes to reliability. This paper introduces Self-Immunity, a technique that improves the integrity of the register file with respect to soft errors. Based on the observation that a certain number of register bits are not always used to represent a value stored in a register. This paper deals with the difficulty to exploit this obvious observation to enhance the register file integrity against soft errors. We show that our technique can reduce the vulnerability of the register file considerably while exhibiting smaller overhead in terms of area and power consumption compared to state-of-the-art in register file protection.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122518870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sudip Roy, B. B. Bhattacharya, P. Chakrabarti, K. Chakrabarty
A biochemical analysis is based on several laboratory protocols that require repeated mixing of samples with reagents. Sample preparation and analyte identification steps in such bioassays often involve mixing for solution preparation, i.e., various fluids are to be mixed in a certain volumetric ratio in their resulting mixture. We present an efficient approach for automated mixing of three or more fluids on a droplet based digital micro fluidic biochip and design a layout for implementing this algorithm. The proposed method reduces the droplet transportation time from boundary reservoirs to on chip mixers as well as cross-contamination among overlapping droplet routing paths. Simulation of several example solutions reveals encouraging results.
{"title":"Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip","authors":"Sudip Roy, B. B. Bhattacharya, P. Chakrabarti, K. Chakrabarty","doi":"10.1109/VLSID.2011.55","DOIUrl":"https://doi.org/10.1109/VLSID.2011.55","url":null,"abstract":"A biochemical analysis is based on several laboratory protocols that require repeated mixing of samples with reagents. Sample preparation and analyte identification steps in such bioassays often involve mixing for solution preparation, i.e., various fluids are to be mixed in a certain volumetric ratio in their resulting mixture. We present an efficient approach for automated mixing of three or more fluids on a droplet based digital micro fluidic biochip and design a layout for implementing this algorithm. The proposed method reduces the droplet transportation time from boundary reservoirs to on chip mixers as well as cross-contamination among overlapping droplet routing paths. Simulation of several example solutions reveals encouraging results.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131800171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates sub threshold voltage operation of digital circuits. The minimum energy per cycle operating point with a single voltage for this mode is known. We further lower the energy per cycle below that point by using dual sub threshold supplies. We call this the true minimum. Special considerations are used in the design for eliminating level converters. We give new mixed integer linear programs (MILP) that automatically and optimally assign gate voltages, avoid the use of level converters, and determine and hold the minimum critical path delay, while minimizing the total energy per cycle. Using examples of a 16-bit ripple-carry adder and a 4 × 4 multiplier we show energy savings of 23% and 5%, respectively. The latter is a worst case example because most paths are critical. Alternatively, for the same energy as that of single below-threshold supply, an optimized dual voltage design can operate at 3 to 4 times higher clock rate. The MILP optimization with special consideration for level converters is general and applicable to any supply voltage range.
{"title":"True Minimum Energy Design Using Dual Below-Threshold Supply Voltages","authors":"Kyung Ki Kim, V. Agrawal","doi":"10.1109/VLSID.2011.67","DOIUrl":"https://doi.org/10.1109/VLSID.2011.67","url":null,"abstract":"This paper investigates sub threshold voltage operation of digital circuits. The minimum energy per cycle operating point with a single voltage for this mode is known. We further lower the energy per cycle below that point by using dual sub threshold supplies. We call this the true minimum. Special considerations are used in the design for eliminating level converters. We give new mixed integer linear programs (MILP) that automatically and optimally assign gate voltages, avoid the use of level converters, and determine and hold the minimum critical path delay, while minimizing the total energy per cycle. Using examples of a 16-bit ripple-carry adder and a 4 × 4 multiplier we show energy savings of 23% and 5%, respectively. The latter is a worst case example because most paths are critical. Alternatively, for the same energy as that of single below-threshold supply, an optimized dual voltage design can operate at 3 to 4 times higher clock rate. The MILP optimization with special consideration for level converters is general and applicable to any supply voltage range.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116749682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As research on developing assertion languages for the AMS domain gains in momentum, it is increasingly being felt that extensions of existing assertion languages like PSL and SVA into the AMS domain are not adequate for expressing the analog design intent. This is largely due to the intricacy of the analog behavioral intent which cannot be captured purely in terms of logic. In this paper we show that by using auxiliary forms of formal specifications such as abstract state machines and real valued functions as references for AMS assertions, it becomes possible to model complex AMS behavioral properties. This approach leverages the growing adoption of AMS behavioral modeling in the industry. The paper also shows that the use of auxiliary state machines allows us to separate out the scope of different analog assertions leading to significant performance gains in the assertion checking overhead.
{"title":"Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions","authors":"Subhankar Mukherjee, P. Dasgupta","doi":"10.1109/VLSID.2011.27","DOIUrl":"https://doi.org/10.1109/VLSID.2011.27","url":null,"abstract":"As research on developing assertion languages for the AMS domain gains in momentum, it is increasingly being felt that extensions of existing assertion languages like PSL and SVA into the AMS domain are not adequate for expressing the analog design intent. This is largely due to the intricacy of the analog behavioral intent which cannot be captured purely in terms of logic. In this paper we show that by using auxiliary forms of formal specifications such as abstract state machines and real valued functions as references for AMS assertions, it becomes possible to model complex AMS behavioral properties. This approach leverages the growing adoption of AMS behavioral modeling in the industry. The paper also shows that the use of auxiliary state machines allows us to separate out the scope of different analog assertions leading to significant performance gains in the assertion checking overhead.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sreekanth Soman, A. Brahme, R. Venkatraman, Raashid Shaikh, Santhosh Thiyagaraja, Mahendrasing Patil
VLSI designs in advanced technology nodes increasingly have more power dissipation packed in a smaller area due to high levels of logic integration. Local power demand causes high current to flow through a power distribution network which is normally designed based on average current considerations, while even in normal switching scenarios, the average current is much less than the peak current. The instantaneous flow of high current results in dynamic voltage drops in the power network, which can affect the design performance. In this paper, we discuss methods to ensure power grid robustness by avoiding high dynamic voltage drop issues, and hence improve the overall reliability of the design. The analyses and techniques were adopted on a ~100 sq.mm., 40nm system-on-chip (SoC) design with peak clock frequency of 1.2GHz, and having 10 individual processors along with a collection of hardware accelerators. We also present relevant results highlighting the overall improvements seen.
{"title":"Ensuring On-Die Power Supply Robustness in High-Performance Designs","authors":"Sreekanth Soman, A. Brahme, R. Venkatraman, Raashid Shaikh, Santhosh Thiyagaraja, Mahendrasing Patil","doi":"10.1109/VLSID.2011.62","DOIUrl":"https://doi.org/10.1109/VLSID.2011.62","url":null,"abstract":"VLSI designs in advanced technology nodes increasingly have more power dissipation packed in a smaller area due to high levels of logic integration. Local power demand causes high current to flow through a power distribution network which is normally designed based on average current considerations, while even in normal switching scenarios, the average current is much less than the peak current. The instantaneous flow of high current results in dynamic voltage drops in the power network, which can affect the design performance. In this paper, we discuss methods to ensure power grid robustness by avoiding high dynamic voltage drop issues, and hence improve the overall reliability of the design. The analyses and techniques were adopted on a ~100 sq.mm., 40nm system-on-chip (SoC) design with peak clock frequency of 1.2GHz, and having 10 individual processors along with a collection of hardware accelerators. We also present relevant results highlighting the overall improvements seen.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a novel methodology to automate the transistor-level sizing of OpAmps. Given the net list and the specifications of the OpAmp, our methodology automatically produces a set of monomial design equations that can be solved using a geometric programming. The use of monomial models eliminates the overhead of generating elaborate posynomial design equations. The proposed approach is based on the use of circuit heuristics to generate a first order design model, which is then refined by adopting a localized simulation scheme. This approach produces a design that has the accuracy of the BSIM models used for simulation and the advantage of a quick design time. The results of a two stage OpAmp and a Telescopic OpAmp designed in TSMC 0.25? technology prove the efficacy of our approach.
{"title":"A Methodology for Automatic Transistor-Level Sizing of CMOS OpAmps","authors":"Praveen K. Meduri, S. Dhali","doi":"10.1109/VLSID.2011.53","DOIUrl":"https://doi.org/10.1109/VLSID.2011.53","url":null,"abstract":"In this paper, we propose a novel methodology to automate the transistor-level sizing of OpAmps. Given the net list and the specifications of the OpAmp, our methodology automatically produces a set of monomial design equations that can be solved using a geometric programming. The use of monomial models eliminates the overhead of generating elaborate posynomial design equations. The proposed approach is based on the use of circuit heuristics to generate a first order design model, which is then refined by adopting a localized simulation scheme. This approach produces a design that has the accuracy of the BSIM models used for simulation and the advantage of a quick design time. The results of a two stage OpAmp and a Telescopic OpAmp designed in TSMC 0.25? technology prove the efficacy of our approach.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 4-lane, 2Gbps-per-lane, source synchronous, voltage-mode differential transmitter is presented here. Staggered switching of driver termination is used to obtain controlled, nearlinear rise/fall transitions on the pads. The timing for the staggering is generated by a calibrated digitally controlled delay line. An on-chip high bandwidth regulator serves as a low impedance 400mV source required for voltage mode transmission. The transmitter, designed and fabricated in 45nm CMOS technology, occupies a core area of 0.013mm2 per lane and consumes 4.3mW/Gbps.
{"title":"4×2Gbps Source-Synchronous Transmitter in 45nm CMOS","authors":"Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty","doi":"10.1109/VLSID.2011.33","DOIUrl":"https://doi.org/10.1109/VLSID.2011.33","url":null,"abstract":"A 4-lane, 2Gbps-per-lane, source synchronous, voltage-mode differential transmitter is presented here. Staggered switching of driver termination is used to obtain controlled, nearlinear rise/fall transitions on the pads. The timing for the staggering is generated by a calibrated digitally controlled delay line. An on-chip high bandwidth regulator serves as a low impedance 400mV source required for voltage mode transmission. The transmitter, designed and fabricated in 45nm CMOS technology, occupies a core area of 0.013mm2 per lane and consumes 4.3mW/Gbps.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129923437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
System optimization techniques based on dynamic reconfiguration are widely adopted for energy conservation. While dynamic voltage scaling (DVS) techniques have been extensively studied for processor energy conservation, dynamic cache reconfiguration (DCR) for reducing cache energy consumption in multitasking systems is still in its infancy. In this paper, we propose a general and flexible algorithm for energy optimization based on dynamic reconfiguration in multitasking systems. Our algorithm is flexibly parameterized and can be used to provide tradeoffs between running time and solution quality. Furthermore, it can easily incorporate variable reconfiguration overhead. Experimental results show that our technique can generate near-optimal solutions with significantly low running time and memory requirements.
{"title":"A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems","authors":"Weixun Wang, S. Ranka, P. Mishra","doi":"10.1109/VLSID.2011.17","DOIUrl":"https://doi.org/10.1109/VLSID.2011.17","url":null,"abstract":"System optimization techniques based on dynamic reconfiguration are widely adopted for energy conservation. While dynamic voltage scaling (DVS) techniques have been extensively studied for processor energy conservation, dynamic cache reconfiguration (DCR) for reducing cache energy consumption in multitasking systems is still in its infancy. In this paper, we propose a general and flexible algorithm for energy optimization based on dynamic reconfiguration in multitasking systems. Our algorithm is flexibly parameterized and can be used to provide tradeoffs between running time and solution quality. Furthermore, it can easily incorporate variable reconfiguration overhead. Experimental results show that our technique can generate near-optimal solutions with significantly low running time and memory requirements.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129934023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design and implementation of a 20 MHz voltage mode DC-DC buck converter with high power efficiency. The power efficiency has been improved by minimising the short circuit current in the driver stage. At the same time, a high gain, wide-band error amplifier topology with reduced current consumption, improves various dynamic performance parameters such as settling time, load and line regulations of the converter. A prototype of a 20 MHz DCDC buck converter is implemented and fabricated in 0.5 ?m Bi-CMOS process with a maximum of 600 mA load current driving capability in the input voltage range of 2.7-5.5 V which is suitable for single-cell lithiumion (Li-Ion) battery operated portable applications. A reasonably good settling time of 10 ?s is observed in the measured result with off-chip filter components of L=270 nH, C=1.6 ?F. The measured value of load regulation and line regulation are 1.6 mV/A and 3 mV/V respectively. A maximum of 84% power efficiency is achieved at 2.7 V to 1.2 V conversion. A very low form factor of 2.5 mm× 2.5 mm× 0.7 mm, has been achieved by using power power flip-chip packaging technology.
{"title":"Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications","authors":"A. Maity, A. Patra, N. Yamamura, J. Knight","doi":"10.1109/VLSID.2011.37","DOIUrl":"https://doi.org/10.1109/VLSID.2011.37","url":null,"abstract":"This paper presents the design and implementation of a 20 MHz voltage mode DC-DC buck converter with high power efficiency. The power efficiency has been improved by minimising the short circuit current in the driver stage. At the same time, a high gain, wide-band error amplifier topology with reduced current consumption, improves various dynamic performance parameters such as settling time, load and line regulations of the converter. A prototype of a 20 MHz DCDC buck converter is implemented and fabricated in 0.5 ?m Bi-CMOS process with a maximum of 600 mA load current driving capability in the input voltage range of 2.7-5.5 V which is suitable for single-cell lithiumion (Li-Ion) battery operated portable applications. A reasonably good settling time of 10 ?s is observed in the measured result with off-chip filter components of L=270 nH, C=1.6 ?F. The measured value of load regulation and line regulation are 1.6 mV/A and 3 mV/V respectively. A maximum of 84% power efficiency is achieved at 2.7 V to 1.2 V conversion. A very low form factor of 2.5 mm× 2.5 mm× 0.7 mm, has been achieved by using power power flip-chip packaging technology.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128462099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For optimal operation, the Clock and Data Recovery (CDR) circuit requires perfect quadrature between In-phase and Quadrature phase clocks. These clocks are used to sample the Data and the Edge information so as to enable the CDR to align the Receiver clock to the centre of Data eye. Any error in quadrature between the two clocks results in higher CDR jitter. Quadrature error mainly comes from the clock-path mismatch and also from mismatch between the In-phase and Quadrature-phase interpolators. A novel Quadrature Error Compensation (Calibration) mechanism to overcome the quadrature error is implemented and discussed in this paper. An improvement of 30% in the CDR jitter was obtained with the proposed mechanism for a 5 Gbps (PCIe Gen2) link implemented in a 45nm process.
{"title":"Quadrature Error Compensation for Jitter Reduction in High Speed Clock and Data Recovery Circuits","authors":"K. Desai, V. Krishna","doi":"10.1109/VLSID.2011.30","DOIUrl":"https://doi.org/10.1109/VLSID.2011.30","url":null,"abstract":"For optimal operation, the Clock and Data Recovery (CDR) circuit requires perfect quadrature between In-phase and Quadrature phase clocks. These clocks are used to sample the Data and the Edge information so as to enable the CDR to align the Receiver clock to the centre of Data eye. Any error in quadrature between the two clocks results in higher CDR jitter. Quadrature error mainly comes from the clock-path mismatch and also from mismatch between the In-phase and Quadrature-phase interpolators. A novel Quadrature Error Compensation (Calibration) mechanism to overcome the quadrature error is implemented and discussed in this paper. An improvement of 30% in the CDR jitter was obtained with the proposed mechanism for a 5 Gbps (PCIe Gen2) link implemented in a 45nm process.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131827225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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