Fault Collapsing of a target fault-list can help in obtaining a compact test set, decreasing test-generation/fault simulation time, and indirectly reducing test data volume and test application time during Manufacturing Test. These factors have a direct impact on test economics, thus obtaining a compact fault list is essential. In this paper, we propose a novel extensibility relation that aids in identifying non-trivial dominance relationships among fault-pairs. We show that our technique supersedes existing dominance-based collapsing techniques and thus may identify more dominance relations among faults. To this end, we learn several necessary assignments for faults in a low-cost fault independent manner, in which memory requirements are also low. Further, from a theoretical point of interest, we theorize a lower bound on the size of a collapsed fault-list. Experimental results on ISCAS85 and full-scan versions of ISCAS89 circuits indicate that, on an average, our technique can eliminate 5% of faults from the collapsed fault list reported by the best known fault collapsing engine. Further, our technique consumed only 2% -4% of the memory used by the best known engine, which also provided for a 2:3x average speed-up!
{"title":"Fault Collapsing Using a Novel Extensibility Relation","authors":"M. Chandrasekar, M. Hsiao","doi":"10.1109/VLSID.2011.56","DOIUrl":"https://doi.org/10.1109/VLSID.2011.56","url":null,"abstract":"Fault Collapsing of a target fault-list can help in obtaining a compact test set, decreasing test-generation/fault simulation time, and indirectly reducing test data volume and test application time during Manufacturing Test. These factors have a direct impact on test economics, thus obtaining a compact fault list is essential. In this paper, we propose a novel extensibility relation that aids in identifying non-trivial dominance relationships among fault-pairs. We show that our technique supersedes existing dominance-based collapsing techniques and thus may identify more dominance relations among faults. To this end, we learn several necessary assignments for faults in a low-cost fault independent manner, in which memory requirements are also low. Further, from a theoretical point of interest, we theorize a lower bound on the size of a collapsed fault-list. Experimental results on ISCAS85 and full-scan versions of ISCAS89 circuits indicate that, on an average, our technique can eliminate 5% of faults from the collapsed fault list reported by the best known fault collapsing engine. Further, our technique consumed only 2% -4% of the memory used by the best known engine, which also provided for a 2:3x average speed-up!","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131127676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A conventional duo binary transmitter needs a clock frequency equal to transmission data rate and for high speed data transmission the clock frequency defines the transmission limit. In this work we propose a double data rate duo binary transmitter architecture. It uses a clock frequency half of the output data transmission rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duo binary transmitter. In this architecture, duo binary precoder is integrated into the last stage of a tree structured serializer to combine two high speed NRZ data streams at half the output data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper back plane where the channel transfer characteristic is exploited to provide the duo binary spectral shaping and the transmitter performs duo binary precoding. In the second mode, filtering operation follows duo binary precoding at the transmitter and hence is applicable for optical transmission where the high bandwidth channel can not provide the required spectral shaping. A delay locked loop(DLL) based clock multiply unit(CMU) is employed to generate a high frequency, low jitter clock with 50% duty cycle needed for the realization of the proposed transmitter architecture. The design is implemented in 1.8-V, 0.18-?m Digital CMOS technology. The duo binary transmitter circuit works up-to 10-Gb/s speed and consumes 20-mW power.
{"title":"A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture","authors":"M. Sharad, V. Pasupureddi, P. Mandal","doi":"10.1109/VLSID.2011.52","DOIUrl":"https://doi.org/10.1109/VLSID.2011.52","url":null,"abstract":"A conventional duo binary transmitter needs a clock frequency equal to transmission data rate and for high speed data transmission the clock frequency defines the transmission limit. In this work we propose a double data rate duo binary transmitter architecture. It uses a clock frequency half of the output data transmission rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duo binary transmitter. In this architecture, duo binary precoder is integrated into the last stage of a tree structured serializer to combine two high speed NRZ data streams at half the output data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper back plane where the channel transfer characteristic is exploited to provide the duo binary spectral shaping and the transmitter performs duo binary precoding. In the second mode, filtering operation follows duo binary precoding at the transmitter and hence is applicable for optical transmission where the high bandwidth channel can not provide the required spectral shaping. A delay locked loop(DLL) based clock multiply unit(CMU) is employed to generate a high frequency, low jitter clock with 50% duty cycle needed for the realization of the proposed transmitter architecture. The design is implemented in 1.8-V, 0.18-?m Digital CMOS technology. The duo binary transmitter circuit works up-to 10-Gb/s speed and consumes 20-mW power.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126185887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Subhadip Kundu, S. Chattopadhyay, I. Sengupta, R. Kapur
Fault diagnosis is extremely important to ramp up the manufacturing yield and in some cases to reduce the product debug time as well. In this paper, we have proposed a novel technique to analyze multiple fault diagnosis based on multiple fault injection. Almost all the conventional fault diagnosis method simulate one fault (among the candidate faults) at a time and based on the number of failed patterns the fault can explain, a ranking is proposed for all candidate faults. But, a single fault injection cannot manifest the effect of multiple faults that are present in the actual failed circuit. Thus, in this paper, we have injected multiple faults simultaneously, and perform an effect-cause analysis to find the possible list of faults. Experimental results prove the validation of our approach as it has high diagnosability and resolution. The proposed method runs within moderate CPU time. We have been able to run simulations to diagnose upto 10 faults in a reasonable time. However, the scheme does not put any restrictions on the number of simultaneous faults.
{"title":"Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization","authors":"Subhadip Kundu, S. Chattopadhyay, I. Sengupta, R. Kapur","doi":"10.1109/VLSID.2011.34","DOIUrl":"https://doi.org/10.1109/VLSID.2011.34","url":null,"abstract":"Fault diagnosis is extremely important to ramp up the manufacturing yield and in some cases to reduce the product debug time as well. In this paper, we have proposed a novel technique to analyze multiple fault diagnosis based on multiple fault injection. Almost all the conventional fault diagnosis method simulate one fault (among the candidate faults) at a time and based on the number of failed patterns the fault can explain, a ranking is proposed for all candidate faults. But, a single fault injection cannot manifest the effect of multiple faults that are present in the actual failed circuit. Thus, in this paper, we have injected multiple faults simultaneously, and perform an effect-cause analysis to find the possible list of faults. Experimental results prove the validation of our approach as it has high diagnosability and resolution. The proposed method runs within moderate CPU time. We have been able to run simulations to diagnose upto 10 faults in a reasonable time. However, the scheme does not put any restrictions on the number of simultaneous faults.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114593644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, fabrication and characterization of semi conducting nanotube thin-film transistors (SN-TFTs) using 90% and 95% purity semi conducting single walled carbon nanotubes (SWCNTs) are presented. The wafer scale fabrication of SN-TFTs are carried out on 2 inch Si wafers. Pre-separated semi conducting SWCNTs are deposited on amino-silane treated Si/SiO2 surface. A simple method is suggested for silanization in order to improve the carbon nanotube density more than 30 nanotubes/¹m2. SN-TFTs fabricated using both 90% and 95% enriched semi conducting SWCNTs have exhibited p-type output characteristic with excellent linear and saturation region of operation along with high on-off current ratio and steep sub threshold slope.
{"title":"Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes","authors":"K. C. Narasimhamurthy, R. Paily","doi":"10.1109/VLSID.2011.59","DOIUrl":"https://doi.org/10.1109/VLSID.2011.59","url":null,"abstract":"In this paper, fabrication and characterization of semi conducting nanotube thin-film transistors (SN-TFTs) using 90% and 95% purity semi conducting single walled carbon nanotubes (SWCNTs) are presented. The wafer scale fabrication of SN-TFTs are carried out on 2 inch Si wafers. Pre-separated semi conducting SWCNTs are deposited on amino-silane treated Si/SiO2 surface. A simple method is suggested for silanization in order to improve the carbon nanotube density more than 30 nanotubes/¹m2. SN-TFTs fabricated using both 90% and 95% enriched semi conducting SWCNTs have exhibited p-type output characteristic with excellent linear and saturation region of operation along with high on-off current ratio and steep sub threshold slope.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133943113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a Silicon-on-Insulator based circuit for use as configuration storage in a radiation hard reconfigurable system. A non-volatile storage cell, manufacturable in a standar single polysilicon SOI CMOS process with no special layers, is combined with a Schmitt sense amplifier such that the overall block exhibits two unique characteristics that enhance its resistance to radiation induced upsets. Firstly, it is impossible for a radiation-induced event to permanently flip the configuration state. Secondly, a partial de-programming resulting in a reduction in the magnitude of the storage cell voltage causes a large change in static current that can be very easily detected using a conventional sense amplifier. A memory correction (scrubbing) system that exploits this behavior is briefly described.
{"title":"A SOI EEPROM Based Configuration Cell with Simple Scrubbing Detection","authors":"Kashfia Haque, P. Beckett","doi":"10.1109/VLSID.2011.50","DOIUrl":"https://doi.org/10.1109/VLSID.2011.50","url":null,"abstract":"We present a Silicon-on-Insulator based circuit for use as configuration storage in a radiation hard reconfigurable system. A non-volatile storage cell, manufacturable in a standar single polysilicon SOI CMOS process with no special layers, is combined with a Schmitt sense amplifier such that the overall block exhibits two unique characteristics that enhance its resistance to radiation induced upsets. Firstly, it is impossible for a radiation-induced event to permanently flip the configuration state. Secondly, a partial de-programming resulting in a reduction in the magnitude of the storage cell voltage causes a large change in static current that can be very easily detected using a conventional sense amplifier. A memory correction (scrubbing) system that exploits this behavior is briefly described.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121352658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work we propose an improved and efficient method for static estimation of average and root-mean-square currents used for electro migration (EM) reliability analysis. Significantly different from the state-of-the-art, the proposed method gives closed-form expressions for average and root mean-square currents in one complete cycle. The method, additionally, handles the asymmetric nature of the rise and fall current waveforms. We further present a detailed comparison of the proposed method with other conventional approaches and outline the inadequacies of using prevalent EM-severity metrics: either the net’s lumped capacitance or the net’s effective capacitance, along with the regular timing slew. As a correction, and, application of proposed method, we provide formulations for deriving the effective ‘EM’ slew, which can be used with conventional static approaches to accurately compute the currents. Additionally, unlike conventional understanding, for the first time, we note that not just the RMS current, but even the total charge transfer, and therefore the average current can also be dependent on the current waveform type and net’s electrical properties. We propose formulations to account for this behavior of average current. Finally, we share model validation results with respect to actual SPICE simulations from heavily loaded and/or high fan-out nets operating at high frequency from a production 40nm design. The method enables still higher performance of a design, which was otherwise optimized for an originally lower frequency target using conventional approaches.
{"title":"Accurate Estimation of Signal Currents for Reliability Analysis Considering Advanced Waveform-Shape Effects","authors":"Palkesh Jain, Ankit Jain","doi":"10.1109/VLSID.2011.61","DOIUrl":"https://doi.org/10.1109/VLSID.2011.61","url":null,"abstract":"In this work we propose an improved and efficient method for static estimation of average and root-mean-square currents used for electro migration (EM) reliability analysis. Significantly different from the state-of-the-art, the proposed method gives closed-form expressions for average and root mean-square currents in one complete cycle. The method, additionally, handles the asymmetric nature of the rise and fall current waveforms. We further present a detailed comparison of the proposed method with other conventional approaches and outline the inadequacies of using prevalent EM-severity metrics: either the net’s lumped capacitance or the net’s effective capacitance, along with the regular timing slew. As a correction, and, application of proposed method, we provide formulations for deriving the effective ‘EM’ slew, which can be used with conventional static approaches to accurately compute the currents. Additionally, unlike conventional understanding, for the first time, we note that not just the RMS current, but even the total charge transfer, and therefore the average current can also be dependent on the current waveform type and net’s electrical properties. We propose formulations to account for this behavior of average current. Finally, we share model validation results with respect to actual SPICE simulations from heavily loaded and/or high fan-out nets operating at high frequency from a production 40nm design. The method enables still higher performance of a design, which was otherwise optimized for an originally lower frequency target using conventional approaches.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116544198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an analytical physics-based model for width dependence of threshold voltage of nano-scale MOSFETs. Shallow trench isolated MOSFETs have been considered in the 90 nm and 65 nm technology nodes. The combined effect of gate fringing field and do pant redistribution has been considered for developing the model. The trench oxide parasitic capacitance is evaluated by conformal mapping technique and is then used to determine the width-dependent threshold voltage shift. The developed model has been validated by comparing the results predicted from the derived model with experimental data, simulation data and also with a similar model available in literature. It has been demonstrated that our model predicts more correctly the inverse narrow width effect on threshold voltage of nano-scale devices compared to the existing model.
{"title":"Modeling the Effect of Gate Fringing and Dopant Redistribution on the Inverse Narrow Width Effect of Narrow Channel Shallow Trench Isolated MOSFETs","authors":"S. Pandit, C. Sarkar","doi":"10.1109/VLSID.2011.16","DOIUrl":"https://doi.org/10.1109/VLSID.2011.16","url":null,"abstract":"This paper presents an analytical physics-based model for width dependence of threshold voltage of nano-scale MOSFETs. Shallow trench isolated MOSFETs have been considered in the 90 nm and 65 nm technology nodes. The combined effect of gate fringing field and do pant redistribution has been considered for developing the model. The trench oxide parasitic capacitance is evaluated by conformal mapping technique and is then used to determine the width-dependent threshold voltage shift. The developed model has been validated by comparing the results predicted from the derived model with experimental data, simulation data and also with a similar model available in literature. It has been demonstrated that our model predicts more correctly the inverse narrow width effect on threshold voltage of nano-scale devices compared to the existing model.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130371680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To reduce pessimism in cross talk analysis, a key technique that is employed is the use of timing windows. However, timing windows are associated with corners, hence the use of a single corner timing windows during analysis can lead to optimism. Alternately if the timings windows from best and worst corners are combined to create a wider window, it can lead to excessive pessimism. We propose an approach based on parametrized statistical timing analysis modeling to overcome the shortcomings of the existing approaches, and to account for process variations in the defnition of timing windows. We show that this approach can overcome both the issues in the current approaches.
{"title":"Improved Timing Windows Overlap Check Using Statistical Timing Analysis","authors":"Sachin Shrivastava, H. Parameswaran","doi":"10.1109/VLSID.2011.21","DOIUrl":"https://doi.org/10.1109/VLSID.2011.21","url":null,"abstract":"To reduce pessimism in cross talk analysis, a key technique that is employed is the use of timing windows. However, timing windows are associated with corners, hence the use of a single corner timing windows during analysis can lead to optimism. Alternately if the timings windows from best and worst corners are combined to create a wider window, it can lead to excessive pessimism. We propose an approach based on parametrized statistical timing analysis modeling to overcome the shortcomings of the existing approaches, and to account for process variations in the defnition of timing windows. We show that this approach can overcome both the issues in the current approaches.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mobile devices and embedded devices need more processing power but energy consumption should be less to save battery power. Google has released an open source platform Android for mobile devices. Android uses new power management framework to save power in mobile devices. Android developers are allowed to build only JAVA applications. In this work, we present benefits of using Android in low power embedded devices. We compared Android JAVA performance with popular Sun embedded JVM running on top of Angstrom linux. Our work shows that Android can be made more energy efficient by improving performance of JAVA applications. We developed a JAVA DSP framework which allows Android JAVA applications to use both ARM & DSP parallely and thus improves performance. We also showed, Android can be made more energy efficient by using our developed framework.
{"title":"Improving Android Performance and Energy Efficiency","authors":"T. K. Kundu, K. Paul","doi":"10.1109/VLSID.2011.63","DOIUrl":"https://doi.org/10.1109/VLSID.2011.63","url":null,"abstract":"Mobile devices and embedded devices need more processing power but energy consumption should be less to save battery power. Google has released an open source platform Android for mobile devices. Android uses new power management framework to save power in mobile devices. Android developers are allowed to build only JAVA applications. In this work, we present benefits of using Android in low power embedded devices. We compared Android JAVA performance with popular Sun embedded JVM running on top of Angstrom linux. Our work shows that Android can be made more energy efficient by improving performance of JAVA applications. We developed a JAVA DSP framework which allows Android JAVA applications to use both ARM & DSP parallely and thus improves performance. We also showed, Android can be made more energy efficient by using our developed framework.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126594462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The variation of intra-die process parameters play a significant role in determining the yield of an analog/RF circuit. This paper presents statistical results demonstrating the effect of variations of process parameters on a nano-scale CMOS voltage controlled oscillator circuit. A statistical model relating the process parameter variations and the performance variations has been constructed using artificial neural network. The constructed model shows accuracy similar to that obtained though Monte Carlo analysis technique, however, consuming much less time.
{"title":"Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network","authors":"S. Mandal, Soumya Pandit","doi":"10.1109/VLSID.2011.28","DOIUrl":"https://doi.org/10.1109/VLSID.2011.28","url":null,"abstract":"The variation of intra-die process parameters play a significant role in determining the yield of an analog/RF circuit. This paper presents statistical results demonstrating the effect of variations of process parameters on a nano-scale CMOS voltage controlled oscillator circuit. A statistical model relating the process parameter variations and the performance variations has been constructed using artificial neural network. The constructed model shows accuracy similar to that obtained though Monte Carlo analysis technique, however, consuming much less time.","PeriodicalId":371062,"journal":{"name":"2011 24th Internatioal Conference on VLSI Design","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132582045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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