Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365819
Qiaochu Zhang, Shiyu Su, C. Ho, M. Chen
Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scaling-friendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has been increasing interest in injecting a low-noise reference clock signal to the RO to refresh the accumulated jitter, as seen in multiplying delay-locked loops (MDLLs) and injection-locked phase-locked loops (1L-pLLs). The main challenge of this architecture is that the injection signal derived from the reference clock is not perfectly aligned with the RO phase at the injection node, hence spurious tones are generated, and this phase alignment issue is especially exacerbated in fractional-N 0peration as the injection time paint must gradually drift away from the reference clock phase [1]. One way of achieving this required phase drift is by tuning digital-to-time converters (DTCs) according to a fractional frequency multiplication ratio; however, DTC offset and gain errors can introduce spurs. Several works have demonstrated DTC calibration, but are either limited to foreground calibration or incur an additional time-to-digital converter (TDC) [2], [3]. To further suppress injection-locking-induced spurs, we propose a background DTC calibration scheme that: 1) simultaneously estimates DTC gain and offset errors by occasional injection squelching; 2) performs two-point gain and offset error correction in the respective analog and digital domains; 3) uses TDC dithering [4] to enhance error estimation accuracy; and 4) removes dithering noise with an adaptive comb-filter-assisted cancellation loop. To prove the concept, a fractional-N digital MDLL using the DTC calibration scheme is implemented in 65nm CMOS and demonstrates 1.67ps RMS jitter and -60dBc fractional spur with 26dB spur suppression.
{"title":"29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur","authors":"Qiaochu Zhang, Shiyu Su, C. Ho, M. Chen","doi":"10.1109/ISSCC42613.2021.9365819","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365819","url":null,"abstract":"Ring oscillator (RO)-based frequency synthesizers enable cost-efficient and scaling-friendly implementation, but also result in worse phase noise compared to LC-based alternatives. There has been increasing interest in injecting a low-noise reference clock signal to the RO to refresh the accumulated jitter, as seen in multiplying delay-locked loops (MDLLs) and injection-locked phase-locked loops (1L-pLLs). The main challenge of this architecture is that the injection signal derived from the reference clock is not perfectly aligned with the RO phase at the injection node, hence spurious tones are generated, and this phase alignment issue is especially exacerbated in fractional-N 0peration as the injection time paint must gradually drift away from the reference clock phase [1]. One way of achieving this required phase drift is by tuning digital-to-time converters (DTCs) according to a fractional frequency multiplication ratio; however, DTC offset and gain errors can introduce spurs. Several works have demonstrated DTC calibration, but are either limited to foreground calibration or incur an additional time-to-digital converter (TDC) [2], [3]. To further suppress injection-locking-induced spurs, we propose a background DTC calibration scheme that: 1) simultaneously estimates DTC gain and offset errors by occasional injection squelching; 2) performs two-point gain and offset error correction in the respective analog and digital domains; 3) uses TDC dithering [4] to enhance error estimation accuracy; and 4) removes dithering noise with an adaptive comb-filter-assisted cancellation loop. To prove the concept, a fractional-N digital MDLL using the DTC calibration scheme is implemented in 65nm CMOS and demonstrates 1.67ps RMS jitter and -60dBc fractional spur with 26dB spur suppression.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131209160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/isscc42613.2021.9365794
{"title":"ISSCC 2021 Back Cover","authors":"","doi":"10.1109/isscc42613.2021.9365794","DOIUrl":"https://doi.org/10.1109/isscc42613.2021.9365794","url":null,"abstract":"","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134243239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365857
J. Holloway, G. Dogiamis, R. Han
The rapid surge of data transmission within computation, storage and communication infrastructures is pushing the speed boundary of traditional copper-based electrical links. Recent realizations of l00Gb/s wired links require advanced FinFET technologies, highcost packaging/cables and power-consuming equalization. High-frequency waves over dielectric waveguides have been considered as an alternative solution that exploits the low-loss, broadband medium while maintaining compatibility with existing silicon 1C platforms. However, since its debut in 2011 [1], this scheme, previously using $leq 140mathrm{G}mathrm{H}mathrm{z}$ carriers, has only achieved data rates of up to 36Gb/s[2]. lt is expected that higher carrier frequencies (e.g. >200GHz) and multi-channel aggregation would further increase the data rate while shrinking the interconnect size; but that scheme has been hindered by challenges related to the required high-order multiplexer and ultra-broadband waveguide coupler operating efficiently at sub terahertz (sub-THz) frequencies. in this paper, using a 130nmSiGe BiCMOS technology, we present a multi-channel, multiplexer/coupler-integrated transmitter (Tx) that delivers a data rate of $105mathrm{G}mathrm{b}/mathrm{s}(3times 35mathrm{G}mathrm{b}/mathrm{s})$. To demodulate each channel, a 35Gb/s coupler-integrated receiver (Rx) is also developed. Ourlink, including the chipset and a 0. 4mm-wide, 30cm-long dielectric ribbon, experimentally demonstrates the potential speed, efficiency, size and cost advantages of THz fiber links in high-speed inter-server and backplane fabrics.
{"title":"A 105Gb/s Dielectric-Waveguide Link in 130nm BiCMOS Using Channelized 220-to-335GHz Signal and Integrated Waveguide Coupler","authors":"J. Holloway, G. Dogiamis, R. Han","doi":"10.1109/ISSCC42613.2021.9365857","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365857","url":null,"abstract":"The rapid surge of data transmission within computation, storage and communication infrastructures is pushing the speed boundary of traditional copper-based electrical links. Recent realizations of l00Gb/s wired links require advanced FinFET technologies, highcost packaging/cables and power-consuming equalization. High-frequency waves over dielectric waveguides have been considered as an alternative solution that exploits the low-loss, broadband medium while maintaining compatibility with existing silicon 1C platforms. However, since its debut in 2011 [1], this scheme, previously using $leq 140mathrm{G}mathrm{H}mathrm{z}$ carriers, has only achieved data rates of up to 36Gb/s[2]. lt is expected that higher carrier frequencies (e.g. >200GHz) and multi-channel aggregation would further increase the data rate while shrinking the interconnect size; but that scheme has been hindered by challenges related to the required high-order multiplexer and ultra-broadband waveguide coupler operating efficiently at sub terahertz (sub-THz) frequencies. in this paper, using a 130nmSiGe BiCMOS technology, we present a multi-channel, multiplexer/coupler-integrated transmitter (Tx) that delivers a data rate of $105mathrm{G}mathrm{b}/mathrm{s}(3times 35mathrm{G}mathrm{b}/mathrm{s})$. To demodulate each channel, a 35Gb/s coupler-integrated receiver (Rx) is also developed. Ourlink, including the chipset and a 0. 4mm-wide, 30cm-long dielectric ribbon, experimentally demonstrates the potential speed, efficiency, size and cost advantages of THz fiber links in high-speed inter-server and backplane fabrics.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124514785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365801
Tantan Zhang, Hyunwoo Son, Yuan Gao, Jingjing Lan, C. Heng
Bio-impedance (BioZ) is an important physiological parameter in wearable healthcare sensing. Besides the inherent cardiac and respiratory information, BioZ can be also used for other emerging applications such as non-invasive blood status sensing [1]. A conventiona14-e1ectrode (4E) setup eliminates the effect of electrode-tissue impedance (ETI) at the expense of user comfort, system complexity, and cost. On the other hand, a 2-electrode (2E) setup avoids short-falls of 4E but can only capture relative changes of Bi0Z instead of its absolute value. In addition, a readout front-end (RFE) with wide dynamic range (DR) and high signal-to-noise ratio (SNR) is needed to deal with small BioZ variation (0.1$sim10Omega$) as well as large baseline resistance (>10k$Omega$). A conventional RFE architecture employing an instrumentation amplifier (IA) and ADC has to trade-off between resolution, DR and noise [2, 3]. Although flicker noise in the current generator (CG) is mitigated through dynamic element matching (DEM) [2], the reference current (IREF) noise issue remains unaddressed. In [5], digital-assisted baseline cancellation and IREF correlated noise cancellation are proposed, which help eliminate IREF noise and input-dependent noise [4] due to the large signal in the current-balance instrumentation amplifier (CBIA). Nevertheless, larger noise is still observed due to the finite residual current $(I_{res})$ from the baseline cancellation.
{"title":"28.5 A 0.6V/0.9V 26.6-to-119.3µW ΔΣ-Based Bio-Impedance Readout IC with 101.9dB SNR and <0.1Hz 1/f Corner","authors":"Tantan Zhang, Hyunwoo Son, Yuan Gao, Jingjing Lan, C. Heng","doi":"10.1109/ISSCC42613.2021.9365801","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365801","url":null,"abstract":"Bio-impedance (BioZ) is an important physiological parameter in wearable healthcare sensing. Besides the inherent cardiac and respiratory information, BioZ can be also used for other emerging applications such as non-invasive blood status sensing [1]. A conventiona14-e1ectrode (4E) setup eliminates the effect of electrode-tissue impedance (ETI) at the expense of user comfort, system complexity, and cost. On the other hand, a 2-electrode (2E) setup avoids short-falls of 4E but can only capture relative changes of Bi0Z instead of its absolute value. In addition, a readout front-end (RFE) with wide dynamic range (DR) and high signal-to-noise ratio (SNR) is needed to deal with small BioZ variation (0.1$sim10Omega$) as well as large baseline resistance (>10k$Omega$). A conventional RFE architecture employing an instrumentation amplifier (IA) and ADC has to trade-off between resolution, DR and noise [2, 3]. Although flicker noise in the current generator (CG) is mitigated through dynamic element matching (DEM) [2], the reference current (IREF) noise issue remains unaddressed. In [5], digital-assisted baseline cancellation and IREF correlated noise cancellation are proposed, which help eliminate IREF noise and input-dependent noise [4] due to the large signal in the current-balance instrumentation amplifier (CBIA). Nevertheless, larger noise is still observed due to the finite residual current $(I_{res})$ from the baseline cancellation.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131828220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365773
A. Matamura, N. Nishimura, Preston Birdsong, A. Bandyopadhyay, Adam Spirer, M. Markova, Shaolong Liu
True Wireless Stereo/True Wireless Active-Noise-Canceling (ANC) headphones require low-latency digital-input headphone drivers that consume the lowest possible power to maximize battery life while providing high-fidelity audio playback. Typical headphone drivers use Class-A/AB topologies, and to improve power efficiency, Class-G/H drivers with a ground-center operation are used at the expense of using external components to decouple the required extra supply rails [1–3]. Closed-loop Class-D speaker drivers have become popular [4–6], and filter-less configurations are common in the 1-to-3W output range [6]. Some of the challenges associated with a Class-D driver for headphone applications are to maintain high linearity and SNR for low-voltage supply rails while reducing quiescent power. This paper describes a digital input, 93% efficient, filter-less Class-D amplifier achieving 113dB SNR and -93dB THD+N while operating from a single 1.8V supply.
{"title":"31.1 An 82mW ΔΣ - Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% Efficiency","authors":"A. Matamura, N. Nishimura, Preston Birdsong, A. Bandyopadhyay, Adam Spirer, M. Markova, Shaolong Liu","doi":"10.1109/ISSCC42613.2021.9365773","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365773","url":null,"abstract":"True Wireless Stereo/True Wireless Active-Noise-Canceling (ANC) headphones require low-latency digital-input headphone drivers that consume the lowest possible power to maximize battery life while providing high-fidelity audio playback. Typical headphone drivers use Class-A/AB topologies, and to improve power efficiency, Class-G/H drivers with a ground-center operation are used at the expense of using external components to decouple the required extra supply rails [1–3]. Closed-loop Class-D speaker drivers have become popular [4–6], and filter-less configurations are common in the 1-to-3W output range [6]. Some of the challenges associated with a Class-D driver for headphone applications are to maintain high linearity and SNR for low-voltage supply rails while reducing quiescent power. This paper describes a digital input, 93% efficient, filter-less Class-D amplifier achieving 113dB SNR and -93dB THD+N while operating from a single 1.8V supply.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122492851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365840
Jihwan Kim, S. Kundu, A. Balankutty, Matthew Beach, Bong Chan Kim, Stephen T. Kim, Yutao Liu, Savyassachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yongping Fan, F. O’Mahony
Wireline IOs have doubled per-lane data-rate every 3-4 years over the last two decades due to increasing demand in high-performance computing, networking/communications, and most recently from machine learning and AI. To address the need for higher throughput, this paper presents a 224Gb/s DAC-based PAM-4 TX with 8-tap FFE in 10nm CMOS technology. Doubling the data-rate from 112Gb/s while supporting the same PAM-4 modulation requires doubling the pad and internal net bandwidth and reducing the clocking jitter and circuit noise PSD by $2 times $ while maintaining swing, linearity, and reliability requirements. These are addressed by combining a low-noise on-chip LC-PLL, an inductive clock distribution network with jitter filtering, a two-stage 4:1 MUX with active peaking, and a group-delay-optimized output matching network for signal integrity.
{"title":"8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS","authors":"Jihwan Kim, S. Kundu, A. Balankutty, Matthew Beach, Bong Chan Kim, Stephen T. Kim, Yutao Liu, Savyassachi Keshava Murthy, Priya Wali, Kai Yu, Hyung Seok Kim, Chuanchang Liu, Dongseok Shin, Ariel Cohen, Yongping Fan, F. O’Mahony","doi":"10.1109/ISSCC42613.2021.9365840","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365840","url":null,"abstract":"Wireline IOs have doubled per-lane data-rate every 3-4 years over the last two decades due to increasing demand in high-performance computing, networking/communications, and most recently from machine learning and AI. To address the need for higher throughput, this paper presents a 224Gb/s DAC-based PAM-4 TX with 8-tap FFE in 10nm CMOS technology. Doubling the data-rate from 112Gb/s while supporting the same PAM-4 modulation requires doubling the pad and internal net bandwidth and reducing the clocking jitter and circuit noise PSD by $2 times $ while maintaining swing, linearity, and reliability requirements. These are addressed by combining a low-noise on-chip LC-PLL, an inductive clock distribution network with jitter filtering, a two-stage 4:1 MUX with active peaking, and a group-delay-optimized output matching network for signal integrity.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"43 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114115750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365931
Heyi Li, Z. Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Yihan Zhang, Le Ye, Ru Huang
Capacitive sensors are widely deployed in low-power IoT nodes, where power consumption is stringently limited by the batteries or energy harvesters. Energy-efficient interface circuits that convert sensing information into digital code are important for successful application of such sensors. Two humidity sensors based on a frequencylocking loop (FLL) [1] and a delta-sigma modulator (DSM) [2] achieve high resolution, but at the expense of high power consumption of 10.32μW and 15.6μW, respectively. The Zoom-based humidity sensor in [3] and capacitor-to-digital converters (CDC) in [3,4] exhibit a significantly improved dynamic range (DR). However, the DSM in the Zoom scheme typically entails large redundancy to cover the SAR conversion error due to noise or interference. Further, the OTA current budget is set to drive the maximum input capacitance, thus wasting power when driving typically small capacitance in most cases.
{"title":"5.1 A 1.5μW 0.135pJ·%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array","authors":"Heyi Li, Z. Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Yihan Zhang, Le Ye, Ru Huang","doi":"10.1109/ISSCC42613.2021.9365931","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365931","url":null,"abstract":"Capacitive sensors are widely deployed in low-power IoT nodes, where power consumption is stringently limited by the batteries or energy harvesters. Energy-efficient interface circuits that convert sensing information into digital code are important for successful application of such sensors. Two humidity sensors based on a frequencylocking loop (FLL) [1] and a delta-sigma modulator (DSM) [2] achieve high resolution, but at the expense of high power consumption of 10.32μW and 15.6μW, respectively. The Zoom-based humidity sensor in [3] and capacitor-to-digital converters (CDC) in [3,4] exhibit a significantly improved dynamic range (DR). However, the DSM in the Zoom scheme typically entails large redundancy to cover the SAR conversion error due to noise or interference. Further, the OTA current budget is set to drive the maximum input capacitance, thus wasting power when driving typically small capacitance in most cases.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"221 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116065167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365839
M. Lefebvre, Ludovic Moreau, R. Dekimpe, D. Bol
Mixed-signal vision chips are becoming increasingly popular for low-power embedded computer vision applications on smartphones, wearables and IoT nodes, as they meet stringent power and area constraints while maintaining a sufficient level of accuracy for low- to medium-level image processing tasks. On the one hand, in-sensor processing [1, 2] enables massively parallel operation but relies on pixel-level processing elements that degrade the pixel pitch and restrict the convolutional receptive field to neighboring pixels [1], precluding multi-scale operation. On the other hand, near-sensor processing [3–5] can operate at multiple scales by pixel downsampling [3] or binning [4] but entails significant power and area overhead as an analog memory is required to store pixel values awaiting processing. In addition, previous near-sensor processing SoCs are generally application-specific and thus suffer from limited versatility. In this paper, we present a 65nm QQVGA convolutional imager SoC codenamed SleepSpotter capable of versatile feature extraction and region-of-interest (RoI) detection based on in-sensor current-domain MAC operations. It operates at 6 different scales, features programmable filter size (F), stride (S), and ternary filter weights (1.5b). It reaches a minimum energy of 2.5pJ/pixel•frame•filter and a peak efficiency of 3.6TOPS/W, with 29% pixel area overhead for enabling the convolution and without the need for an analog memory.
{"title":"A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection","authors":"M. Lefebvre, Ludovic Moreau, R. Dekimpe, D. Bol","doi":"10.1109/ISSCC42613.2021.9365839","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365839","url":null,"abstract":"Mixed-signal vision chips are becoming increasingly popular for low-power embedded computer vision applications on smartphones, wearables and IoT nodes, as they meet stringent power and area constraints while maintaining a sufficient level of accuracy for low- to medium-level image processing tasks. On the one hand, in-sensor processing [1, 2] enables massively parallel operation but relies on pixel-level processing elements that degrade the pixel pitch and restrict the convolutional receptive field to neighboring pixels [1], precluding multi-scale operation. On the other hand, near-sensor processing [3–5] can operate at multiple scales by pixel downsampling [3] or binning [4] but entails significant power and area overhead as an analog memory is required to store pixel values awaiting processing. In addition, previous near-sensor processing SoCs are generally application-specific and thus suffer from limited versatility. In this paper, we present a 65nm QQVGA convolutional imager SoC codenamed SleepSpotter capable of versatile feature extraction and region-of-interest (RoI) detection based on in-sensor current-domain MAC operations. It operates at 6 different scales, features programmable filter size (F), stride (S), and ternary filter weights (1.5b). It reaches a minimum energy of 2.5pJ/pixel•frame•filter and a peak efficiency of 3.6TOPS/W, with 29% pixel area overhead for enabling the convolution and without the need for an analog memory.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125384336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365946
A. C. Oliveira, J. Groenesteijn, R. Wiegerink, K. Makinwa
Precision flow sensors are widely used in the pharmaceutical, food, and semiconductor industries to measure small amounts (<1 gram/hour) of liquids and gases. MEMS thermal flow sensors currently achieve state-of-the-art performance in terms of resolution, size, and power consumption [1, 3]. However, they only measure volumetric flow, and so must be calibrated for use with specific liquids [1] or gases [2, 3]. In contrast, Coriolis flow sensors measure mass flow and thus do not need calibration for specific fluids. Furthermore, their resonance frequency can be used as a measure of fluid density. These features enable significant size, cost, and complexity reductions in low-flow microfluidic systems. Although much progress has been made, miniature [4] and MEMS [5– 7] Coriolis mass flow sensors are still outperformed by their thermal counterparts, especially in terms of resolution and long-term stability.
{"title":"5.7 A MEMS Coriolis Mass Flow Sensor with 300 μ g/h/√Hz Resolution and ± 0.8mg/h Zero Stability","authors":"A. C. Oliveira, J. Groenesteijn, R. Wiegerink, K. Makinwa","doi":"10.1109/ISSCC42613.2021.9365946","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365946","url":null,"abstract":"Precision flow sensors are widely used in the pharmaceutical, food, and semiconductor industries to measure small amounts (<1 gram/hour) of liquids and gases. MEMS thermal flow sensors currently achieve state-of-the-art performance in terms of resolution, size, and power consumption [1, 3]. However, they only measure volumetric flow, and so must be calibrated for use with specific liquids [1] or gases [2, 3]. In contrast, Coriolis flow sensors measure mass flow and thus do not need calibration for specific fluids. Furthermore, their resonance frequency can be used as a measure of fluid density. These features enable significant size, cost, and complexity reductions in low-flow microfluidic systems. Although much progress has been made, miniature [4] and MEMS [5– 7] Coriolis mass flow sensors are still outperformed by their thermal counterparts, especially in terms of resolution and long-term stability.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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