Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365843
Chengjie Zhu, Jesús Maldonado, Hao Tang, S. Venkatesh, K. Sengupta
The emergence of the pandemic has demonstrated the necessity of point-of-care (POC) molecular diagnostic platforms that encompass an end-to-end system (from sample fluid to diagnostic information) with the ability to allow rapid analysis on the spot. While POC sensing technologies have been demonstrated in miniaturize chip-scale platforms [1–5], the bottlenecks in enabling end-to-end low-cost handheld platforms have often been bio-sample handling, filtering, mixing with re-agents that are critical to the robustness of the assay chemistry and sensing sensitivity/specificity. These processes are typically carried out either manually or by employing complex pneumatic flow control with multiple bulky syringe pumps, which have been a severe limitation to enable end-to-end biosensing systems (Fig. 18.2.1). While electrically driven droplets, molecular and cell manipulation techniques, such as electro-wetting, electrophoresis and dielectrophoresis, have been demonstrated in singular systems before [1], they do not have the ability to process bulk bio-sample fluids that is required for POC devices. In this paper, we present a scalable approach that merges the functionalities of sample processing and cellular/bio-molecular sensing in a single system and eliminates any pneumatic pumping mechanisms by exploiting CMOS-based electrically driven electro-kinetic flow of bulk fluids. We demonstrate, for the first time, a CMOS-microfluidic system that is capable of 1) pumping bulk electrolyte fluid with AC electro-osmosis, 2) cell manipulation and separation with dielectrophoresis (DEP), 3) label-free biomolecular and cell sensing, classification with dedicated 16-element impedance spectroscopy receivers. While we demonstrate these kernel functionalities in a multichip module/microfluidic interface (Fig. 18.2.1), the overall architecture, fluidics and sensing components can be massively scaled up for various POC applications due to elimination of pressure-driven flows (Fig. 18.2.1).
{"title":"CMOS-Driven Pneumatic-Free Scalable Microfluidics and Fluid Processing with Label-Free Cellular and Bio-Molecular Sensing Capability for an End-to-End Point-of-Care System","authors":"Chengjie Zhu, Jesús Maldonado, Hao Tang, S. Venkatesh, K. Sengupta","doi":"10.1109/ISSCC42613.2021.9365843","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365843","url":null,"abstract":"The emergence of the pandemic has demonstrated the necessity of point-of-care (POC) molecular diagnostic platforms that encompass an end-to-end system (from sample fluid to diagnostic information) with the ability to allow rapid analysis on the spot. While POC sensing technologies have been demonstrated in miniaturize chip-scale platforms [1–5], the bottlenecks in enabling end-to-end low-cost handheld platforms have often been bio-sample handling, filtering, mixing with re-agents that are critical to the robustness of the assay chemistry and sensing sensitivity/specificity. These processes are typically carried out either manually or by employing complex pneumatic flow control with multiple bulky syringe pumps, which have been a severe limitation to enable end-to-end biosensing systems (Fig. 18.2.1). While electrically driven droplets, molecular and cell manipulation techniques, such as electro-wetting, electrophoresis and dielectrophoresis, have been demonstrated in singular systems before [1], they do not have the ability to process bulk bio-sample fluids that is required for POC devices. In this paper, we present a scalable approach that merges the functionalities of sample processing and cellular/bio-molecular sensing in a single system and eliminates any pneumatic pumping mechanisms by exploiting CMOS-based electrically driven electro-kinetic flow of bulk fluids. We demonstrate, for the first time, a CMOS-microfluidic system that is capable of 1) pumping bulk electrolyte fluid with AC electro-osmosis, 2) cell manipulation and separation with dielectrophoresis (DEP), 3) label-free biomolecular and cell sensing, classification with dedicated 16-element impedance spectroscopy receivers. While we demonstrate these kernel functionalities in a multichip module/microfluidic interface (Fig. 18.2.1), the overall architecture, fluidics and sensing components can be massively scaled up for various POC applications due to elimination of pressure-driven flows (Fig. 18.2.1).","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133870522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365808
Nevada Sanchez, Kailiang Chen, Chao Chen, D. McMahill, Sewook Hwang, J. Lutsky, Jungwook Yang, Liewei Bao, Leung Kin Chiu, Graham Peyton, H. Soleimani, Bob Ryan, J. R. Petrus, Youn-Jae Kook, T. Ralston, K. Fife, J. Rothberg
Point-of-care ultrasound (POCUS) is transforming healthcare worldwide as a diagnostic tool with the potential to significantly reduce the delay between symptom onset and initiation of therapy. Conventional POCUS systems are based on piezoelectric transducers and cable-connected electronics, which require a costly manufacturing process and usually come with an undesirably limited channel count. Such devices typically serve a specific subset of clinical applications, as imaging at different body parts calls for different ultrasound frequencies that are beyond the bandwidth of a single piezoelectric transducer. To enable whole-body imaging, multiple probes with different frequencies, apertures and beamforming (BF) methods are generally required. This further limits the affordability and accessibility of POCUS. Recent advances in micromachined ultrasound transducers (MUTs) have offered an alternative path to addressing these challenges. However, previous attempts to integrate MUTs with chips have been incomplete, neither solving the integration problem [1, 2] nor achieving full ultrasound processing capabilities [3, 4].
{"title":"34.1 An 8960-Element Ultrasound-on-Chip for Point-of-Care Ultrasound","authors":"Nevada Sanchez, Kailiang Chen, Chao Chen, D. McMahill, Sewook Hwang, J. Lutsky, Jungwook Yang, Liewei Bao, Leung Kin Chiu, Graham Peyton, H. Soleimani, Bob Ryan, J. R. Petrus, Youn-Jae Kook, T. Ralston, K. Fife, J. Rothberg","doi":"10.1109/ISSCC42613.2021.9365808","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365808","url":null,"abstract":"Point-of-care ultrasound (POCUS) is transforming healthcare worldwide as a diagnostic tool with the potential to significantly reduce the delay between symptom onset and initiation of therapy. Conventional POCUS systems are based on piezoelectric transducers and cable-connected electronics, which require a costly manufacturing process and usually come with an undesirably limited channel count. Such devices typically serve a specific subset of clinical applications, as imaging at different body parts calls for different ultrasound frequencies that are beyond the bandwidth of a single piezoelectric transducer. To enable whole-body imaging, multiple probes with different frequencies, apertures and beamforming (BF) methods are generally required. This further limits the affordability and accessibility of POCUS. Recent advances in micromachined ultrasound transducers (MUTs) have offered an alternative path to addressing these challenges. However, previous attempts to integrate MUTs with chips have been incomplete, neither solving the integration problem [1, 2] nor achieving full ultrasound processing capabilities [3, 4].","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131475504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9366056
Jian Ouyang, Xueliang Du, Yin Ma, Jiaqiang Liu
In order to be able to handle a wide range of AI applications, such as for speech, image, language and autonomous driving, it is necessary that an AI accelerator be flexible enough to handle diversified workloads. Baidu Kunlun, an AI chip designed in-house by Baidu, achieves this capability with high programmability, flexibility and performance. Baidu Kunlun was inspired by the XPU architecture [1]. The chip is implemented in Samsung 14nm process technology. Its peak performance is 230TOPS@INT8 at 900MHz and up to 281TOPS@INT8 at 1.1GHz boost frequency. The memory bandwidth is 512GB/s and the peak power is 160W. Baidu Kunlun achieves good performance across various types of workloads. With 900MHz base frequency, the latencies of BERT, ResNet50, YOLOv3 are $1.7 times, 1.2 times$ and $2 times$ less than an Nvidia T4 GPU, respectively, with optimizations from TensorRT. Recently, Baidu Kunlun has been deployed in data centers in Baidu to serve many applications. It achieves 1.5-to$- 3 times$ better performance for several models within the search engine vs. the Nvidia T4.
{"title":"Kunlun: A 14nm High-Performance AI Processor for Diversified Workloads","authors":"Jian Ouyang, Xueliang Du, Yin Ma, Jiaqiang Liu","doi":"10.1109/ISSCC42613.2021.9366056","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366056","url":null,"abstract":"In order to be able to handle a wide range of AI applications, such as for speech, image, language and autonomous driving, it is necessary that an AI accelerator be flexible enough to handle diversified workloads. Baidu Kunlun, an AI chip designed in-house by Baidu, achieves this capability with high programmability, flexibility and performance. Baidu Kunlun was inspired by the XPU architecture [1]. The chip is implemented in Samsung 14nm process technology. Its peak performance is 230TOPS@INT8 at 900MHz and up to 281TOPS@INT8 at 1.1GHz boost frequency. The memory bandwidth is 512GB/s and the peak power is 160W. Baidu Kunlun achieves good performance across various types of workloads. With 900MHz base frequency, the latencies of BERT, ResNet50, YOLOv3 are $1.7 times, 1.2 times$ and $2 times$ less than an Nvidia T4 GPU, respectively, with optimizations from TensorRT. Recently, Baidu Kunlun has been deployed in data centers in Baidu to serve many applications. It achieves 1.5-to$- 3 times$ better performance for several models within the search engine vs. the Nvidia T4.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132642354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365955
Dongfang Pan, Guolong Li, Fangting Miao, Biao Deng, Junying Wei, Daquan Yu, Ming Liu, Lin Cheng
Power delivering with galvanic isolation is essential to guarantee system safety and reliability in harsh industry environments. However, efficiently transferring power of hundreds of mW across an isolation barrier is challenging for such size- and costconstrained applications. Isolated capacitive power transfer using on-chip capacitors and an off-chip inductor is demonstrated in [1], but it only delivers 62mW power with less1 kV isolation voltage that is limited by the on-chip capacitors. To increase the output power and the isolation voltage, isolated DC-DC converters using silicon-based postprocessed micro-transformers have been reported recently [2] –[4]. In [2], 6-$mu mathrm{m}$-thick plated Au are used for both the primary and the secondary coil windings to achieve quality factors of 6.8 at 200MHz, while the efficiency of the converter is lower than 34% with a maximum output power of 0.8W. A performance-enhanced micro-transformer using a magnetic core is proposed in [3] to achieve a peak efficiency of 52% and a maximum output power of 1.1W. However, the fabrication process of such a transformer is complex and the cost is high. In [4], the micro-transformer is formed by using ultrathick metal windings, and high inductances with high quality factors are achieved to allow the converter to switch at 11MHz. However, the topology proposed produces large resonant currents that flow into the coils, degrading the efficiency to 34% with only 165mW output power. Moreover, the abovementioned isolated converters are assembled in a small-outline integrated-circuit (SOIC) 8-lead [2] or 28-lead [3] packages that measure 6mm $times 10$ mm or 10mm $times 18$ mm, respectively, resulting in a maximum power density of only 13.33mW/mm2.
{"title":"A 1.25W 46.5%-Peak-Efficiency Transformer-in-Package Isolated DC-DC Converter Using Glass-Based Fan-Out Wafer-Level Packaging Achieving 50mW/mm2 Power Density","authors":"Dongfang Pan, Guolong Li, Fangting Miao, Biao Deng, Junying Wei, Daquan Yu, Ming Liu, Lin Cheng","doi":"10.1109/ISSCC42613.2021.9365955","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365955","url":null,"abstract":"Power delivering with galvanic isolation is essential to guarantee system safety and reliability in harsh industry environments. However, efficiently transferring power of hundreds of mW across an isolation barrier is challenging for such size- and costconstrained applications. Isolated capacitive power transfer using on-chip capacitors and an off-chip inductor is demonstrated in [1], but it only delivers 62mW power with less1 kV isolation voltage that is limited by the on-chip capacitors. To increase the output power and the isolation voltage, isolated DC-DC converters using silicon-based postprocessed micro-transformers have been reported recently [2] –[4]. In [2], 6-$mu mathrm{m}$-thick plated Au are used for both the primary and the secondary coil windings to achieve quality factors of 6.8 at 200MHz, while the efficiency of the converter is lower than 34% with a maximum output power of 0.8W. A performance-enhanced micro-transformer using a magnetic core is proposed in [3] to achieve a peak efficiency of 52% and a maximum output power of 1.1W. However, the fabrication process of such a transformer is complex and the cost is high. In [4], the micro-transformer is formed by using ultrathick metal windings, and high inductances with high quality factors are achieved to allow the converter to switch at 11MHz. However, the topology proposed produces large resonant currents that flow into the coils, degrading the efficiency to 34% with only 165mW output power. Moreover, the abovementioned isolated converters are assembled in a small-outline integrated-circuit (SOIC) 8-lead [2] or 28-lead [3] packages that measure 6mm $times 10$ mm or 10mm $times 18$ mm, respectively, resulting in a maximum power density of only 13.33mW/mm2.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9366002
Somok Mondal, Omid Ghadami, D. Hall
Continuous-time delta-sigma modulators (CT $Delta Sigma mathrm{Ms}$) have inherent anti-aliasing, resistive inputs, and relaxed settling requirements making them popular for audio applications. Due to the relatively low bandwidth, the noise-efficiency of the first OTA has a substantial influence on the power and FoM. OTA-stacking is a recently reported technique that improves the noise-current tradeoff in continuous-time amplifiers [1], [2]. This is the central idea behind the proposed CT $DeltaSigma$ M where an AC-coupled stacked OTA improves the noise-efficiency of the first integrator. The ADC with a 3-stack OTA achieves 100.9 dB SNDR and $104.8 mathrm{dB} mathrm{DR}$ in a 24 kHz bandwidth while consuming $139 mu mathrm{W}$ for a state-of-the-art Schreier $FoM _{mathrm{DR}}$ of 187.2 dB.
连续时间delta-sigma调制器(CT $Delta Sigma mathrm{Ms}$)具有固有的抗混叠，电阻输入和宽松的解决要求，使其在音频应用中很受欢迎。由于第一OTA的带宽相对较低，因此噪声效率对功率和FoM有很大影响。ota堆叠是最近报道的一种技术，可以改善连续时间放大器的噪声-电流权衡[1]，[2]。这是所提出的CT $DeltaSigma$ M背后的核心思想，其中交流耦合堆叠OTA提高了第一个积分器的噪声效率。具有3堆栈OTA的ADC在24 kHz带宽下实现100.9 dB SNDR和$104.8 mathrm{dB} mathrm{DR}$，而最先进的Schreier $FoM _{mathrm{DR}}$功耗为$139 mu mathrm{W}$，为187.2 dB。
{"title":"10.2 A 139 µ W 104.8dB-DR 24 kHz-BW CT ΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs","authors":"Somok Mondal, Omid Ghadami, D. Hall","doi":"10.1109/ISSCC42613.2021.9366002","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366002","url":null,"abstract":"Continuous-time delta-sigma modulators (CT $Delta Sigma mathrm{Ms}$) have inherent anti-aliasing, resistive inputs, and relaxed settling requirements making them popular for audio applications. Due to the relatively low bandwidth, the noise-efficiency of the first OTA has a substantial influence on the power and FoM. OTA-stacking is a recently reported technique that improves the noise-current tradeoff in continuous-time amplifiers [1], [2]. This is the central idea behind the proposed CT $DeltaSigma$ M where an AC-coupled stacked OTA improves the noise-efficiency of the first integrator. The ADC with a 3-stack OTA achieves 100.9 dB SNDR and $104.8 mathrm{dB} mathrm{DR}$ in a 24 kHz bandwidth while consuming $139 mu mathrm{W}$ for a state-of-the-art Schreier $FoM _{mathrm{DR}}$ of 187.2 dB.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"19 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130715942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9366057
P. Paternoster, Andy Maki, A. Hernandez, Mark Grossman, M. Lau, David Sutherland, Aditya Mathad
The XBOX Series X System-on-Chip (SoC) delivers an enormous improvement over the prior generation with up to $2 times$ GPU performance, $3 times$ CPU performance, $2.4 times$ GPU performance/W, $1.7 times$ memory bandwidth and $2 times$ IO bandwidth to feed the additional processing capability and features shown in Fig. 3.1.1. The chip is fabricated in TSMC’s N7 process node [6], containing 15.3B transistors on a 360.4mm2 die. It is packaged in $mathrm{a}52.5 times 52.5$ mm2 BGA using a 12-layer (5-2-5) substrate with 2963 balls and a 0.80mm minimum ball pitch. A die photo is shown in Fig. 3.1.7. The IO-limited chip floorplan is driven by DRAM connections on 3 sides of the chip.
{"title":"XBOX Series X: A Next-Generation Gaming Console SoC","authors":"P. Paternoster, Andy Maki, A. Hernandez, Mark Grossman, M. Lau, David Sutherland, Aditya Mathad","doi":"10.1109/ISSCC42613.2021.9366057","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366057","url":null,"abstract":"The XBOX Series X System-on-Chip (SoC) delivers an enormous improvement over the prior generation with up to $2 times$ GPU performance, $3 times$ CPU performance, $2.4 times$ GPU performance/W, $1.7 times$ memory bandwidth and $2 times$ IO bandwidth to feed the additional processing capability and features shown in Fig. 3.1.1. The chip is fabricated in TSMC’s N7 process node [6], containing 15.3B transistors on a 360.4mm2 die. It is packaged in $mathrm{a}52.5 times 52.5$ mm2 BGA using a 12-layer (5-2-5) substrate with 2963 balls and a 0.80mm minimum ball pitch. A die photo is shown in Fig. 3.1.7. The IO-limited chip floorplan is driven by DRAM connections on 3 sides of the chip.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124557051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365818
Youngcheol Chae, Yun-Shiang Shu, J. Anders, V. Schaffer, T. Oshima, M. Corsi
The advances in high-precision analog front-end and data conversion circuits have opened up new opportunities in diverse application spaces. To keep fueling the evolution of emerging applications, such as health monitoring, industry 4.0, and internet of things, advanced sensing technology is required to further improve resolution, speed, as well as power and area efficiency of the system. This forum highlights the fundamental challenges with an emphasis on techniques to achieve the ultimate accuracy in analog circuits and data converters. Following an overview of analog-circuit challenges, a series of discussions start with essential high-accuracy voltage and frequency references along with the compensation techniques for their long-term drift, and then move on to the systemlevel functions of high-precision amplifiers, digital-to-analog converters, as well as overasampling and Nyquist-rate analog-to-digital converters, which are required to construct the overall signal chain.
{"title":"F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits","authors":"Youngcheol Chae, Yun-Shiang Shu, J. Anders, V. Schaffer, T. Oshima, M. Corsi","doi":"10.1109/ISSCC42613.2021.9365818","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365818","url":null,"abstract":"The advances in high-precision analog front-end and data conversion circuits have opened up new opportunities in diverse application spaces. To keep fueling the evolution of emerging applications, such as health monitoring, industry 4.0, and internet of things, advanced sensing technology is required to further improve resolution, speed, as well as power and area efficiency of the system. This forum highlights the fundamental challenges with an emphasis on techniques to achieve the ultimate accuracy in analog circuits and data converters. Following an overview of analog-circuit challenges, a series of discussions start with essential high-accuracy voltage and frequency references along with the compensation techniques for their long-term drift, and then move on to the systemlevel functions of high-precision amplifiers, digital-to-analog converters, as well as overasampling and Nyquist-rate analog-to-digital converters, which are required to construct the overall signal chain.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114358711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365863
K. Choo, Hyochan An, D. Sylvester, D. Blaauw
IoT sensors are in rising demand and they often require low power, yet high precision measurements. Under constrained energy, Nyquist-rate SAR ADCs are typically used for readout as they are energy efficient and easy to multiplex across many sensors. However, achieving high precision (>14b) in SAR ADCs is challenging as all factors limiting performance (resolution, mismatch, and noise) must be simultaneously addressed with minimal energy impact. In this paper, we present an energy-efficient, capacitor-array-assisted cascaded charge-injection SAR ADC (c-ciSAR) with 17b nominal resolution (14.14b ENOB) that achieves a 184.9dB Schreier FoM (SFoM) and 4.32fJ/conv with a 1V supply in 0.18μm CMOS. The ADC deploys a combination of techniques to improve resolution, mismatch, and noise performance while remaining energy-efficient, namely: 1) hybridization of a capacitor-array DAC (CDAC) with chargeinjection-cell (ci-cell) based DACs (ciDACs) to achieve high resolution and flexible programmability; 2) direct analog DAC mismatch compensation and repeated LSB decisions that leverage flexible programmability; 3) a noise-efficient charge-domain preamplifier for comparator (1.66 NEF) and SNR extended ci-cell; and 4) ±2?VDD signal sampling with pre-sampling MSB decision.
{"title":"14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC","authors":"K. Choo, Hyochan An, D. Sylvester, D. Blaauw","doi":"10.1109/ISSCC42613.2021.9365863","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365863","url":null,"abstract":"IoT sensors are in rising demand and they often require low power, yet high precision measurements. Under constrained energy, Nyquist-rate SAR ADCs are typically used for readout as they are energy efficient and easy to multiplex across many sensors. However, achieving high precision (>14b) in SAR ADCs is challenging as all factors limiting performance (resolution, mismatch, and noise) must be simultaneously addressed with minimal energy impact. In this paper, we present an energy-efficient, capacitor-array-assisted cascaded charge-injection SAR ADC (c-ciSAR) with 17b nominal resolution (14.14b ENOB) that achieves a 184.9dB Schreier FoM (SFoM) and 4.32fJ/conv with a 1V supply in 0.18μm CMOS. The ADC deploys a combination of techniques to improve resolution, mismatch, and noise performance while remaining energy-efficient, namely: 1) hybridization of a capacitor-array DAC (CDAC) with chargeinjection-cell (ci-cell) based DACs (ciDACs) to achieve high resolution and flexible programmability; 2) direct analog DAC mismatch compensation and repeated LSB decisions that leverage flexible programmability; 3) a noise-efficient charge-domain preamplifier for comparator (1.66 NEF) and SNR extended ci-cell; and 4) ±2?VDD signal sampling with pre-sampling MSB decision.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123647533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365846
O. Aiello, P. Crovetti, M. Alioto
In low-cost battery-less systems, capacitive sensing via capacitance-to-digital conversion (CDC) needs to operate with minimal or no support from additional circuitry such as voltage regulation, voltage/current references or digital post-processing as shown in Fig. 5.2.1 (e.g., for linearization). At the same time, direct harvesting demands operation down to very low voltages and power, to consistently fit the power available from the environment even when scarce (e.g., down to $sim mathrm{nW} / mathrm{mm}^{2}$ in light harvesters under realistic conditions). To enable continuous monitoring at power lower than the μW-range of state-of-the-art $sim 12$ -bit CDCs $[1-3], 7$ -to-8-bit architectures with power down to sub-nW have been demonstrated for sensor nodes [4], although their supply voltage requirement $(geq 0.6 mathrm{~V})$ is not suitable for direct harvesting, similar to [5]. CDCs for continuous monitoring at lower resolution $(sim 7$ bit) with sub-nW operation at $0.6 mathrm{~V}$ have been also demonstrated [6], although their power is burdened by the additional contribution of digital post-processing $(sim n W s)$ and others. A fully digital CDC has been introduced in [7] in the form of capacitance-to-voltage conversion via capacitor linear discharge due to a ring oscillator and final voltage-to-digital conversion, which requires two supply voltages of $0.45 mathrm{~V}$ and $1 mathrm{~V}$. Operation at minimal power also comes with measurement times in the sub-second or second scale [6,8] in addition to the reduced resolution, which are still in the range required by continuous monitoring in several applications [6,8] (e.g., temperature, humidity, proximity, fluid level monitoring).
在低成本的无电池系统中，通过电容-数字转换(CDC)进行的电容传感需要在电压调节、电压/电流参考或如图5.2.1所示的数字后处理(例如，用于线性化)等额外电路的支持下进行操作。与此同时，直接采集需要操作到非常低的电压和功率，以始终适应环境中可用的功率，即使在稀缺的情况下(例如，在现实条件下，光收割机的功率降至$sim mathrm{nW} / mathrm{mm}^{2}$)。为了在功率低于μ w范围的情况下实现对最先进的$sim 12$位cdc $[1-3], 7$至8位架构的连续监测，功耗降至亚nw[4]，尽管它们的电源电压要求$(geq 0.6 mathrm{~V})$不适合直接采集，类似于[5]。用于低分辨率($(sim 7$ bit)和亚nw运算($0.6 mathrm{~V}$)的连续监测的cdc也得到了证明[6]，尽管它们的能力受到数字后处理$(sim n W s)$和其他因素的额外贡献的影响。文献[7]中介绍了一种全数字CDC，通过环形振荡器的电容线性放电实现电容-电压转换，并最终实现电压-数字转换，需要$0.45 mathrm{~V}$和$1 mathrm{~V}$两个电源电压。除分辨率降低外，以最小功率运行还具有亚秒或秒尺度的测量时间[6,8]，这仍然在几个应用中连续监测所需的范围内[6,8](例如，温度，湿度，接近度，液位监测)。
{"title":"Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation","authors":"O. Aiello, P. Crovetti, M. Alioto","doi":"10.1109/ISSCC42613.2021.9365846","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365846","url":null,"abstract":"In low-cost battery-less systems, capacitive sensing via capacitance-to-digital conversion (CDC) needs to operate with minimal or no support from additional circuitry such as voltage regulation, voltage/current references or digital post-processing as shown in Fig. 5.2.1 (e.g., for linearization). At the same time, direct harvesting demands operation down to very low voltages and power, to consistently fit the power available from the environment even when scarce (e.g., down to $sim mathrm{nW} / mathrm{mm}^{2}$ in light harvesters under realistic conditions). To enable continuous monitoring at power lower than the μW-range of state-of-the-art $sim 12$ -bit CDCs $[1-3], 7$ -to-8-bit architectures with power down to sub-nW have been demonstrated for sensor nodes [4], although their supply voltage requirement $(geq 0.6 mathrm{~V})$ is not suitable for direct harvesting, similar to [5]. CDCs for continuous monitoring at lower resolution $(sim 7$ bit) with sub-nW operation at $0.6 mathrm{~V}$ have been also demonstrated [6], although their power is burdened by the additional contribution of digital post-processing $(sim n W s)$ and others. A fully digital CDC has been introduced in [7] in the form of capacitance-to-voltage conversion via capacitor linear discharge due to a ring oscillator and final voltage-to-digital conversion, which requires two supply voltages of $0.45 mathrm{~V}$ and $1 mathrm{~V}$. Operation at minimal power also comes with measurement times in the sub-second or second scale [6,8] in addition to the reduced resolution, which are still in the range required by continuous monitoring in several applications [6,8] (e.g., temperature, humidity, proximity, fluid level monitoring).","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124086907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365781
Yechan Park, Seok-Tae Koh, Jeongeun Lee, Hong-Gyeom Kim, Jaesuk Choi, S. Ha, Chul-Woong Kim, M. Je
The electrical cochlear implants (Cls) have given > 500,000 patients worldwide a better life to date. However, the electrical neural stimulation has limited spatial resolution due to the spread of stimulation current, which reduces the number of effective channels to < 10 and results in a restricted perception of sound. Recently developed CIs such as optogenetic Cls have overcome this limitation, enabling much higher effective channel count [1]. However, such CIs require much larger power consumption (>100mW) and a higher data transmission rate (>lMb/s) than conventional Cls. As a result, designing a simultaneous wireless power and data transfer (SWPDT) system becomes challenging. AIso, due to the short distance between transmitter (TX) and receiver (RX) coils separated only by a scalp, frequency splitting may occur, and it should be carefully considered.
{"title":"A Frequency-Splitting-Based Wireless Power and Data Transfer IC for Neural Prostheses with Simultaneous 115mWPower and 2.5Mb/s Forward Data Delivery","authors":"Yechan Park, Seok-Tae Koh, Jeongeun Lee, Hong-Gyeom Kim, Jaesuk Choi, S. Ha, Chul-Woong Kim, M. Je","doi":"10.1109/ISSCC42613.2021.9365781","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365781","url":null,"abstract":"The electrical cochlear implants (Cls) have given > 500,000 patients worldwide a better life to date. However, the electrical neural stimulation has limited spatial resolution due to the spread of stimulation current, which reduces the number of effective channels to < 10 and results in a restricted perception of sound. Recently developed CIs such as optogenetic Cls have overcome this limitation, enabling much higher effective channel count [1]. However, such CIs require much larger power consumption (>100mW) and a higher data transmission rate (>lMb/s) than conventional Cls. As a result, designing a simultaneous wireless power and data transfer (SWPDT) system becomes challenging. AIso, due to the short distance between transmitter (TX) and receiver (RX) coils separated only by a scalp, frequency splitting may occur, and it should be carefully considered.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"153 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125877350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：