Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365979
Robin Garg, Sanket Jain, Paul Dania, Arun Nataraian
Reduction in base-station deployment costs while increasing coverage has motivated Integrated Access and Backhaul (IAB) nodes in mm-wave 5G NR (Fig. 14.3.1). Similarly, high path loss due to shadowing and limited outdoor-to-indoor penetration at mm-wave has led to an interest in repeater/relays to extend 5G NR coverage [1]. Currently, halfduplexlinks based on TDD (preferred for lAB), FDD, spatial, and polarization-duplexare explored, targeting mm-wave TWRX isolation at the cost of channel capacity. While mmwave in-band full-duplex (IBFD) with shared antenna (ANT) interface can enable spectrum reuse in IAB and repeaters/relays, >100dB total self-interference cancellation (SIC) is required with up to 50dB of SIC in the mm-wave front-end [2]. Such SIC has been shown for IBFD at RF [3– 5], however mm-wave IBFD SIC with a shared antenna interface has been limited to 20dBat28GHz and 40dB(22dB at +10dBm TX SI power) at 60GHz [6, 7]. Achieving mm-wave IBFD SIC with a shared ANT interface is particularly challenging given (i) the high frequency of operation, (ii) wide 400MHz/800MHz bandwidths targeted in 5G NR, and (iii) variations in beamformer ANT impedance that changes the SI channel. This paper presents a fully integrated mm-wave circulator RX that addresses these challenges using (i) a hybrid-coupler and non-reciprocal N-path filter-based shared ANT interface that provides wideband SIC while creating an SI replica, enabling (ii) subsequent active cancellation with variable gain/phase shift to accommodate SI channel variations. The circulator RX implementation in 45nm SOI CMOS achieves 52. 8dB cancellation across 400MHz at 26. 4GHz(>100 $times$ improvement over state of the art at high power levels) with 3.1dB TX-to-ANT insertion loss (IL) and +11.5dBm TX power-handling. System-level feasibility for mm-wave wideband IBFD is shown with the integrated RX supporting 600MS/s128-OAM wireless reception (4.2Gb/s) with 3.3% RX EVM in the presence of an in-band 128-OAM 300MS/s (limited by instrument) TX SI signal, and SIC is demonstrated across SI channel changes using a global optimization approach.
{"title":"14.3 A 26GHz Full-Duplex Circulator Receiver with 53UB/400MHz(40UB/800MHz) Self-Interference Cancellation for mm-Wave Repeaters","authors":"Robin Garg, Sanket Jain, Paul Dania, Arun Nataraian","doi":"10.1109/ISSCC42613.2021.9365979","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365979","url":null,"abstract":"Reduction in base-station deployment costs while increasing coverage has motivated Integrated Access and Backhaul (IAB) nodes in mm-wave 5G NR (Fig. 14.3.1). Similarly, high path loss due to shadowing and limited outdoor-to-indoor penetration at mm-wave has led to an interest in repeater/relays to extend 5G NR coverage [1]. Currently, halfduplexlinks based on TDD (preferred for lAB), FDD, spatial, and polarization-duplexare explored, targeting mm-wave TWRX isolation at the cost of channel capacity. While mmwave in-band full-duplex (IBFD) with shared antenna (ANT) interface can enable spectrum reuse in IAB and repeaters/relays, >100dB total self-interference cancellation (SIC) is required with up to 50dB of SIC in the mm-wave front-end [2]. Such SIC has been shown for IBFD at RF [3– 5], however mm-wave IBFD SIC with a shared antenna interface has been limited to 20dBat28GHz and 40dB(22dB at +10dBm TX SI power) at 60GHz [6, 7]. Achieving mm-wave IBFD SIC with a shared ANT interface is particularly challenging given (i) the high frequency of operation, (ii) wide 400MHz/800MHz bandwidths targeted in 5G NR, and (iii) variations in beamformer ANT impedance that changes the SI channel. This paper presents a fully integrated mm-wave circulator RX that addresses these challenges using (i) a hybrid-coupler and non-reciprocal N-path filter-based shared ANT interface that provides wideband SIC while creating an SI replica, enabling (ii) subsequent active cancellation with variable gain/phase shift to accommodate SI channel variations. The circulator RX implementation in 45nm SOI CMOS achieves 52. 8dB cancellation across 400MHz at 26. 4GHz(>100 $times$ improvement over state of the art at high power levels) with 3.1dB TX-to-ANT insertion loss (IL) and +11.5dBm TX power-handling. System-level feasibility for mm-wave wideband IBFD is shown with the integrated RX supporting 600MS/s128-OAM wireless reception (4.2Gb/s) with 3.3% RX EVM in the presence of an in-band 128-OAM 300MS/s (limited by instrument) TX SI signal, and SIC is demonstrated across SI channel changes using a global optimization approach.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128604490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365986
Dongsu Kim, Jun-Suk Bang, Jongbeom Baek, Seungchan Park, Young-Ho Jung, Jae-Yeol Han, Ik-Hwan Kim, Sung-Youb Jung, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee, T. Cho
Envelope tracking (ET) is a key technology improving efficiency of RF power amplifiers (PAs) and battery lifetime in mobile handsets. It has been commercialized since 4G LTE era, and is also being employed in 5G NR handsets. A supply modulator (SM) is a circuit generating power supplies of RF PAs for ET and average power tracking (APT) operations. Currently, the maximum channel BW and supported ET BW of 5G NR handset is 100MHz [1]–[4]. In a short time, over 100MHz BW will be necessary to support intra-band contiguous carrier aggregation cases of n77C/n78C/n79C in 3GPP standard [5]. The required instantaneous maximum output power of SM is about 10W which is calculated by the following parameters: 26dBm output power by power class 2 (PC2), 2dB loss of RF front-end module (FEM) due to complex operating band combinations (EN-DC for non-standalone mode, NE-DC, 2CA/3CA), 6dB higher instantaneous power due to peak-to-average power ratio (PAPR) at 1 resource block (RB), 1dB margin, and poor PA efficiency of around 33% (worst example) due to high carrier frequency of 5GHz at n79 band. The poor PA efficiency can be relaxed by high voltage PA design beyond 5V. In [1], a supply modulator with boosted output larger than battery voltage $(V_{BAT})$ is proposed, and the designed PA with 30% higher voltage shows 10% higher efficiency and broader BW owing to low impedance transformation ratio from $50 Omega$ and small parasitic output capacitance of power cell. The challenge is how to design a supply modulator for 5G NR that can achieve both wide ET BW and high output voltage/power capability, while satisfying high efficiency, low receiver-band noise, short transition time, and multi-mode/standard operation.
{"title":"33.9 A Hybrid Switching Supply Modulator Achieving 130MHz Envelope-Tracking Bandwidth and 10W Output Power for 2G/3G/LTE/NR RF Power Amplifiers","authors":"Dongsu Kim, Jun-Suk Bang, Jongbeom Baek, Seungchan Park, Young-Ho Jung, Jae-Yeol Han, Ik-Hwan Kim, Sung-Youb Jung, Takahiro Nomiyama, Ji-Seon Paek, Jongwoo Lee, T. Cho","doi":"10.1109/ISSCC42613.2021.9365986","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365986","url":null,"abstract":"Envelope tracking (ET) is a key technology improving efficiency of RF power amplifiers (PAs) and battery lifetime in mobile handsets. It has been commercialized since 4G LTE era, and is also being employed in 5G NR handsets. A supply modulator (SM) is a circuit generating power supplies of RF PAs for ET and average power tracking (APT) operations. Currently, the maximum channel BW and supported ET BW of 5G NR handset is 100MHz [1]–[4]. In a short time, over 100MHz BW will be necessary to support intra-band contiguous carrier aggregation cases of n77C/n78C/n79C in 3GPP standard [5]. The required instantaneous maximum output power of SM is about 10W which is calculated by the following parameters: 26dBm output power by power class 2 (PC2), 2dB loss of RF front-end module (FEM) due to complex operating band combinations (EN-DC for non-standalone mode, NE-DC, 2CA/3CA), 6dB higher instantaneous power due to peak-to-average power ratio (PAPR) at 1 resource block (RB), 1dB margin, and poor PA efficiency of around 33% (worst example) due to high carrier frequency of 5GHz at n79 band. The poor PA efficiency can be relaxed by high voltage PA design beyond 5V. In [1], a supply modulator with boosted output larger than battery voltage $(V_{BAT})$ is proposed, and the designed PA with 30% higher voltage shows 10% higher efficiency and broader BW owing to low impedance transformation ratio from $50 Omega$ and small parasitic output capacitance of power cell. The challenge is how to design a supply modulator for 5G NR that can achieve both wide ET BW and high output voltage/power capability, while satisfying high efficiency, low receiver-band noise, short transition time, and multi-mode/standard operation.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130811047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365841
Erwin Allebes, Gaurav Singh, Yuming He, E. Tiurin, Paul Mateman, M. Ding, J. Dijkhuis, Gert-Jan van Schaik, E. Bechthum, J. V. D. Heuvel, Mohieddine El Soussi, Arjan Breeschoten, Hannu Korpela, Yao-Hong Liu, Christian Bachmann
The recent popularity of indoor-localization applications such as secure access and asset tracking has led to growing interest in accurate RF-based ranging solutions. Impulse-radio ultra-wideband (IR-UWB) is a promising solution for accurate ranging due to its wideband 0peration. The recently released IEEE 802. 15.4z standard [1] improves upon the security of ranging and mandates a coherent operation with higher mean pulse-repetition frequencies (mPRF), in comparison to the legacy standard IEEE 802. 15.4a. The next generation IR-UWB devices demand ultra-low-power operation while meeting the strict spectrum regulations to operate worldwide in C and X bands (4 to 10GHz). The prior-art coherent IR-UWB transmitters either consume very high power [2] or result in high spurious emissions in adjacent channels due to poor sidelobe suppression [3 –6]. In this work, an asynchronous polar transmitter is proposed that consumes 4.9mW active power with an output power spectral density (PSD) of -41.3dBm/MHz and a sidelobe suppression of over 28dBrin IEEE 802. 15.4zl24.8MHzmPRF mode, channel 9 (7987.2MHz). Further, we demonstrate the use of an injection-locked ring oscillator (IL-R0) with fine-grained duty-cycling of the TX chain to achieve state-of-the-art power consumption for mPRFs from 3.9MHz to 124. 8MHz while maintaining coherent operation over the packet.
{"title":"21.2 A 3-to-10GHz 180pJ/b IEEE802.15.4z/4a IR-UWB Coherent Polar Transmitter in 28nm CMOS with Asynchronous Amplitude Pulse-Shaping and Injection-Locked Phase Modulation","authors":"Erwin Allebes, Gaurav Singh, Yuming He, E. Tiurin, Paul Mateman, M. Ding, J. Dijkhuis, Gert-Jan van Schaik, E. Bechthum, J. V. D. Heuvel, Mohieddine El Soussi, Arjan Breeschoten, Hannu Korpela, Yao-Hong Liu, Christian Bachmann","doi":"10.1109/ISSCC42613.2021.9365841","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365841","url":null,"abstract":"The recent popularity of indoor-localization applications such as secure access and asset tracking has led to growing interest in accurate RF-based ranging solutions. Impulse-radio ultra-wideband (IR-UWB) is a promising solution for accurate ranging due to its wideband 0peration. The recently released IEEE 802. 15.4z standard [1] improves upon the security of ranging and mandates a coherent operation with higher mean pulse-repetition frequencies (mPRF), in comparison to the legacy standard IEEE 802. 15.4a. The next generation IR-UWB devices demand ultra-low-power operation while meeting the strict spectrum regulations to operate worldwide in C and X bands (4 to 10GHz). The prior-art coherent IR-UWB transmitters either consume very high power [2] or result in high spurious emissions in adjacent channels due to poor sidelobe suppression [3 –6]. In this work, an asynchronous polar transmitter is proposed that consumes 4.9mW active power with an output power spectral density (PSD) of -41.3dBm/MHz and a sidelobe suppression of over 28dBrin IEEE 802. 15.4zl24.8MHzmPRF mode, channel 9 (7987.2MHz). Further, we demonstrate the use of an injection-locked ring oscillator (IL-R0) with fine-grained duty-cycling of the TX chain to achieve state-of-the-art power consumption for mPRFs from 3.9MHz to 124. 8MHz while maintaining coherent operation over the packet.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130596314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/isscc42613.2021.9365787
{"title":"ISSCC 2022 Call for Papers","authors":"","doi":"10.1109/isscc42613.2021.9365787","DOIUrl":"https://doi.org/10.1109/isscc42613.2021.9365787","url":null,"abstract":"","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129694511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9366023
Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun
A high-order CTDSM can provide high resolution with a small OSR, but its design suffers from a few challenges. First, it requires a large number of OTAs [1]. This increases the design complexity and power. In addition, each OTA contributes extra phase delay, whose reduction requires increasing the OTA BW, further increasing power. Second, it is harder to stabilize, especially considering PVT variations. For example, a slight change in the RC time constant can cause instability. One way to address these issues is to use a passive discrete-time (DT) noise-shaping (NS) SAR ADC as quantizer [2], [3]. In [2], a 3rdorder DSM is built with only 1 OTA and a 2ndorder NS-SAR. Since it is set by device ratios, the NTF of a NS-SAR is PVT-robust. Hence, the 3rd order DSM stability is equivalent to that of a 1storder CTDSM, which is easy to ensure. Nevertheless, because its CT front-end provides only 1storder shaping, it cannot provide sufficient suppression for noises coming from later stages, limiting its SNDR to 70dB. Reference [3] increases the CT front-end order to 2 by using a single-amplifier-biquad (SAB), but its NS-SAR is only 1storder with a mild zero at 0.5, which limits its achievable resolution. Overall, both [2] and [3] achieve only 3rd order shaping with a Schreier FoM limited to 171dB.
高阶CTDSM可以用小OSR提供高分辨率，但其设计存在一些挑战。首先，它需要大量的ota[1]。这增加了设计的复杂性和功率。此外，每个OTA都会产生额外的相位延迟，降低相位延迟需要增加OTA的BW，从而进一步提高功率。其次，很难稳定，特别是考虑到PVT的变化。例如，RC时间常数的微小变化可能导致不稳定。解决这些问题的一种方法是使用无源离散时间(DT)噪声整形(NS) SAR ADC作为量化器[2]，[3]。在[2]中，仅使用1个OTA和一个2阶NS-SAR构建了一个3阶DSM。由于NTF是由设备比例决定的，因此NS-SAR的NTF具有pvt鲁棒性。因此，三阶DSM的稳定性等同于一级CTDSM的稳定性，易于保证。然而，由于其CT前端仅提供1阶整形，因此无法对来自后期的噪声提供足够的抑制，从而将其SNDR限制在70dB。参考文献[3]通过使用单放大器-双放大器(SAB)将CT前端阶数增加到2，但其NS-SAR仅为1阶，在0.5处为轻度零，这限制了其可实现的分辨率。总的来说，[2]和[3]都只能实现三阶整形，Schreier FoM限制在171dB。
{"title":"10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR","authors":"Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun","doi":"10.1109/ISSCC42613.2021.9366023","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366023","url":null,"abstract":"A high-order CTDSM can provide high resolution with a small OSR, but its design suffers from a few challenges. First, it requires a large number of OTAs [1]. This increases the design complexity and power. In addition, each OTA contributes extra phase delay, whose reduction requires increasing the OTA BW, further increasing power. Second, it is harder to stabilize, especially considering PVT variations. For example, a slight change in the RC time constant can cause instability. One way to address these issues is to use a passive discrete-time (DT) noise-shaping (NS) SAR ADC as quantizer [2], [3]. In [2], a 3rdorder DSM is built with only 1 OTA and a 2ndorder NS-SAR. Since it is set by device ratios, the NTF of a NS-SAR is PVT-robust. Hence, the 3rd order DSM stability is equivalent to that of a 1storder CTDSM, which is easy to ensure. Nevertheless, because its CT front-end provides only 1storder shaping, it cannot provide sufficient suppression for noises coming from later stages, limiting its SNDR to 70dB. Reference [3] increases the CT front-end order to 2 by using a single-amplifier-biquad (SAB), but its NS-SAR is only 1storder with a mild zero at 0.5, which limits its achievable resolution. Overall, both [2] and [3] achieve only 3rd order shaping with a Schreier FoM limited to 171dB.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126230202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365782
Yasser Moursy, T. Rosa, Lionel Jure, A. Quelen, S. Genevey, L. Pierrefeu, E. Collins, Joerg Winkler, Jonathan Park, G. Pillonnet, V. Huard, A. Bonzo, P. Flatresse
A near-threshold power supply aims to operate at the minimal energy point but suffers from high-sensitivity to process, temperature and voltage variations. Adaptive voltage scaling (AVS) is a well-known strategy to adapt the power supply to die-to-die and temperature variations [1]. However, AVS needs dedicated power supplies with nonnegligible overheads, e.g. extra die area, lower power converter efficiency, and with granularity limitations or complex fine-grain integration in the power mesh. SOI-based technologies offer unique features by biasing the wells below the transistors to tune the threshold voltage ($mathrm{V}_{mathrm{T}mathrm{H}}$). The well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating $mathrm{V}_{mathrm{T}mathrm{H}}$ variability according to process corners and temperature [1–5]. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm2, with low area and power overhead, e.g. 1.2% @ 2mm2 and 0.4% @ 10mm2, respectively. We properly quantify the gain in a mass-production context with a large statistical scope analysis across 316 measured dies from different split-wafer lots and from -40 to 125°C with a representative load (a Cortex M4F). Thanks to 3V asymmetrical wells amplitude swing, our ABB-IP brings up to 30% power reduction by decreasing the minimal power supply byl00mV, while maintaining the target operating frequency (50 MHz) with a high yield. Distributed timing monitors (DTM) guarantee an accurate timing monitoring of the biased digital load, while scalable well drivers adjust to the biased well area, enabling the ABB-IP genericity.
{"title":"A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology","authors":"Yasser Moursy, T. Rosa, Lionel Jure, A. Quelen, S. Genevey, L. Pierrefeu, E. Collins, Joerg Winkler, Jonathan Park, G. Pillonnet, V. Huard, A. Bonzo, P. Flatresse","doi":"10.1109/ISSCC42613.2021.9365782","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365782","url":null,"abstract":"A near-threshold power supply aims to operate at the minimal energy point but suffers from high-sensitivity to process, temperature and voltage variations. Adaptive voltage scaling (AVS) is a well-known strategy to adapt the power supply to die-to-die and temperature variations [1]. However, AVS needs dedicated power supplies with nonnegligible overheads, e.g. extra die area, lower power converter efficiency, and with granularity limitations or complex fine-grain integration in the power mesh. SOI-based technologies offer unique features by biasing the wells below the transistors to tune the threshold voltage ($mathrm{V}_{mathrm{T}mathrm{H}}$). The well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating $mathrm{V}_{mathrm{T}mathrm{H}}$ variability according to process corners and temperature [1–5]. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm2, with low area and power overhead, e.g. 1.2% @ 2mm2 and 0.4% @ 10mm2, respectively. We properly quantify the gain in a mass-production context with a large statistical scope analysis across 316 measured dies from different split-wafer lots and from -40 to 125°C with a representative load (a Cortex M4F). Thanks to 3V asymmetrical wells amplitude swing, our ABB-IP brings up to 30% power reduction by decreasing the minimal power supply byl00mV, while maintaining the target operating frequency (50 MHz) with a high yield. Distributed timing monitors (DTM) guarantee an accurate timing monitoring of the biased digital load, while scalable well drivers adjust to the biased well area, enabling the ABB-IP genericity.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"22 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114001455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365835
S. Trotta, D. Weber, Reinhard Jungmaier, Ashutosh Baheti, J. Lien, Dennis Noppeney, M. Tabesh, Christoph Rumpler, Michael Aichner, Siegfried Albel, Jagjit S. Bal, I. Poupyrev
With the introduction of the Internet of Things (IoT), there is an increasing focus on human-to-machine interaction. Nowadays, sensors make system and robots to see, hear, feel, and intuitively “understand” their surroundings. 60GHz radar [1] provides a very attractive solution for the sensing of human motion, enabling specific use cases such as: smart presence, hand gesture, and vital signs monitoring. Those can enhance the user experience in wearables, mobile devices, TVs, smart homes, automotive infotainment systems and AR-VR applications. The high bandwidth allocated in the 60GHz band (from 57 to 64GHz) enables very high range resolution sensing ($approx$ 2cm), which, when complemented with micro-Doppler and time domain analysis [2], offers a powerful tool for discriminating complex hand movements with millimeter accuracy. The solution presented in this paper represents the a tiny radar system integrated into a smartphone, the Google Pixel 4. The simplified signal flow pipeline, from the radar sensor up to the signal transformation and classification, is presented in Fig. 2.3.1 [3]. The radar sensor is designed primarily taking into account all the integration boundaries, which includes in primis power consumption and package size (including antenna). Specifically, the power consumption requirement translates to a very stringent requirement for the maximum number of chirps the sensor could run per frame, impacting the process gain, and so the maximum detection range.
{"title":"SOLI: A Tiny Device for a New Human Machine Interface","authors":"S. Trotta, D. Weber, Reinhard Jungmaier, Ashutosh Baheti, J. Lien, Dennis Noppeney, M. Tabesh, Christoph Rumpler, Michael Aichner, Siegfried Albel, Jagjit S. Bal, I. Poupyrev","doi":"10.1109/ISSCC42613.2021.9365835","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365835","url":null,"abstract":"With the introduction of the Internet of Things (IoT), there is an increasing focus on human-to-machine interaction. Nowadays, sensors make system and robots to see, hear, feel, and intuitively “understand” their surroundings. 60GHz radar [1] provides a very attractive solution for the sensing of human motion, enabling specific use cases such as: smart presence, hand gesture, and vital signs monitoring. Those can enhance the user experience in wearables, mobile devices, TVs, smart homes, automotive infotainment systems and AR-VR applications. The high bandwidth allocated in the 60GHz band (from 57 to 64GHz) enables very high range resolution sensing ($approx$ 2cm), which, when complemented with micro-Doppler and time domain analysis [2], offers a powerful tool for discriminating complex hand movements with millimeter accuracy. The solution presented in this paper represents the a tiny radar system integrated into a smartphone, the Google Pixel 4. The simplified signal flow pipeline, from the radar sensor up to the signal transformation and classification, is presented in Fig. 2.3.1 [3]. The radar sensor is designed primarily taking into account all the integration boundaries, which includes in primis power consumption and package size (including antenna). Specifically, the power consumption requirement translates to a very stringent requirement for the maximum number of chirps the sensor could run per frame, impacting the process gain, and so the maximum detection range.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121616346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365987
Hossein Jalili, O. Momeni
High-resolution and fast imaging/sensing at THz requires highly directive steerable beams for scanning the object. A coherent array of coupled sources could improve the radiated power but requires mechanical and slow scanning of the object [1]. Phased array systems could use beam steering to scan the object at a higher speed, but in both coherent-array and phased-array systems, large array sizes with high power consumption are needed to generate a highly directive and narrow beam for high image resolution [2 –4]. Although Si lens can be used to increase directivity in a phased array, the steering capability is significantly diminished [5]. Therefore, arrays of non-coherent sources are used with Si lens to illuminate different parts of the object with each source with high directivity [6]. The firing angle of each source is determined by the ratio of its displacement $(L_{dis})$ from the lens center to the lens radius $(R_{lens})$, as shown in Fig. 23.2.1 [1]. However, this type of source can only illuminate the object in discrete steps determined by beam spacing, which in turn is limited by the inevitable distance between adjacent sources on the chip. Being constrained to independent single pixels for illumination leads to loss of resolution and blind spots between the neighboring beams (Fig. 23.2.1). A larger lens can improve the resolution by reducing the beam spacing but at the cost of a smaller total scanning range.
{"title":"23.2 A 436-to-467GHz Lens-Integrated Reconfigurable Radiating Source with Continuous 2D Steering and Multi-Beam Operations in 65nm CMOS","authors":"Hossein Jalili, O. Momeni","doi":"10.1109/ISSCC42613.2021.9365987","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365987","url":null,"abstract":"High-resolution and fast imaging/sensing at THz requires highly directive steerable beams for scanning the object. A coherent array of coupled sources could improve the radiated power but requires mechanical and slow scanning of the object [1]. Phased array systems could use beam steering to scan the object at a higher speed, but in both coherent-array and phased-array systems, large array sizes with high power consumption are needed to generate a highly directive and narrow beam for high image resolution [2 –4]. Although Si lens can be used to increase directivity in a phased array, the steering capability is significantly diminished [5]. Therefore, arrays of non-coherent sources are used with Si lens to illuminate different parts of the object with each source with high directivity [6]. The firing angle of each source is determined by the ratio of its displacement $(L_{dis})$ from the lens center to the lens radius $(R_{lens})$, as shown in Fig. 23.2.1 [1]. However, this type of source can only illuminate the object in discrete steps determined by beam spacing, which in turn is limited by the inevitable distance between adjacent sources on the chip. Being constrained to independent single pixels for illumination leads to loss of resolution and blind spots between the neighboring beams (Fig. 23.2.1). A larger lens can improve the resolution by reducing the beam spacing but at the cost of a smaller total scanning range.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122509365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9366050
Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, M. Ahn, Dongkeon Lee, Seunghyun Cho, Dong-Yeon Park, Y.J. Park, Min-Soo Jang, Yongjun Kim, Jinyong Choi, Sung-Woo Yoon, Jaesu Jung, Jae-Koo Park, Jae-Woo Lee, D. Kwon, H. Cha, Si-Hyeong Cho, Seonghwan Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chankyung Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, N. Kim, Jung-Bae Lee
The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process.
{"title":"25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM","authors":"Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, M. Ahn, Dongkeon Lee, Seunghyun Cho, Dong-Yeon Park, Y.J. Park, Min-Soo Jang, Yongjun Kim, Jinyong Choi, Sung-Woo Yoon, Jaesu Jung, Jae-Koo Park, Jae-Woo Lee, D. Kwon, H. Cha, Si-Hyeong Cho, Seonghwan Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chankyung Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, N. Kim, Jung-Bae Lee","doi":"10.1109/ISSCC42613.2021.9366050","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366050","url":null,"abstract":"The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128600152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/isscc42613.2021.9365764
{"title":"ISSCC 2021 Index to Authors","authors":"","doi":"10.1109/isscc42613.2021.9365764","DOIUrl":"https://doi.org/10.1109/isscc42613.2021.9365764","url":null,"abstract":"","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"13 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114154660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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