In application of multiaxial fatigue theories, extrapolation of concepts developed from uniaxial fatigue research must be used with caution. Previous related research on plated-through hole (PTH) fatigue investigations has been based on so-called effective stress/strain methods, which did not account for the fact that fatigue crack nucleation and growth is observed to occur on specifically oriented planes. Moreover, previous related thermal stress/strain analyses on PTH has been based on so-called bilinear constitutive relations for modeling copper plating with a linear kinematic hardening assumption, and this cannot capture many aspects of cyclic stress/strain behavior during thermal excursions. In this paper, thermal stress analyses using thermodynamics-based constitutive models of metallic consituents of PTHs are conducted by finite element package ABAQUS (1995) for multiaxial fatigue studies. Two types of PTHs (via) are investigated: ordinary empty PTH and PTH with solder filler. Two thermal profiles which simulate temperature fields in service are applied, with one experiencing the glass transition temperature of FR4. Residual stresses generated from previous process temperature history are considered. From the stress analyses, critical plane orientations for tensile type and shear type fatigue cracks are located.
{"title":"Thermomechanical Stress Analyses of Plated-Through Holes in PWB Using Internal State Variable Constitutive Models","authors":"C. Fu, I. C. Ume, D. McDowell","doi":"10.1115/imece1996-0891","DOIUrl":"https://doi.org/10.1115/imece1996-0891","url":null,"abstract":"\u0000 In application of multiaxial fatigue theories, extrapolation of concepts developed from uniaxial fatigue research must be used with caution. Previous related research on plated-through hole (PTH) fatigue investigations has been based on so-called effective stress/strain methods, which did not account for the fact that fatigue crack nucleation and growth is observed to occur on specifically oriented planes. Moreover, previous related thermal stress/strain analyses on PTH has been based on so-called bilinear constitutive relations for modeling copper plating with a linear kinematic hardening assumption, and this cannot capture many aspects of cyclic stress/strain behavior during thermal excursions. In this paper, thermal stress analyses using thermodynamics-based constitutive models of metallic consituents of PTHs are conducted by finite element package ABAQUS (1995) for multiaxial fatigue studies. Two types of PTHs (via) are investigated: ordinary empty PTH and PTH with solder filler. Two thermal profiles which simulate temperature fields in service are applied, with one experiencing the glass transition temperature of FR4. Residual stresses generated from previous process temperature history are considered. From the stress analyses, critical plane orientations for tensile type and shear type fatigue cracks are located.","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114544276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the use of an integrated flow-thermo-mechanical analysis method and tools for numerically studying the effect of local heat transfer coefficient on anisothermal cyclic fatigue behavior of solder joints in a CBGA (ceramic ball grid array) package under power cycling. A cyclic chip power load of 1 watt to 10 watts at a frequency of 5 cph (cycles per hour) with an air flow speed of 0.5 m/s was used to simulate a typical field condition for a 32mm CBGA air cooled package. Temperature dependent viscoplastic properties of Pb-Sn (lead-tin) alloys were used to model the solder joint behavior in the package. An approach using the Δϵeqin-modified Coffin-Manson Law was applied to estimate the fatigue life of the solder joint. The Δϵeqin represents a saturated equivalent inelastic strain range as determined by the finite element model. The results of anisothermal deformation and fatigue response of solder joint are compared to that of a condition of constant temperature cycling.
{"title":"Anisothermal Fatigue Analysis of Solder Joints in a Convective CBGA Package Under Power Cycling","authors":"B. Z. Hong, T. Yuan, L. Burrell","doi":"10.1115/imece1996-0888","DOIUrl":"https://doi.org/10.1115/imece1996-0888","url":null,"abstract":"\u0000 This paper presents the use of an integrated flow-thermo-mechanical analysis method and tools for numerically studying the effect of local heat transfer coefficient on anisothermal cyclic fatigue behavior of solder joints in a CBGA (ceramic ball grid array) package under power cycling. A cyclic chip power load of 1 watt to 10 watts at a frequency of 5 cph (cycles per hour) with an air flow speed of 0.5 m/s was used to simulate a typical field condition for a 32mm CBGA air cooled package. Temperature dependent viscoplastic properties of Pb-Sn (lead-tin) alloys were used to model the solder joint behavior in the package. An approach using the Δϵeqin-modified Coffin-Manson Law was applied to estimate the fatigue life of the solder joint. The Δϵeqin represents a saturated equivalent inelastic strain range as determined by the finite element model. The results of anisothermal deformation and fatigue response of solder joint are compared to that of a condition of constant temperature cycling.","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125954480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Package warpage was studied previously using thermoelastic finite element analysis. Epoxy Molding Compound (EMC) was assumed to be thermal-elastic with temperature dependent mechanical properties (usually assigned values above and below the glass transition temperature, Tg). The effect of thermal mismatch of components inside the package was examined without considering the time history of the curing process. To account for this, this study will examine the effect of viscoelastic properties of EMC with different degree-of-cure on package warpage during the encapsulation process. In this study, warpage of a 160 leads Plastic Quad Flat Package (PQFP) was evaluated by employing a three-dimensional viscoelastic finite element model. Dynamic mechanical properties of the EMC for different degree-of-cure were measured in a Rheometrics RMS-800 analyzer at different temperatures: 160°C, 165°C, 170°C, 175°C, 180°C and 185°C to determine the viscoelastic shear modulus of G′ and G″. The test data were then used to formulate the Maxwell model for viscoelastic analysis using a commercial finite element package ABAQUS. The analysis examined the effect of degree-of-cure of EMC on warpage prediction. The predicted warpage values were compared with laboratory measurement using a Coordinate Measuring Machine (CMM).
{"title":"Viscoelastic Analysis of IC Package Warpage","authors":"T. S. Yeung, M. Yuen","doi":"10.1115/imece1996-0896","DOIUrl":"https://doi.org/10.1115/imece1996-0896","url":null,"abstract":"\u0000 Package warpage was studied previously using thermoelastic finite element analysis. Epoxy Molding Compound (EMC) was assumed to be thermal-elastic with temperature dependent mechanical properties (usually assigned values above and below the glass transition temperature, Tg). The effect of thermal mismatch of components inside the package was examined without considering the time history of the curing process. To account for this, this study will examine the effect of viscoelastic properties of EMC with different degree-of-cure on package warpage during the encapsulation process.\u0000 In this study, warpage of a 160 leads Plastic Quad Flat Package (PQFP) was evaluated by employing a three-dimensional viscoelastic finite element model. Dynamic mechanical properties of the EMC for different degree-of-cure were measured in a Rheometrics RMS-800 analyzer at different temperatures: 160°C, 165°C, 170°C, 175°C, 180°C and 185°C to determine the viscoelastic shear modulus of G′ and G″. The test data were then used to formulate the Maxwell model for viscoelastic analysis using a commercial finite element package ABAQUS. The analysis examined the effect of degree-of-cure of EMC on warpage prediction. The predicted warpage values were compared with laboratory measurement using a Coordinate Measuring Machine (CMM).","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130224592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Pao, E. Jih, V. Siddapureddy, X. Song, R. Liu, R. McMillan, J. M. Hu
The reliability of surface mount leadless solder joints, e.g., LCCC (leadless ceramic chip carrier), LCR (leadless chip resistor), and LCC (leadless chip capacitor), has been a long-term research topic due to the concern of thermal fatigue failure resulting from significant stresses and strains induced in the joint. Numerous studies of failure analysis of leadless solder joints exist in the literature, and a number of life prediction models based on different failure characterizing parameters, e.g., total strain, plastic strain, strain energy density, etc., have been developed for particular loading conditions, such as isothermal or thermal cyclic fatigue tests. To name a few, e.g., one can refer to Engelmaier (1984), Cltterbaugh and Charles (1985), Hall and Sherry (1986), Clech and Augis (1987), Wong et al. (1988), Bae et al. (1989), Solomon (1990), Frear et al. (1991), Satoh et al. (1991), Lee and Stone 91991), Lau (1991), Govila et al. (1994), Schroeder and Mitchell (1994), JPL (1994), Syed (1995), Wen and Ross (1995), Jih and Pao (1995), Zhang et al. (1996), Kawai et al. (1996), Hu (1996), Guo and Conrad (1996), Lin et al. (1996), and Lau and Pao (1996).
无引线陶瓷芯片载体(LCCC)、无引线芯片电阻器(LCR)和无引线芯片电容器(LCC)等表面贴装无铅焊点的可靠性一直是一个长期研究的课题，因为人们担心连接处产生的巨大应力和应变会导致热疲劳失效。文献中存在大量关于无铅焊点失效分析的研究，并且针对特定的加载条件，如等温或热循环疲劳试验，开发了许多基于不同失效特征参数(如总应变、塑性应变、应变能密度等)的寿命预测模型。等等,例如,一个可以参考Engelmaier (1984), Cltterbaugh和查尔斯(1985),大厅和雪莉(1986),Clech和Augis(1987),黄et al . (1988), Bae et al .(1989),所罗门(1990),Frear et al。(1991),Satoh et al。(1991),李和石91991年),刘(1991),Govila et al。(1994)、施罗德和米切尔(1994),喷气推进实验室(1994),赛义德(1995),他和罗斯(1995)》,Pao(1995),张et al。(1996),卡瓦依et al。(1996),胡(1996),郭和康拉德(1996),林et al。(1996),Lau和Pao(1996)。
{"title":"A Thermal Fatigue Model for Surface Mount Leadless Chip Resistor (LCR) Solder Joints","authors":"Y. Pao, E. Jih, V. Siddapureddy, X. Song, R. Liu, R. McMillan, J. M. Hu","doi":"10.1115/imece1996-0884","DOIUrl":"https://doi.org/10.1115/imece1996-0884","url":null,"abstract":"\u0000 The reliability of surface mount leadless solder joints, e.g., LCCC (leadless ceramic chip carrier), LCR (leadless chip resistor), and LCC (leadless chip capacitor), has been a long-term research topic due to the concern of thermal fatigue failure resulting from significant stresses and strains induced in the joint. Numerous studies of failure analysis of leadless solder joints exist in the literature, and a number of life prediction models based on different failure characterizing parameters, e.g., total strain, plastic strain, strain energy density, etc., have been developed for particular loading conditions, such as isothermal or thermal cyclic fatigue tests. To name a few, e.g., one can refer to Engelmaier (1984), Cltterbaugh and Charles (1985), Hall and Sherry (1986), Clech and Augis (1987), Wong et al. (1988), Bae et al. (1989), Solomon (1990), Frear et al. (1991), Satoh et al. (1991), Lee and Stone 91991), Lau (1991), Govila et al. (1994), Schroeder and Mitchell (1994), JPL (1994), Syed (1995), Wen and Ross (1995), Jih and Pao (1995), Zhang et al. (1996), Kawai et al. (1996), Hu (1996), Guo and Conrad (1996), Lin et al. (1996), and Lau and Pao (1996).","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127271165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently the plastic ball grid array (PBGA) has been gaining industry-wide acceptance in high pin count applications as a low-cost alternative to fine-pitch leaded packages such as the plastic quad flat pack (PQFP). The main factors leading to its use include low cost, high I/O density, a small footprint, and the potential for superior electrical and thermal performance with respect to PQFPs [Houghton 1993; Freyman and Pennisi, 1991]. However, concerns about interconnect reliability remain, particularly for systems to be joined with novel solders or conductive adhesives, which are being used increasingly both for environmental reasons and because of the need for higher temperature operating systems. Thus there exists a need to accurately evaluate design trade-offs arising due to these failures in order to increase reliability and drive design improvements. A PC-based CAD tool for the assessment of the reliability of PBGA interconnects is presented. This tool facilitates the use of physics-of-failure methodology in design for reliability, virtual qualification and the selection of accelerated test conditions. The tool assesses candidate and existing package designs for reliability in many different environments using a database of fully validated physics-of-failure models. These models calculate times-to-failure for the fundamental mechanisms which cause failure of area array packages housing both bipolar and CMOS based systems. Particular focus is placed on the use of this tool for analyzing the reliability of area array solder joint interconnects, including those made with lead-free solders and conductive adhesives, and on conductive filament formation between the traces in a plastic ball grid array. The addition of the appropriate material properties for high temperature, fatigue resistant, lead-free solders to the materials database, the development of a package designer for PBGA designs, and the incorporation of failure mechanism models for flip chip solder fatigue, PBGA solder joint shear and tensile fatigue, and PBGA conductive filament formation will be discussed. The ability to use this tool to conduct assessments of the susceptibility of PBGAs to non-interconnect failure mechanisms is an added advantage as it permits a determination of the relative importance of interconnect failure as a failure mode.
最近，塑料球栅阵列(PBGA)在高引脚数应用中获得了广泛的认可，作为细间距引线封装(如塑料四平面封装(PQFP))的低成本替代品。导致其使用的主要因素包括低成本，高I/O密度，占地面积小，以及相对于pqfp具有优越的电气和热性能的潜力[Houghton 1993;Freyman and Pennisi, 1991]。然而，对互连可靠性的担忧仍然存在，特别是对于使用新型焊料或导电粘合剂连接的系统，由于环境原因和对更高温度操作系统的需求，这些系统的使用越来越多。因此，有必要准确地评估由于这些故障而产生的设计权衡，以提高可靠性并推动设计改进。提出了一种基于pc机的PBGA互连可靠性评估CAD工具。该工具有助于在可靠性设计、虚拟鉴定和加速测试条件选择中使用失效物理方法。该工具使用经过充分验证的失效物理模型数据库，评估候选和现有封装设计在许多不同环境中的可靠性。这些模型计算了导致双极和CMOS系统的区域阵列封装失效的基本机制的失效时间。特别关注的是使用该工具来分析区域阵列焊点互连的可靠性，包括那些由无铅焊料和导电粘合剂制成的，以及塑料球网格阵列中走线之间的导电丝形成。将在材料数据库中添加适合高温、耐疲劳、无铅焊料的材料特性，开发PBGA设计的封装设计器，并将倒装焊料疲劳、PBGA焊点剪切和拉伸疲劳以及PBGA导电丝形成的失效机制模型纳入其中。使用该工具评估pbga对非互连失效机制的敏感性是一个额外的优势，因为它允许确定互连失效作为失效模式的相对重要性。
{"title":"Reliability Assessment of BGA Interconnects With CADMP-II","authors":"F. McCluskey, A. Govind, D. Beaudet","doi":"10.1115/imece1996-0895","DOIUrl":"https://doi.org/10.1115/imece1996-0895","url":null,"abstract":"\u0000 Recently the plastic ball grid array (PBGA) has been gaining industry-wide acceptance in high pin count applications as a low-cost alternative to fine-pitch leaded packages such as the plastic quad flat pack (PQFP). The main factors leading to its use include low cost, high I/O density, a small footprint, and the potential for superior electrical and thermal performance with respect to PQFPs [Houghton 1993; Freyman and Pennisi, 1991]. However, concerns about interconnect reliability remain, particularly for systems to be joined with novel solders or conductive adhesives, which are being used increasingly both for environmental reasons and because of the need for higher temperature operating systems. Thus there exists a need to accurately evaluate design trade-offs arising due to these failures in order to increase reliability and drive design improvements.\u0000 A PC-based CAD tool for the assessment of the reliability of PBGA interconnects is presented. This tool facilitates the use of physics-of-failure methodology in design for reliability, virtual qualification and the selection of accelerated test conditions. The tool assesses candidate and existing package designs for reliability in many different environments using a database of fully validated physics-of-failure models. These models calculate times-to-failure for the fundamental mechanisms which cause failure of area array packages housing both bipolar and CMOS based systems. Particular focus is placed on the use of this tool for analyzing the reliability of area array solder joint interconnects, including those made with lead-free solders and conductive adhesives, and on conductive filament formation between the traces in a plastic ball grid array. The addition of the appropriate material properties for high temperature, fatigue resistant, lead-free solders to the materials database, the development of a package designer for PBGA designs, and the incorporation of failure mechanism models for flip chip solder fatigue, PBGA solder joint shear and tensile fatigue, and PBGA conductive filament formation will be discussed. The ability to use this tool to conduct assessments of the susceptibility of PBGAs to non-interconnect failure mechanisms is an added advantage as it permits a determination of the relative importance of interconnect failure as a failure mode.","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130631176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this research, a vibration analysis using finite element method with specific application to CHIP, LCP socket and PCB packaging are studied. The sensitivity of the design and material parameters of the whole CPU connector system is studied by two different approaches. A coarse finite element model is established to investigate the effects of vibration modes of the boundary condition parameters, and a detailed finite element model is adopted to evaluate the influence of the different types of boundary constrains to the whole system.
{"title":"Finite Element Vibration Analysis for Zero Inserting Force Socket","authors":"K. Chiang, Hsueh-Horng Fu","doi":"10.1115/imece1996-0893","DOIUrl":"https://doi.org/10.1115/imece1996-0893","url":null,"abstract":"\u0000 In this research, a vibration analysis using finite element method with specific application to CHIP, LCP socket and PCB packaging are studied. The sensitivity of the design and material parameters of the whole CPU connector system is studied by two different approaches. A coarse finite element model is established to investigate the effects of vibration modes of the boundary condition parameters, and a detailed finite element model is adopted to evaluate the influence of the different types of boundary constrains to the whole system.","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123397338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The results of simulation, and material performance testing of anisotropic conductive polymers for flip chip interconnects necessary for power MMICs are reported. The flip chip interconnects are designed to connect source metallization to a common ground plane, and also to provide for heat sinking paths to a ceramic substrate. Finite Element Analysis results are also reported simulating the thermal mechanical stresses present during high frequency operation at a frequency of 1–10 GHz.
{"title":"Polymer Based Flip Chip Interconnect Materials for Monolithic Integrated Circuits","authors":"N. Strifas, A. Christou","doi":"10.1115/imece1996-0897","DOIUrl":"https://doi.org/10.1115/imece1996-0897","url":null,"abstract":"\u0000 The results of simulation, and material performance testing of anisotropic conductive polymers for flip chip interconnects necessary for power MMICs are reported. The flip chip interconnects are designed to connect source metallization to a common ground plane, and also to provide for heat sinking paths to a ceramic substrate. Finite Element Analysis results are also reported simulating the thermal mechanical stresses present during high frequency operation at a frequency of 1–10 GHz.","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128626320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a simulation method for vibration sweep tests of components and interconnects. The paper introduces the computational method to determine cumulative fatigue damage as a function of the stress-frequency response, the sweep rate and the testing time, demonstrates the “local stress-strain” approach to predict the non-linear (elastic-plastic) stress at the potential failure sites through the linear dynamic finite element analysis in the frequency domain. As an application example, the analysis procedure and computational results for the aluminum wire-bonding between a silicon chip and printed wiring board are presented.
{"title":"CAE Durability Simulation of Vibration Sweep Tests","authors":"J. M. Hu, G. Garfinkel","doi":"10.1115/imece1996-0889","DOIUrl":"https://doi.org/10.1115/imece1996-0889","url":null,"abstract":"\u0000 This paper presents a simulation method for vibration sweep tests of components and interconnects. The paper introduces the computational method to determine cumulative fatigue damage as a function of the stress-frequency response, the sweep rate and the testing time, demonstrates the “local stress-strain” approach to predict the non-linear (elastic-plastic) stress at the potential failure sites through the linear dynamic finite element analysis in the frequency domain. As an application example, the analysis procedure and computational results for the aluminum wire-bonding between a silicon chip and printed wiring board are presented.","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115367736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Pan, H. D. Blair, D. Mitlin, G. M. Crosbie, J. Nicholson, J. Hangas
One of the essential thick film materials on the hybrid circuit is the conductor which performs as an interconnection between discrete components. However, metallurgical reaction between the conductor and solder during the soldering or thermal aging/cycling may cause electrical failure and/or loss of adhesive strength due to the reaction of Ag/Pd with Sn and subsequent intermetallics formed. A step soldering process, which applies a high-Pb solder layer over the conductor layer before the eutectic or near-eutectic Sn-Pb solder is applied, has been shown to prevent contact between the conductor and Sn in the solder, as long as the high-Pb layer does not dissolve into the low-Pb layer. Experiments were carried out to quantify the isothermal interdiffusion reaction rate and the interface displacement between the 88Pb-10Sn-2Ag and the eutectic 63Sn-37Pb solder layers between 195 and 235°C. The results were analyzed by the methodology developed by Lommel and Chalmers (1959) which was based on Nernst-Brunner theory of dissolution (Moelwyn-Hughes, 1947). The displacement of the interface follows an Arrhenius relationship with an activation energy of 98 KJ/mole, which is close to the activation energy of solid Sn diffusion into Pb. A process window was constructed to show that temperature is a more sensitive parameter influencing the reaction rate than time. A mathematical model was applied to predict the interfacial displacement during the reflow process and was found to correlate well with experimental results.
{"title":"Step Soldering Factors Affecting the Reliability of Ag-Pd Thick Film Conductor Pads","authors":"T. Pan, H. D. Blair, D. Mitlin, G. M. Crosbie, J. Nicholson, J. Hangas","doi":"10.1115/imece1996-0898","DOIUrl":"https://doi.org/10.1115/imece1996-0898","url":null,"abstract":"\u0000 One of the essential thick film materials on the hybrid circuit is the conductor which performs as an interconnection between discrete components. However, metallurgical reaction between the conductor and solder during the soldering or thermal aging/cycling may cause electrical failure and/or loss of adhesive strength due to the reaction of Ag/Pd with Sn and subsequent intermetallics formed. A step soldering process, which applies a high-Pb solder layer over the conductor layer before the eutectic or near-eutectic Sn-Pb solder is applied, has been shown to prevent contact between the conductor and Sn in the solder, as long as the high-Pb layer does not dissolve into the low-Pb layer. Experiments were carried out to quantify the isothermal interdiffusion reaction rate and the interface displacement between the 88Pb-10Sn-2Ag and the eutectic 63Sn-37Pb solder layers between 195 and 235°C. The results were analyzed by the methodology developed by Lommel and Chalmers (1959) which was based on Nernst-Brunner theory of dissolution (Moelwyn-Hughes, 1947). The displacement of the interface follows an Arrhenius relationship with an activation energy of 98 KJ/mole, which is close to the activation energy of solid Sn diffusion into Pb. A process window was constructed to show that temperature is a more sensitive parameter influencing the reaction rate than time. A mathematical model was applied to predict the interfacial displacement during the reflow process and was found to correlate well with experimental results.","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114666480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The general trend in the automotive electronics industry dictates increased power dissipation on ever shrinking packaged components, giving rise to greater power density. Flip chips on ceramics have long been used for favorable thermal management and reliability. With the drive to cut costs, printed circuit boards are replacing ceramics for many applications, which requires different thermal management techniques. This paper presents some of the techniques that can be used to achieve comparable thermal performance on printed circuit boards.
{"title":"Thermal Management of Flip Chips on Printed Circuit Boards","authors":"Ron Zhang, D. Peugh, Bruce P Myers","doi":"10.1115/imece1996-0892","DOIUrl":"https://doi.org/10.1115/imece1996-0892","url":null,"abstract":"\u0000 The general trend in the automotive electronics industry dictates increased power dissipation on ever shrinking packaged components, giving rise to greater power density. Flip chips on ceramics have long been used for favorable thermal management and reliability. With the drive to cut costs, printed circuit boards are replacing ceramics for many applications, which requires different thermal management techniques. This paper presents some of the techniques that can be used to achieve comparable thermal performance on printed circuit boards.","PeriodicalId":375055,"journal":{"name":"Sensing, Modeling and Simulation in Emerging Electronic Packaging","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126787012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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