Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404314
Kwen-Siong Chong, M. Barangi, Jaeyoung Kim, J. Chang, P. Mazumder
An ultra-low power sub-threshold Finite Impulse Response (FIR) filter bank for hearing aid applications is demonstrated in 65nm CMOS technology. The system has a 2kb Static Random Access Memory (SRAM) interface optimized for sub-threshold operation. The system operates at 0.3V sub-threshold regime and consumes 10.4 μW at 0.96MHz clock frequency which corresponds to merely 0.6nJ per FIR operation.
{"title":"Ultra low-power filter bank for hearing aid speech processor","authors":"Kwen-Siong Chong, M. Barangi, Jaeyoung Kim, J. Chang, P. Mazumder","doi":"10.1109/SUBVT.2012.6404314","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404314","url":null,"abstract":"An ultra-low power sub-threshold Finite Impulse Response (FIR) filter bank for hearing aid applications is demonstrated in 65nm CMOS technology. The system has a 2kb Static Random Access Memory (SRAM) interface optimized for sub-threshold operation. The system operates at 0.3V sub-threshold regime and consumes 10.4 μW at 0.96MHz clock frequency which corresponds to merely 0.6nJ per FIR operation.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134041308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404304
N. Mazloum, J. Rodrigues, O. Edfors
In sensor network applications, the use of duty-cycled ultra-low power wake-up receivers can significantly reduce overall power consumption. An important complement to previous investigations is to show that low-power wake-up receivers with good enough detection performance can be realized in hardware. In this paper we address this very issue by presenting the design, implementation, and sub-VT characterization of a digital back-end for such an ultra-low power WRx.
{"title":"Sub-VT design of a wake-up receiver back-end in 65 nm CMOS","authors":"N. Mazloum, J. Rodrigues, O. Edfors","doi":"10.1109/SUBVT.2012.6404304","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404304","url":null,"abstract":"In sensor network applications, the use of duty-cycled ultra-low power wake-up receivers can significantly reduce overall power consumption. An important complement to previous investigations is to show that low-power wake-up receivers with good enough detection performance can be realized in hardware. In this paper we address this very issue by presenting the design, implementation, and sub-VT characterization of a digital back-end for such an ultra-low power WRx.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132382614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404325
D. Blaauw, D. Sylvester, Yoonmyung Lee, Inhee Lee, S. Bang, Inhee Lee, Yejoong Kim, Gyouho Kim, H. Ghead
Summary form only given. Moore's Law has received much attention over the last decades. However, the lesser known “Bell's law” has potentially had equal impact on the transformation of electronic systems. Bell's law dictates that every decade the size of a complete computing system shrinks in volume by 100x while the number of such devices per person increases. Bell's law has driven the transformation of gigantic mainframes in the 1960s to small handheld devices in the new millenium. It is generally held, that the next class of computing systems on the trajectory of Bell's law are miniature sensing systems that will instrument numerous aspects of our daily lives. In particular, we focus on millimeter sized systems which, being nearly invisible, will open up a host of new application areas in computing such as medical implantable devices for monitoring vital signs and disease, surveillance and entry detection, and environmental monitoring.
{"title":"From digital processors to analog building blocks: Enabling new applications through ultra-low voltage design","authors":"D. Blaauw, D. Sylvester, Yoonmyung Lee, Inhee Lee, S. Bang, Inhee Lee, Yejoong Kim, Gyouho Kim, H. Ghead","doi":"10.1109/SUBVT.2012.6404325","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404325","url":null,"abstract":"Summary form only given. Moore's Law has received much attention over the last decades. However, the lesser known “Bell's law” has potentially had equal impact on the transformation of electronic systems. Bell's law dictates that every decade the size of a complete computing system shrinks in volume by 100x while the number of such devices per person increases. Bell's law has driven the transformation of gigantic mainframes in the 1960s to small handheld devices in the new millenium. It is generally held, that the next class of computing systems on the trajectory of Bell's law are miniature sensing systems that will instrument numerous aspects of our daily lives. In particular, we focus on millimeter sized systems which, being nearly invisible, will open up a host of new application areas in computing such as medical implantable devices for monitoring vital signs and disease, surveillance and entry detection, and environmental monitoring.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129029159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404316
J. Ledford, P. Gadfort, P. Franzon
Current RFID systems rely on the RF transciever to transmit information and convert RF power to DC to operate any integrated digital circuits. Research investigating the application of RF signals directly on digital CMOS circuits without RF-DC conversion is an emerging area for RFID technologies. One crucial digital circuit for most RFID systems is memory, needed for storing operational instructions and sampled data. An in-depth study and comparison of subthreshold SRAM bitcells has been conducted to analyze how such memories will function in a subthreshold RF-only regime without the need for RF-DC conversion. Several SRAM cells were chosen for conversion into the RF-only family and measured against several metrics, including highest performance at lowest operating voltage, power consumption, and static noise margins (SNM). Including RF supply transistors, an 18-T subthreshold RF-only bitcell is proposed, capable of operating at a data rate of 100 kHz at VRF of 200mVRMS.
{"title":"An analysis of subthreshold SRAM bitcells for operation in low power RF-only technologies","authors":"J. Ledford, P. Gadfort, P. Franzon","doi":"10.1109/SUBVT.2012.6404316","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404316","url":null,"abstract":"Current RFID systems rely on the RF transciever to transmit information and convert RF power to DC to operate any integrated digital circuits. Research investigating the application of RF signals directly on digital CMOS circuits without RF-DC conversion is an emerging area for RFID technologies. One crucial digital circuit for most RFID systems is memory, needed for storing operational instructions and sampled data. An in-depth study and comparison of subthreshold SRAM bitcells has been conducted to analyze how such memories will function in a subthreshold RF-only regime without the need for RF-DC conversion. Several SRAM cells were chosen for conversion into the RF-only family and measured against several metrics, including highest performance at lowest operating voltage, power consumption, and static noise margins (SNM). Including RF supply transistors, an 18-T subthreshold RF-only bitcell is proposed, capable of operating at a data rate of 100 kHz at VRF of 200mVRMS.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125461719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SubVT.2012.6404309
F. Botman, D. Bol, J. Legat
As electronics becomes more mobile, and its uses and applications more widespread, there is an increased need for a low-power yet powerful system to perform a multitude of varied of tasks. Downscaling the supply voltage improves a device's power usage, but also severely impacts the overall performance. A careful balance must therefore be struck between the needs of the application in terms of processing speed versus power usage.
{"title":"Data-dependent operation speed-up through automatically-inserted signal transition detectors for ultra-low voltage logic circuits","authors":"F. Botman, D. Bol, J. Legat","doi":"10.1109/SubVT.2012.6404309","DOIUrl":"https://doi.org/10.1109/SubVT.2012.6404309","url":null,"abstract":"As electronics becomes more mobile, and its uses and applications more widespread, there is an increased need for a low-power yet powerful system to perform a multitude of varied of tasks. Downscaling the supply voltage improves a device's power usage, but also severely impacts the overall performance. A careful balance must therefore be struck between the needs of the application in terms of processing speed versus power usage.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116983026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404319
P. Grossmann, M. Leeser, M. Onabajo
This paper presents a pair of field programmable gate array (FPGA) test chips optimized for subthreshold operation to maximize energy efficiency. Both chips were fabricated in the IBM 0.18 μm silicon-on-insulator (SOI) process using the same FPGA architecture; one making use of conventional static CMOS multiplexers and one using dynamic threshold MOS (DTMOS) multiplexers. Reliable subthreshold operation is achieved for both test chips by replacing conventional SRAM with variation-tolerant interruptible latches. For the chip with conventional multiplexers, testing across eleven dice showed an average minimum operating voltage of 300 mV. A 43X reduction in power delay product (PDP) was seen compared to 1.5V operation. For the DTMOS chip, testing across four dice showed an average minimum operating voltage of 260 mV. The test results show that the DTMOS chip is more reliable at sub-300 mV, consistent with simulations. Minimum energy analysis of both test chips suggests that the minimum energy point for the FPGA occurs at subthreshold voltages.
{"title":"Characterization of a single-supply subthreshold FPGA","authors":"P. Grossmann, M. Leeser, M. Onabajo","doi":"10.1109/SUBVT.2012.6404319","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404319","url":null,"abstract":"This paper presents a pair of field programmable gate array (FPGA) test chips optimized for subthreshold operation to maximize energy efficiency. Both chips were fabricated in the IBM 0.18 μm silicon-on-insulator (SOI) process using the same FPGA architecture; one making use of conventional static CMOS multiplexers and one using dynamic threshold MOS (DTMOS) multiplexers. Reliable subthreshold operation is achieved for both test chips by replacing conventional SRAM with variation-tolerant interruptible latches. For the chip with conventional multiplexers, testing across eleven dice showed an average minimum operating voltage of 300 mV. A 43X reduction in power delay product (PDP) was seen compared to 1.5V operation. For the DTMOS chip, testing across four dice showed an average minimum operating voltage of 260 mV. The test results show that the DTMOS chip is more reliable at sub-300 mV, consistent with simulations. Minimum energy analysis of both test chips suggests that the minimum energy point for the FPGA occurs at subthreshold voltages.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133147051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404318
P. Meinerzhagen, A. Teman, A. Mordakhay, A. Burg, A. Fish
Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. For the first time, this paper presents a gain-cell array which is fully functional in the sub-VT regime and achieves a data retention time that is more than 104 times higher than the access time. Monte Carlos simulations show that the 2 kb gain-cell array, implemented in a mature 0.18μm CMOS node and supplied with a sub-VT voltage of 400mV, exhibits robust write and read operations at 500 kHz under parametric variations and has over 99% availibilty for read and write access.
{"title":"A sub-VT 2T gain-cell memory for biomedical applications","authors":"P. Meinerzhagen, A. Teman, A. Mordakhay, A. Burg, A. Fish","doi":"10.1109/SUBVT.2012.6404318","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404318","url":null,"abstract":"Biomedical systems often require several kb of embedded memory and are typically operated in the subthreshold (sub-VT) domain for good energy-efficiency. Embedded memories and their leakage current can easily dominate the overall silicon area and the total power consumption, respectively. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. For the first time, this paper presents a gain-cell array which is fully functional in the sub-VT regime and achieves a data retention time that is more than 104 times higher than the access time. Monte Carlos simulations show that the 2 kb gain-cell array, implemented in a mature 0.18μm CMOS node and supplied with a sub-VT voltage of 400mV, exhibits robust write and read operations at 500 kHz under parametric variations and has over 99% availibilty for read and write access.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404305
B. Mohammadi, S. M. Y. Sherazi, J. Rodrigues
This paper presents a novel method to improve the performance of sub-threshold (sub-VT) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.
{"title":"Sizing of dual-VT gates for sub-VT circuits","authors":"B. Mohammadi, S. M. Y. Sherazi, J. Rodrigues","doi":"10.1109/SUBVT.2012.6404305","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404305","url":null,"abstract":"This paper presents a novel method to improve the performance of sub-threshold (sub-VT) gates in 65-nm CMOS technology. Faster transistors with a lower threshold voltage are introduced in the weaker network of a gate. It is shown that the employed method significantly enhances the reliability and performance of the gate, with an additive advantage of a lower area cost compared to traditional transistor sizing. Extensive Monte-Carlo simulations are carried out to verify the proposed optimization technique. The simulation results predict that the NAND3 and NOR3 testbench shows a 98% higher noise margin. Furthermore, the inverter and NAND3 gates show an speed improvement of 48% and 97%, respectively.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129206946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404302
P. Palakurthi, J. Martinez, E. MacDonald
For ultra low power applications, improved energy efficiency can be achieved by operating non-critical portions of the logic in the subthreshold region (VDD <; VTH) while performance-critical sections are maintained in the superthreshold region (VDD >; VTH). Signal interfacing from subthreshold to superthreshold levels is a significant challenge and requires a robust level shifter that operates across an extreme input-to-output voltage range. Beyond the challenges of translating signals between such disparate voltages, another concern is the increased sensitivity to radiation that results from the weakened drivers in the traditional level shifter feedback structure. This paper presents a novel rad-hard ultra-low-power level shifter that 1) is Single Event Upset (SEU) immune over a wide range of supply voltages due to a Dual Interlocked Storage Cell (DICE) feedback and 2) is optimized for translating signals from sub to superthreshold levels. Radiation hardness of the proposed design is captured as Qcrit - the amount of radiation-induced charge required to flip the output unintentionally. The proposed design provides SEU resilience at subthreshold voltage (0.45V) with 12x improvement in Qcrit values as simulated using 250 nm CMOS TSMC technology models.
{"title":"Radiation hardened level shifter for sub to superthreshold voltage translation","authors":"P. Palakurthi, J. Martinez, E. MacDonald","doi":"10.1109/SUBVT.2012.6404302","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404302","url":null,"abstract":"For ultra low power applications, improved energy efficiency can be achieved by operating non-critical portions of the logic in the subthreshold region (VDD <; VTH) while performance-critical sections are maintained in the superthreshold region (VDD >; VTH). Signal interfacing from subthreshold to superthreshold levels is a significant challenge and requires a robust level shifter that operates across an extreme input-to-output voltage range. Beyond the challenges of translating signals between such disparate voltages, another concern is the increased sensitivity to radiation that results from the weakened drivers in the traditional level shifter feedback structure. This paper presents a novel rad-hard ultra-low-power level shifter that 1) is Single Event Upset (SEU) immune over a wide range of supply voltages due to a Dual Interlocked Storage Cell (DICE) feedback and 2) is optimized for translating signals from sub to superthreshold levels. Radiation hardness of the proposed design is captured as Qcrit - the amount of radiation-induced charge required to flip the output unintentionally. The proposed design provides SEU resilience at subthreshold voltage (0.45V) with 12x improvement in Qcrit values as simulated using 250 nm CMOS TSMC technology models.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126387218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thanh Tran, A. Rothenbuhler, E. H. B. Smith, V. Saxena, K. Campbell
We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-simulation using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.
{"title":"Reconfigurable Threshold Logic Gates using memristive devices","authors":"Thanh Tran, A. Rothenbuhler, E. H. B. Smith, V. Saxena, K. Campbell","doi":"10.3390/JLPEA3020174","DOIUrl":"https://doi.org/10.3390/JLPEA3020174","url":null,"abstract":"We present our early design exploration of reconfigurable Threshold Logic Gates (TLG) implemented using Silver-chalcogenide memristive devices combined with CMOS circuits. A variety of linearly separable logic functions including AND, OR, NAND, NOR have been realized in a Matlab-Simulink/Cadence co-simulation using a single-layer TLG. The functionality can be changed between these operations by reprogramming the resistance of the memristive devices.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115154065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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