Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404310
Chen Xin, Xia Huan, Wu Nee, B. Na
Because the subthreshold current has an exponential relationship with the supply voltage and the threshold voltage (Vth), it leads to the delay changes exponentially with PVT. To mitigate the impacts caused by PVT variations, increasing the power supply voltage is a simple and effective method. In this paper, a power management control (PMC) scheme for ultra-low power SoCs is proposed. According to the different blocks, different delay detection circuits are inserted into the corresponding critical delay paths. To validate the proposed PMC scheme, a design example for subthreshold SRAM is implemented. The simulation results show that the proposed PMC scheme can mitigate the effects caused by PVT fluctuations upon the subthreshold SRAM circuit effectively at the minimum cost of the power.
{"title":"A power management control scheme for ultra-low power SoCs","authors":"Chen Xin, Xia Huan, Wu Nee, B. Na","doi":"10.1109/SUBVT.2012.6404310","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404310","url":null,"abstract":"Because the subthreshold current has an exponential relationship with the supply voltage and the threshold voltage (Vth), it leads to the delay changes exponentially with PVT. To mitigate the impacts caused by PVT variations, increasing the power supply voltage is a simple and effective method. In this paper, a power management control (PMC) scheme for ultra-low power SoCs is proposed. According to the different blocks, different delay detection circuits are inserted into the corresponding critical delay paths. To validate the proposed PMC scheme, a design example for subthreshold SRAM is implemented. The simulation results show that the proposed PMC scheme can mitigate the effects caused by PVT fluctuations upon the subthreshold SRAM circuit effectively at the minimum cost of the power.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121699729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404306
J. De Vos, D. Flandre, D. Bol
Ultra-low-voltage processors of highly duty-cycled applications such as wireless sensor nodes must support two modes of operation: active mode and sleep mode. Even in sleep mode some critical blocks such as retentive SRAM, timer and interrupt controller must remain powered-on. The DC/DC converter thus need to be able to supply ultra-low loads corresponding to sleep mode. In this paper, we propose a dual-mode switched-capacitor DC/DC converter to power such ultra-low-voltage processors with high efficiencies in both modes. It delivers a 0.3-0.4V output voltage from a 1-1.2V input source. The 0.12mm2 chip was manufactured in a 0.13μm CMOS technology. The efficiency reaches 74% with a 100 μW load and 63% with a 100nW load, corresponding to the processor active and sleep mode respectively. Adaptive body biasing and adaptive internal clock generation supplied by the output voltage allow the converter to correctly operate over a wide load range from 25nW to 125 μW, i.e. nearly 4 orders of magnitude.
{"title":"A dual-mode DC/DC converter for ultra-low-voltage microcontrollers","authors":"J. De Vos, D. Flandre, D. Bol","doi":"10.1109/SUBVT.2012.6404306","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404306","url":null,"abstract":"Ultra-low-voltage processors of highly duty-cycled applications such as wireless sensor nodes must support two modes of operation: active mode and sleep mode. Even in sleep mode some critical blocks such as retentive SRAM, timer and interrupt controller must remain powered-on. The DC/DC converter thus need to be able to supply ultra-low loads corresponding to sleep mode. In this paper, we propose a dual-mode switched-capacitor DC/DC converter to power such ultra-low-voltage processors with high efficiencies in both modes. It delivers a 0.3-0.4V output voltage from a 1-1.2V input source. The 0.12mm2 chip was manufactured in a 0.13μm CMOS technology. The efficiency reaches 74% with a 100 μW load and 63% with a 100nW load, corresponding to the processor active and sleep mode respectively. Adaptive body biasing and adaptive internal clock generation supplied by the output voltage allow the converter to correctly operate over a wide load range from 25nW to 125 μW, i.e. nearly 4 orders of magnitude.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"395 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123393716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404298
Tong Lin, Kwen-Siong Chong, J. Chang, B. Gwee, Wei Shu
Self-Adaptive VDD Scaling (SAVS) technique achieves power/energy reduction by dynamically scaling VDD for the prevailing conditions. However, when applied in sub-threshold (sub-Vt) region, robustness issues need to be addressed due to the severe delay uncertainty associated with sub-Vt Process, Voltage, and Temperature (PVT) variations. To ensure robustness for sub-Vt SAVS, we adopt the asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) approach. To address the usual power/energy overheads associated with conventional async QDI systems, we further propose a hardware-simplified version of QDI (`pseudo-QDI') with an easy-to-met implicit timing. Prototype ICs embodying async filter banks realized in both the conventional QDI and pseudo-QDI have demonstrated the extreme robustness of the proposed approach against sub-Vt PVT variations. Measurement results further suggest pseudo-QDI's energy (~40% lower) and area (~1.34× smaller) advantages as compared to its conventional QDI counterpart.
{"title":"A robust asynchronous approach for realizing ultra-low power digital Self-Adaptive VDD Scaling system","authors":"Tong Lin, Kwen-Siong Chong, J. Chang, B. Gwee, Wei Shu","doi":"10.1109/SUBVT.2012.6404298","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404298","url":null,"abstract":"Self-Adaptive VDD Scaling (SAVS) technique achieves power/energy reduction by dynamically scaling VDD for the prevailing conditions. However, when applied in sub-threshold (sub-Vt) region, robustness issues need to be addressed due to the severe delay uncertainty associated with sub-Vt Process, Voltage, and Temperature (PVT) variations. To ensure robustness for sub-Vt SAVS, we adopt the asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) approach. To address the usual power/energy overheads associated with conventional async QDI systems, we further propose a hardware-simplified version of QDI (`pseudo-QDI') with an easy-to-met implicit timing. Prototype ICs embodying async filter banks realized in both the conventional QDI and pseudo-QDI have demonstrated the extreme robustness of the proposed approach against sub-Vt PVT variations. Measurement results further suggest pseudo-QDI's energy (~40% lower) and area (~1.34× smaller) advantages as compared to its conventional QDI counterpart.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131249844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404327
J. M. Barcak, H. Partal
This paper covers the design, implementation and usage of a matched multiband microstrip antenna intended to collect RF energy efficiently in commonly used portions of the selected cellular frequency spectrum including the ISM bands. Multistage Schottky rectifier antenna (rectenna) array circuit is proposed for high energy conversion efficiency to improve battery life and portability. Design details for the multiband microstrip antenna prototype is presented.
{"title":"Efficient RF energy harvesting by using multiband microstrip antenna arrays with multistage rectifiers","authors":"J. M. Barcak, H. Partal","doi":"10.1109/SUBVT.2012.6404327","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404327","url":null,"abstract":"This paper covers the design, implementation and usage of a matched multiband microstrip antenna intended to collect RF energy efficiently in commonly used portions of the selected cellular frequency spectrum including the ISM bands. Multistage Schottky rectifier antenna (rectenna) array circuit is proposed for high energy conversion efficiency to improve battery life and portability. Design details for the multiband microstrip antenna prototype is presented.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114385705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404311
A. Arthurs, J. Di
Ultra-low voltage electronics is a subject that introduces unique issues. Problems such as process variation adversely affect digital electronics at ultra-low voltages. Signal integrity and systematic timing strongly influence low-voltage digital designs because of the low static noise margin. Candidate solutions include Schmitt-trigger gate design and asynchronous paradigm such as the NULL Convention Logic. Four gate libraries are constructed for comparison between static CMOS and Schmitt-trigger gate design, and between synchronous and asynchronous logic gates. A small test circuit is implemented to measure success rate, active energy, leakage power, and threshold under process variation. Results show that process variation strongly affects ultra-low voltage electronics and that Schmitt-trigger gate design and NULL Convention Logic are effective solutions for deep subthreshold operation.
{"title":"Analysis of ultra-low voltage digital circuits over process variations","authors":"A. Arthurs, J. Di","doi":"10.1109/SUBVT.2012.6404311","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404311","url":null,"abstract":"Ultra-low voltage electronics is a subject that introduces unique issues. Problems such as process variation adversely affect digital electronics at ultra-low voltages. Signal integrity and systematic timing strongly influence low-voltage digital designs because of the low static noise margin. Candidate solutions include Schmitt-trigger gate design and asynchronous paradigm such as the NULL Convention Logic. Four gate libraries are constructed for comparison between static CMOS and Schmitt-trigger gate design, and between synchronous and asynchronous logic gates. A small test circuit is implemented to measure success rate, active energy, leakage power, and threshold under process variation. Results show that process variation strongly affects ultra-low voltage electronics and that Schmitt-trigger gate design and NULL Convention Logic are effective solutions for deep subthreshold operation.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"83 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120893662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404321
P. Gadfort, P. Franzon
This paper describes an analog-to-digital converter (ADC) capable of operating in a RF-only circuit topology. A major limitation to direct RF-powered sensors are the lack of analog circuits. The proposed architecture is comprised of a cross-coupled pair of inverters, which act as the comparator for the ADC. This setup has been simulated in IBMs 0.13 μm bulk CMOS process for a 3 bit analog-to-digital converter (ADC). At a RF supply voltage of 300 mVRMS and frequency 13.57 MHz, the ADC has a resolution of 20 mV and can resolve voltages ranging from -80 mV to 80 mV, and at a frequency of 915 MHz the ADC can resolve voltages ranging from -140 mV to 140 mV. In order to optimize the ADC operation, the sampling time has been adjusted to one-third of the evaluation time, to give the comparator enough time to complete the amplification.
{"title":"Near threshold RF-only analog to digital converter","authors":"P. Gadfort, P. Franzon","doi":"10.1109/SUBVT.2012.6404321","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404321","url":null,"abstract":"This paper describes an analog-to-digital converter (ADC) capable of operating in a RF-only circuit topology. A major limitation to direct RF-powered sensors are the lack of analog circuits. The proposed architecture is comprised of a cross-coupled pair of inverters, which act as the comparator for the ADC. This setup has been simulated in IBMs 0.13 μm bulk CMOS process for a 3 bit analog-to-digital converter (ADC). At a RF supply voltage of 300 mVRMS and frequency 13.57 MHz, the ADC has a resolution of 20 mV and can resolve voltages ranging from -80 mV to 80 mV, and at a frequency of 915 MHz the ADC can resolve voltages ranging from -140 mV to 140 mV. In order to optimize the ADC operation, the sampling time has been adjusted to one-third of the evaluation time, to give the comparator enough time to complete the amplification.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122838762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404320
L. H. C. Ferreira, S. Sonkusale
In this paper a simple and efficient way to enhance the transconductance Gm for bulk-driven sub-threshold differential pair in nanometer CMOS process is presented. This approach is based on a type of positive feedback source degeneration, which does not depend on geometry parameters or biasing voltages, and leads to improved values for the DC gain and the unity gain frequency, without increasing power consumption or changing other features. Despite of possible differential pair output resistance variation, the DC gain and the unity gain frequency of weak inversion differential pair can be increased by (n + 1)/(n - 1) times (e.g., 13.72 times in an 130-nm IBM CMOS process), a factor that improves with scaling while many other device characteristics degrade.
{"title":"Gm enhancement for bulk-driven sub-threshold differential pair in nanometer CMOS process","authors":"L. H. C. Ferreira, S. Sonkusale","doi":"10.1109/SUBVT.2012.6404320","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404320","url":null,"abstract":"In this paper a simple and efficient way to enhance the transconductance Gm for bulk-driven sub-threshold differential pair in nanometer CMOS process is presented. This approach is based on a type of positive feedback source degeneration, which does not depend on geometry parameters or biasing voltages, and leads to improved values for the DC gain and the unity gain frequency, without increasing power consumption or changing other features. Despite of possible differential pair output resistance variation, the DC gain and the unity gain frequency of weak inversion differential pair can be increased by (n + 1)/(n - 1) times (e.g., 13.72 times in an 130-nm IBM CMOS process), a factor that improves with scaling while many other device characteristics degrade.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"58 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121009130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404300
P. Beshay, B. Calhoun, J. Ryan
Voltage offset in SRAM sense amplifiers due to variability causes increased power consumption and degraded performance. The effect is more dominant in the sub-threshold region. In this paper, we propose a circuit that reduces the sense amp offset using an auto-zeroing scheme with automatic temperature, voltage, and aging tracking.
{"title":"Sub-threshold sense amplifier compensation using auto-zeroing circuitry","authors":"P. Beshay, B. Calhoun, J. Ryan","doi":"10.1109/SUBVT.2012.6404300","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404300","url":null,"abstract":"Voltage offset in SRAM sense amplifiers due to variability causes increased power consumption and degraded performance. The effect is more dominant in the sub-threshold region. In this paper, we propose a circuit that reduces the sense amp offset using an auto-zeroing scheme with automatic temperature, voltage, and aging tracking.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126711866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-01DOI: 10.1109/SUBVT.2012.6404317
N. Roberts, D. Wentzloff
A 98nW receiver with a 23nW active rectifier RF front-end biased in deep subthreshold near the saturation/linear boundary is presented. An on-chip voltage reference and 28nW hysteretic comparator are also designed using subthreshold techniques. The receiver can demodulate an OOK signal at 100kbps with a sensitivity of -41dBm and all processing for process and mismatch is handled on-chip [1]. The ultra-low power receiver is used for wireless sensor node applications, specifically for nodes that are to be worn on the body.
{"title":"915MHz ultra low power receiver using sub-Vt active rectifiers","authors":"N. Roberts, D. Wentzloff","doi":"10.1109/SUBVT.2012.6404317","DOIUrl":"https://doi.org/10.1109/SUBVT.2012.6404317","url":null,"abstract":"A 98nW receiver with a 23nW active rectifier RF front-end biased in deep subthreshold near the saturation/linear boundary is presented. An on-chip voltage reference and 28nW hysteretic comparator are also designed using subthreshold techniques. The receiver can demodulate an OOK signal at 100kbps with a sensitivity of -41dBm and all processing for process and mismatch is handled on-chip [1]. The ultra-low power receiver is used for wireless sensor node applications, specifically for nodes that are to be worn on the body.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129875339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：