Pub Date : 2015-10-12DOI: 10.1109/DFT.2015.7315131
J. Backer, D. Hély, R. Karri
The prevalent use of systems-on-chip (SoCs) makes them prime targets for software attacks. Proposed security countermeasures monitor software execution in real-time, but are impractical, and require impractical changes to the internal logic of intellectual property (IP) cores. We leverage the software observability provided by the readily available SoC debug architecture to detect attacks without modifying IP cores. We add hardware components to configure the debug architecture for security monitoring, to store a golden software execution model, and to notify a trusted kernel process when an attack is detected. Our evaluations show that the additions do not impact runtime software execution, and incur 9% area and power overheads on a low-cost processor core.
{"title":"On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks","authors":"J. Backer, D. Hély, R. Karri","doi":"10.1109/DFT.2015.7315131","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315131","url":null,"abstract":"The prevalent use of systems-on-chip (SoCs) makes them prime targets for software attacks. Proposed security countermeasures monitor software execution in real-time, but are impractical, and require impractical changes to the internal logic of intellectual property (IP) cores. We leverage the software observability provided by the readily available SoC debug architecture to detect attacks without modifying IP cores. We add hardware components to configure the debug architecture for security monitoring, to store a golden software execution model, and to notify a trusted kernel process when an attack is detected. Our evaluations show that the additions do not impact runtime software execution, and incur 9% area and power overheads on a low-cost processor core.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124354135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315159
Zhixi Yang, Jie Han, F. Lombardi
Approximate circuit design is an innovative paradigm for error-resilient image and signal processing applications. Multiplication is often a fundamental function for many of these applications. In this paper, three approximate compressors are proposed with an accuracy constraint for the partial product reduction (PPR) in a multiplier. Both approximation and truncation are considered in the approximate multiplier design. An image sharpening algorithm is then investigated as an application of the proposed multiplier designs. Extensive simulation results show that the proposed designs achieve significant reductions in area and power while achieving a high signal-to-noise ratio (SNR > 35 dB), compared to their exact counterparts as well as other approximate multipliers.
{"title":"Approximate compressors for error-resilient multiplier design","authors":"Zhixi Yang, Jie Han, F. Lombardi","doi":"10.1109/DFT.2015.7315159","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315159","url":null,"abstract":"Approximate circuit design is an innovative paradigm for error-resilient image and signal processing applications. Multiplication is often a fundamental function for many of these applications. In this paper, three approximate compressors are proposed with an accuracy constraint for the partial product reduction (PPR) in a multiplier. Both approximation and truncation are considered in the approximate multiplier design. An image sharpening algorithm is then investigated as an application of the proposed multiplier designs. Extensive simulation results show that the proposed designs achieve significant reductions in area and power while achieving a high signal-to-noise ratio (SNR > 35 dB), compared to their exact counterparts as well as other approximate multipliers.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115479709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315140
P. Reviriego, S. Pontarelli, J. A. Maestro, M. Ottavi
Bloom filters are used in many computing and networking applications where they provide a simple method to test if an element is present in a set. In some of those systems, reliability is a major concern and therefore the Bloom filters should be protected to ensure that errors do not affect the system behavior. One of the most common type of errors in electronic implementations of Bloom filters are radiation induced soft errors. Soft errors can corrupt the contents of a Bloom filter causing false positives and false negatives. Error Correction Codes (ECCs) can be used to protect the Bloom filter so that for example single bit errors are detected and corrected. However, the use of ECCs impacts the implementation area, power and delay. In this paper, a method to efficiently protect the contents of a Bloom filter is presented. The scheme exploits the different effects at the system level of false positives and false negatives to achieve effective error protection at lower cost than that of a traditional ECC. To illustrate the benefits of the proposed method, a case study is presented where the proposed implementation is compared with the use of a traditional Hamming ECC.
{"title":"A method to protect Bloom filters from soft errors","authors":"P. Reviriego, S. Pontarelli, J. A. Maestro, M. Ottavi","doi":"10.1109/DFT.2015.7315140","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315140","url":null,"abstract":"Bloom filters are used in many computing and networking applications where they provide a simple method to test if an element is present in a set. In some of those systems, reliability is a major concern and therefore the Bloom filters should be protected to ensure that errors do not affect the system behavior. One of the most common type of errors in electronic implementations of Bloom filters are radiation induced soft errors. Soft errors can corrupt the contents of a Bloom filter causing false positives and false negatives. Error Correction Codes (ECCs) can be used to protect the Bloom filter so that for example single bit errors are detected and corrected. However, the use of ECCs impacts the implementation area, power and delay. In this paper, a method to efficiently protect the contents of a Bloom filter is presented. The scheme exploits the different effects at the system level of false positives and false negatives to achieve effective error protection at lower cost than that of a traditional ECC. To illustrate the benefits of the proposed method, a case study is presented where the proposed implementation is compared with the use of a traditional Hamming ECC.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123047048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315155
Tengteng Zhang, D. Walker
Compaction and compression are commonly used to minimize test data volume and test application time. Both techniques can greatly affect power supply noise (PSN) during test, as these techniques take advantage of the fact that test patterns have low care-bit density. However, there is little prior work studying how compression affects PSN. In this work, embedded deterministic test (EDT) and Illinois Scan patterns are generated with and without compaction. Our previous PSN control algorithm is extended to incorporate the compression constraints and applied to these patterns. The experimental results show that with the PSN control algorithm, EDT lowers the maximal PSN by 24.15% and Illinois Scan lowers it by 2.77% on un-compacted patterns. The maximal PSN is 22.32% and 6.94% lower on compacted patterns.
{"title":"Impact of test compression on power supply noise control","authors":"Tengteng Zhang, D. Walker","doi":"10.1109/DFT.2015.7315155","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315155","url":null,"abstract":"Compaction and compression are commonly used to minimize test data volume and test application time. Both techniques can greatly affect power supply noise (PSN) during test, as these techniques take advantage of the fact that test patterns have low care-bit density. However, there is little prior work studying how compression affects PSN. In this work, embedded deterministic test (EDT) and Illinois Scan patterns are generated with and without compaction. Our previous PSN control algorithm is extended to incorporate the compression constraints and applied to these patterns. The experimental results show that with the PSN control algorithm, EDT lowers the maximal PSN by 24.15% and Illinois Scan lowers it by 2.77% on un-compacted patterns. The maximal PSN is 22.32% and 6.94% lower on compacted patterns.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121202662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315130
Badrun Nahar, B. Meyer
As transient and permanent failures are rise shrinking process technology, MPSoC systems with fail-operational behavior have become important, especially for safety-critical applications. We therefore propose RotR, a rotational task mapping approach for an active-redundancy-based system to facilitate parallel execution of redundant tasks. RotR maps tasks such that no single failure affects more than one copy of a redundant task, and utilizes a multi-functional voter task that adapts its functionality based on the system's redundancy state after each component failure. RotR mapping and the proposed voter task jointly enable fail-operational behavior by seamlessly transitioning from higher reliability (e.g., Triple Modular Redundancy) to lower reliability (e.g., Double Modular Redundancy) without requiring task remapping. Our results show that RotR improves a system's fault-tolerant lifetime on average by 37% and 48% over standard DMR and TMR systems, respectively. Furthermore, it improves the overall lifetime by 29% compared to the baseline system having no redundancy.
{"title":"RotR: Rotational redundant task mapping for fail-operational MPSoCs","authors":"Badrun Nahar, B. Meyer","doi":"10.1109/DFT.2015.7315130","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315130","url":null,"abstract":"As transient and permanent failures are rise shrinking process technology, MPSoC systems with fail-operational behavior have become important, especially for safety-critical applications. We therefore propose RotR, a rotational task mapping approach for an active-redundancy-based system to facilitate parallel execution of redundant tasks. RotR maps tasks such that no single failure affects more than one copy of a redundant task, and utilizes a multi-functional voter task that adapts its functionality based on the system's redundancy state after each component failure. RotR mapping and the proposed voter task jointly enable fail-operational behavior by seamlessly transitioning from higher reliability (e.g., Triple Modular Redundancy) to lower reliability (e.g., Double Modular Redundancy) without requiring task remapping. Our results show that RotR improves a system's fault-tolerant lifetime on average by 37% and 48% over standard DMR and TMR systems, respectively. Furthermore, it improves the overall lifetime by 29% compared to the baseline system having no redundancy.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129186419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315156
A. A. Bawa, N. Touba
Combinational linear compactors can be used to compact the output response for a large number of scan chains into a smaller number of outputs. While some compactor designs can guarantee observation of all scan chains in the presence of a small number of X's, this may not be sufficient for designs with higher X densities. This paper describes an approach for using a combinational rotator between the scan chains and compactor to allow detection of faults even in the presence of high X densities. It is shown that the number of control inputs to the rotator is comparable to the number of control inputs required by conventional X masking approaches, but by not masking, the proposed approach is able to provide higher observability which translates to fewer test patterns, better compression, and better coverage of non-modeled faults. Moreover, the control data for the rotator has many more don't cares than the control data for X masking thereby making it easier and more efficient to compress with a linear decompressor. A heuristic procedure for ordering the inputs to a combinational compactor to increase the probability of observation for a given maximum shift distance is also presented. Experimental results indicate that high observability can be achieved using the proposed method with a relatively small number of control inputs.
{"title":"Improving X-tolerant combinational output compaction via input rotation","authors":"A. A. Bawa, N. Touba","doi":"10.1109/DFT.2015.7315156","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315156","url":null,"abstract":"Combinational linear compactors can be used to compact the output response for a large number of scan chains into a smaller number of outputs. While some compactor designs can guarantee observation of all scan chains in the presence of a small number of X's, this may not be sufficient for designs with higher X densities. This paper describes an approach for using a combinational rotator between the scan chains and compactor to allow detection of faults even in the presence of high X densities. It is shown that the number of control inputs to the rotator is comparable to the number of control inputs required by conventional X masking approaches, but by not masking, the proposed approach is able to provide higher observability which translates to fewer test patterns, better compression, and better coverage of non-modeled faults. Moreover, the control data for the rotator has many more don't cares than the control data for X masking thereby making it easier and more efficient to compress with a linear decompressor. A heuristic procedure for ordering the inputs to a combinational compactor to increase the probability of observation for a given maximum shift distance is also presented. Experimental results indicate that high observability can be achieved using the proposed method with a relatively small number of control inputs.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114201556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315142
A. Eker, O. Ergin
Soft errors caused by the cosmic particles or the radiation from the packaging material of the integrated circuits are an increasingly important design problem. With the shrinking feature sizes, the datapath components of the out-of-order superscalar pipeline are becoming more prone to soft errors. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. We start with the observation that many of the stored values inside the register file have very small Hamming distances when compared to each other. After showing this analysis results we propose a soft error correction scheme that makes use of the presence of multiple register values that have zero Hamming distance from each other. We use this already available redundancy along with parity protection to achieve error correction for many of the stored values. Our results show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to detect and correct 39.0% of the errors with an additional power consumption of 18.9%.
{"title":"Using value similarity of registers for soft error mitigation","authors":"A. Eker, O. Ergin","doi":"10.1109/DFT.2015.7315142","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315142","url":null,"abstract":"Soft errors caused by the cosmic particles or the radiation from the packaging material of the integrated circuits are an increasingly important design problem. With the shrinking feature sizes, the datapath components of the out-of-order superscalar pipeline are becoming more prone to soft errors. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. We start with the observation that many of the stored values inside the register file have very small Hamming distances when compared to each other. After showing this analysis results we propose a soft error correction scheme that makes use of the presence of multiple register values that have zero Hamming distance from each other. We use this already available redundancy along with parity protection to achieve error correction for many of the stored values. Our results show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to detect and correct 39.0% of the errors with an additional power consumption of 18.9%.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132426787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315128
Hyunseung Han, Joon-Sung Yang
3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.
{"title":"Asymmetric ECC organization in 3D-memory via spare column utilization","authors":"Hyunseung Han, Joon-Sung Yang","doi":"10.1109/DFT.2015.7315128","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315128","url":null,"abstract":"3D-memory and processor-memory structures are promising applications of 3D-IC technology. With 3D integration, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to their stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes an error rate of the top layer largest among all layers. Therefore, it is important to improve reliability of upper dies in the 3D-ICs. A novel ECC scheme for 3D-memory to secure reliable operations by enhancing ECC capability of upper layer memories is introduced in this paper. The proposed scheme does not require additional redundancies. Instead, it utilizes unused spare columns of lower layer memories to store additional check-bits of upper layer memories. It forms an asymmetric ECC organization across different layers which enhances ECC capabilities in upper layers. Experimental results show that the proposed method can tolerate more than three times of a bit-error rate compared to the conventional method.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133633091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315162
T. Yoneda, Masashi Imai, H. Saito, Kenji Kise
This paper explores a new dependable real-time task execution scheme for a many-core system. This scheme is based on duplication with temporary TMR and reconfiguration. Unlike a common scheme with several spare units, every processor core in our scheme is used for task execution. Thus, redundant processor cores contribute to both the reliability and performance of the entire system. We first show the implementation details of our scheme. Then the proposed scheme is analytically evaluated using abstracted models and compared with two other schemes.
{"title":"Dependable real-time task execution scheme for a many-core platform","authors":"T. Yoneda, Masashi Imai, H. Saito, Kenji Kise","doi":"10.1109/DFT.2015.7315162","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315162","url":null,"abstract":"This paper explores a new dependable real-time task execution scheme for a many-core system. This scheme is based on duplication with temporary TMR and reconfiguration. Unlike a common scheme with several spare units, every processor core in our scheme is used for task execution. Thus, redundant processor cores contribute to both the reliability and performance of the entire system. We first show the implementation details of our scheme. Then the proposed scheme is analytically evaluated using abstracted models and compared with two other schemes.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130928262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315167
C. Bolchini, Luca Cassano
Functional diagnosis for complex electronic boards is a time-consuming task that requires big expertise to the diagnosis engineers. In this paper we propose a new engine for board-level adaptive incremental functional diagnosis based on decision trees. The engine incrementally selects the tests that have to be executed and based on the test outcomes it automatically stops the diagnosis as soon as one or more faulty candidates can be identified, thus allowing to reduce the number of executed tests. Moreover, we propose a configurable early stop condition for the engine that allows to further reduce the number of executed tests leveraging the diagnosis accuracy. The effectiveness of the proposed approach has been assessed using a set of synthetic but realistic boards and three industrial boards.
{"title":"A configurable board-level adaptive incremental diagnosis technique based on decision trees","authors":"C. Bolchini, Luca Cassano","doi":"10.1109/DFT.2015.7315167","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315167","url":null,"abstract":"Functional diagnosis for complex electronic boards is a time-consuming task that requires big expertise to the diagnosis engineers. In this paper we propose a new engine for board-level adaptive incremental functional diagnosis based on decision trees. The engine incrementally selects the tests that have to be executed and based on the test outcomes it automatically stops the diagnosis as soon as one or more faulty candidates can be identified, thus allowing to reduce the number of executed tests. Moreover, we propose a configurable early stop condition for the engine that allows to further reduce the number of executed tests leveraging the diagnosis accuracy. The effectiveness of the proposed approach has been assessed using a set of synthetic but realistic boards and three industrial boards.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121893125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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