Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315129
Adedotun Adeyemo, J. Mathew, A. Jabir, D. Pradhan
In an effort to reduce the overall read/write power consumption in emerging memory technologies, efficient read/write schemes have recently attracted increased attention. Among these emerging technologies is the memristor-based resistive random access memory (ReRAM) with simpler structures and capability of producing highly dense memory through the sneak-path prone crossbar architecture. In this paper, a multiple-cells read solution to reduce the overall energy consumption when reading from a memory array is considered. A closed form expression for the noise margin effect is derived and analysis shows that there is zero sneak-path when sensing certain patterns of stored data. The multiple-cells readout method was thus used to analyse an energy efficient Inverted-Hamming (I-H) architecture capable of detecting and correcting single-bit write error in memristor-based memory array.
{"title":"Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays","authors":"Adedotun Adeyemo, J. Mathew, A. Jabir, D. Pradhan","doi":"10.1109/DFT.2015.7315129","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315129","url":null,"abstract":"In an effort to reduce the overall read/write power consumption in emerging memory technologies, efficient read/write schemes have recently attracted increased attention. Among these emerging technologies is the memristor-based resistive random access memory (ReRAM) with simpler structures and capability of producing highly dense memory through the sneak-path prone crossbar architecture. In this paper, a multiple-cells read solution to reduce the overall energy consumption when reading from a memory array is considered. A closed form expression for the noise margin effect is derived and analysis shows that there is zero sneak-path when sensing certain patterns of stored data. The multiple-cells readout method was thus used to analyse an energy efficient Inverted-Hamming (I-H) architecture capable of detecting and correcting single-bit write error in memristor-based memory array.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130170596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315146
Subidh Ali, O. Sinanoglu
We present a new scan attack on hardware implementation of Elliptic Curve Cryptography (ECC), a representative public key cipher. The existing scan attacks on ECC exploit the Design for Testability (DfT) infrastructure of the implementation to identify the internal registers used in the scalar multiplication, and leak the secret key based on a bit-flip analysis in the scalar multiplication registers. These attacks assume two internal registers are affected by the secret key in the ECC. In practical implementations, multiple internal registers are affected by the secret key, significantly complicating the identification of the targeted registers. Furthermore, existing scan attacks rely on a switch from normal to test mode, fail against the widely utilized mode-reset countermeasure. The proposed attack identifies the internal registers in a depth-first search fashion, where registers corresponding to the innermost module of the hardware design are identified first. This attack identifies all the registers related to the secret key, and does so by remaining only in the test mode, thus overcoming both limitations of the existing scan attacks.
{"title":"Scan attack on Elliptic Curve Cryptosystem","authors":"Subidh Ali, O. Sinanoglu","doi":"10.1109/DFT.2015.7315146","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315146","url":null,"abstract":"We present a new scan attack on hardware implementation of Elliptic Curve Cryptography (ECC), a representative public key cipher. The existing scan attacks on ECC exploit the Design for Testability (DfT) infrastructure of the implementation to identify the internal registers used in the scalar multiplication, and leak the secret key based on a bit-flip analysis in the scalar multiplication registers. These attacks assume two internal registers are affected by the secret key in the ECC. In practical implementations, multiple internal registers are affected by the secret key, significantly complicating the identification of the targeted registers. Furthermore, existing scan attacks rely on a switch from normal to test mode, fail against the widely utilized mode-reset countermeasure. The proposed attack identifies the internal registers in a depth-first search fashion, where registers corresponding to the innermost module of the hardware design are identified first. This attack identifies all the registers related to the secret key, and does so by remaining only in the test mode, thus overcoming both limitations of the existing scan attacks.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127675404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315148
Puneet Ramesh Savanur, Phaninder Alladi, S. Tragoudas
This paper presents a simple BIST enhancement to detect counterfeit circuits which experience aging delays. The approach is based on the NBTI aging factor. HSPICE simulations on 45nm and 65nm technologies using a predictive NBTI degradation model are presented. The results indicate that counterfeit circuits undergone minimal stress are detected consistently in the presence of process variations.
{"title":"A BIST approach for counterfeit circuit detection based on NBTI degradation","authors":"Puneet Ramesh Savanur, Phaninder Alladi, S. Tragoudas","doi":"10.1109/DFT.2015.7315148","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315148","url":null,"abstract":"This paper presents a simple BIST enhancement to detect counterfeit circuits which experience aging delays. The approach is based on the NBTI aging factor. HSPICE simulations on 45nm and 65nm technologies using a predictive NBTI degradation model are presented. The results indicate that counterfeit circuits undergone minimal stress are detected consistently in the presence of process variations.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134019310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315151
Gustavo K. Contreras, N. Ahmed, L. Winemberg, M. Tehranipoor
Integrated circuits used in critical and high reliability applications have often strict test requirements including high test coverage and limited test time. Achieving a high test coverage using built-in self-test (BIST) has proven difficult. Methods such as test point insertion or deterministic BIST can provide high test coverage but introduce significant area overhead and design effort. In this paper, we propose a computational algorithm that uses a linear XOR model of the logic BIST (LBIST) structure and fault partitioning to extract seeds for partial ATPG patterns. Partial ATPG patterns are used to decrease the complexity of the algorithm when solving linear XOR equations to generate deterministic seeds. The extracted seeds are stored in a nonvolatile memory on- or off-chip. Results show that for most designs, patterns generated from the extracted ATPG seeds are significantly more effective in detecting faults and can achieve higher test coverage than LBIST.
{"title":"Predictive LBIST model and partial ATPG for seed extraction","authors":"Gustavo K. Contreras, N. Ahmed, L. Winemberg, M. Tehranipoor","doi":"10.1109/DFT.2015.7315151","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315151","url":null,"abstract":"Integrated circuits used in critical and high reliability applications have often strict test requirements including high test coverage and limited test time. Achieving a high test coverage using built-in self-test (BIST) has proven difficult. Methods such as test point insertion or deterministic BIST can provide high test coverage but introduce significant area overhead and design effort. In this paper, we propose a computational algorithm that uses a linear XOR model of the logic BIST (LBIST) structure and fault partitioning to extract seeds for partial ATPG patterns. Partial ATPG patterns are used to decrease the complexity of the algorithm when solving linear XOR equations to generate deterministic seeds. The extracted seeds are stored in a nonvolatile memory on- or off-chip. Results show that for most designs, patterns generated from the extracted ATPG seeds are significantly more effective in detecting faults and can achieve higher test coverage than LBIST.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133984013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315160
D. Felici, S. Bonacini, M. Ottavi
The availability of low-power, radiation-resistant components has an enormous importance in the development of the electronic systems for modern detectors in a High Energy Physics (HEP) experiment. This paper describes the characterization in terms of radiation effects of two serializer blocks within a high speed transmitter, prior developed with the objective of achieving a power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. Within the first serializer, called “simple TMR”, a traditional solution, based on the hardware redundancy, has been implemented. In the second case a new architecture, less power consuming, called “code protected”, has been proposed. The tests previously performed shown an average consumption of ~30 mW and ~19 mW, respectively, for a bit rate of 4.8 Gbit/sec but do not fully clarify if the blocks are suitable for working under extremely high radiation levels. Hence, a deep radiation hardness investigation has been performed and presented here to confirm the availability of these blocks in a HEP electronic system. SEU sensitivities are measured and bit error rates better than 2 E-15 are obtained, confirming that the “code protected” solution assures reliable communications in HEP experiments environment with a smaller power consumption. These blocks have also been designed and tested to cope with a total ionizing dose of 100 Mrad over 10 years of operation.
{"title":"Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics","authors":"D. Felici, S. Bonacini, M. Ottavi","doi":"10.1109/DFT.2015.7315160","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315160","url":null,"abstract":"The availability of low-power, radiation-resistant components has an enormous importance in the development of the electronic systems for modern detectors in a High Energy Physics (HEP) experiment. This paper describes the characterization in terms of radiation effects of two serializer blocks within a high speed transmitter, prior developed with the objective of achieving a power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. Within the first serializer, called “simple TMR”, a traditional solution, based on the hardware redundancy, has been implemented. In the second case a new architecture, less power consuming, called “code protected”, has been proposed. The tests previously performed shown an average consumption of ~30 mW and ~19 mW, respectively, for a bit rate of 4.8 Gbit/sec but do not fully clarify if the blocks are suitable for working under extremely high radiation levels. Hence, a deep radiation hardness investigation has been performed and presented here to confirm the availability of these blocks in a HEP electronic system. SEU sensitivities are measured and bit error rates better than 2 E-15 are obtained, confirming that the “code protected” solution assures reliable communications in HEP experiments environment with a smaller power consumption. These blocks have also been designed and tested to cope with a total ionizing dose of 100 Mrad over 10 years of operation.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129733915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315161
A. Malek, S. Tzilis, D. Khan, I. Sourdis, Georgios Smaragdos, C. Strydis
Permanent faults on a chip are often tolerated using spare resources. In the past, sparing has been applied to Chip Multiprocessors (CMPs) at various granularities of substitutable units (SUs). Entire processors, pipeline stages or even individual functional units are isolated when faulty and replaced by spare ones using flexible, reconfigurable interconnects. Although spare resources increase systems fault tolerance, the extra delay imposed by the reconfigurable interconnects limits performance. In this paper, we study two options for dealing with this delay: (i) pipelining the reconfigurable interconnects and (ii) scaling down operating frequency. The former keeps a frequency close to the one of the baseline processor, but increases the number of cycles required for executing a program. The latter maintains the number of execution cycles constant, but requires a slower clock. We investigate the above performance tradeoff using an adaptive 4-core CMP design with substitutable pipeline stages. We retrieve post place and route results of different designs running two sets of benchmarks and evaluate their performance. Our experiments indicate that adding reconfigurable interconnects for wiring the SUs of a 4-core CMP pose significant delay increasing the critical path of the design almost by 3.5 times. On the other hand, pipelining the reconfigurable interconnects increases cycle time by 41% and - depending on the processor configuration - reduces performance overhead to 1.4-2.9× the execution time of the baseline.
{"title":"Reducing the performance overhead of resilient CMPs with substitutable resources","authors":"A. Malek, S. Tzilis, D. Khan, I. Sourdis, Georgios Smaragdos, C. Strydis","doi":"10.1109/DFT.2015.7315161","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315161","url":null,"abstract":"Permanent faults on a chip are often tolerated using spare resources. In the past, sparing has been applied to Chip Multiprocessors (CMPs) at various granularities of substitutable units (SUs). Entire processors, pipeline stages or even individual functional units are isolated when faulty and replaced by spare ones using flexible, reconfigurable interconnects. Although spare resources increase systems fault tolerance, the extra delay imposed by the reconfigurable interconnects limits performance. In this paper, we study two options for dealing with this delay: (i) pipelining the reconfigurable interconnects and (ii) scaling down operating frequency. The former keeps a frequency close to the one of the baseline processor, but increases the number of cycles required for executing a program. The latter maintains the number of execution cycles constant, but requires a slower clock. We investigate the above performance tradeoff using an adaptive 4-core CMP design with substitutable pipeline stages. We retrieve post place and route results of different designs running two sets of benchmarks and evaluate their performance. Our experiments indicate that adding reconfigurable interconnects for wiring the SUs of a 4-core CMP pose significant delay increasing the critical path of the design almost by 3.5 times. On the other hand, pipelining the reconfigurable interconnects increases cycle time by 41% and - depending on the processor configuration - reduces performance overhead to 1.4-2.9× the execution time of the baseline.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"7 9‐10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120859721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315165
Bahareh J. Farahani, S. Safari
As the semiconductor industry migrates into the nanometer regime, processors become increasingly susceptible to transient faults. Such faults usually stem either from soft errors due to particle strikes or timing violations due to Process, Voltage, Temperature, and Aging (PVTA) variations. These faults can propagate from circuit-level to application-level and alter the correct execution output of the application. For generations, designers build high-level resiliency such that the details of the underlying circuit are an abstraction that could be neglected. This paper argues that in contrast to the prior work, which only take into account Architectural Vulnerability Factor (AVF) as a measure to guide fault tolerant techniques, the vulnerability of each abstraction layer of design stack from circuit going up to instruction and application layers should be considered. This paper presents a novel online cross-layer reliability prediction technique based on learning algorithms which can anticipate the susceptibility of the processor considering both lower-level and higher-level details in an adaptive fashion. According to the results, the proposed technique can predict the future reliability with 6% error on average across SPEC2000 benchmarks. Our technique by forecasting the reliability emergencies can assist proactive fault tolerant techniques to maintain the reliability constraints more efficiently in comparison to reactive strategies.
{"title":"A cross-layer approach to online adaptive reliability prediction of transient faults","authors":"Bahareh J. Farahani, S. Safari","doi":"10.1109/DFT.2015.7315165","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315165","url":null,"abstract":"As the semiconductor industry migrates into the nanometer regime, processors become increasingly susceptible to transient faults. Such faults usually stem either from soft errors due to particle strikes or timing violations due to Process, Voltage, Temperature, and Aging (PVTA) variations. These faults can propagate from circuit-level to application-level and alter the correct execution output of the application. For generations, designers build high-level resiliency such that the details of the underlying circuit are an abstraction that could be neglected. This paper argues that in contrast to the prior work, which only take into account Architectural Vulnerability Factor (AVF) as a measure to guide fault tolerant techniques, the vulnerability of each abstraction layer of design stack from circuit going up to instruction and application layers should be considered. This paper presents a novel online cross-layer reliability prediction technique based on learning algorithms which can anticipate the susceptibility of the processor considering both lower-level and higher-level details in an adaptive fashion. According to the results, the proposed technique can predict the future reliability with 6% error on average across SPEC2000 benchmarks. Our technique by forecasting the reliability emergencies can assist proactive fault tolerant techniques to maintain the reliability constraints more efficiently in comparison to reactive strategies.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122995956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315138
I. Herrera-Alzu, M. López-Vallejo, C. G. Soriano
Systems based on Xilinx Virtex series FPGAs can benefit, compared to traditional rad-hard technologies, from high performance, high logic density and dynamic reconfiguration capability. However, the underlying SRAM technology is sensitive to ionizing radiation, which can induce faults that must be managed to improve system's dependability. This paper proposes a Dual-Layer Fault Manager concept, which aims at managing both configuration and application faults, dynamically balancing redundancy level, dependability and functionality. This concept has been prototyped and its initial test results are discussed.
{"title":"A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs","authors":"I. Herrera-Alzu, M. López-Vallejo, C. G. Soriano","doi":"10.1109/DFT.2015.7315138","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315138","url":null,"abstract":"Systems based on Xilinx Virtex series FPGAs can benefit, compared to traditional rad-hard technologies, from high performance, high logic density and dynamic reconfiguration capability. However, the underlying SRAM technology is sensitive to ionizing radiation, which can induce faults that must be managed to improve system's dependability. This paper proposes a Dual-Layer Fault Manager concept, which aims at managing both configuration and application faults, dynamically balancing redundancy level, dependability and functionality. This concept has been prototyped and its initial test results are discussed.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127041113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315133
G. Chapman, Rahul Thomas, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Tommy Q. Yang, I. Koren, Z. Koren
From extensive study of digital imager defects, we found that permanent “Hot Pixels” are the main long term digital camera defects, and are caused by high energy cosmic ray particles. Clearly, as in other microelectronic integrated circuits, most of the particles do not induce permanent damage but instead, inject a short term charge that may cause a transient fault, known as a Single Event Upset (SEU). Unlike standard digital ICs, pixels in a digital imaging sensor can be monitored at almost any desirable frequency. Since an SEU manifests itself as one or more brighter pixels in an otherwise dark image, the rate of SEUs can be measured at a considerably higher accuracy by taking dark-field pictures at different exposure times and different frequencies. In this paper we describe an experimental approach to measuring the occurrence rate and resulting characteristics of SEUs. The SEU rate that we have observed for digital imagers, of about 4 SEUs for every 30 seconds, is considerably higher than was previously reported for ordinary ICs. For the same imager, permanent hot pixels have a rate of 1 every 12.6 days, while SEUs occur 145,000 times more often. Ordinary IC SEU rates have been reported to be about 100× of permanent fault rates. In addition, we found that some SEUs in digital imagers do not impact a single pixel, as do hot pixels, but can create a line of injected charges which appears as a bright line in the dark image.
{"title":"Single Event Upsets and Hot Pixels in digital imagers","authors":"G. Chapman, Rahul Thomas, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Tommy Q. Yang, I. Koren, Z. Koren","doi":"10.1109/DFT.2015.7315133","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315133","url":null,"abstract":"From extensive study of digital imager defects, we found that permanent “Hot Pixels” are the main long term digital camera defects, and are caused by high energy cosmic ray particles. Clearly, as in other microelectronic integrated circuits, most of the particles do not induce permanent damage but instead, inject a short term charge that may cause a transient fault, known as a Single Event Upset (SEU). Unlike standard digital ICs, pixels in a digital imaging sensor can be monitored at almost any desirable frequency. Since an SEU manifests itself as one or more brighter pixels in an otherwise dark image, the rate of SEUs can be measured at a considerably higher accuracy by taking dark-field pictures at different exposure times and different frequencies. In this paper we describe an experimental approach to measuring the occurrence rate and resulting characteristics of SEUs. The SEU rate that we have observed for digital imagers, of about 4 SEUs for every 30 seconds, is considerably higher than was previously reported for ordinary ICs. For the same imager, permanent hot pixels have a rate of 1 every 12.6 days, while SEUs occur 145,000 times more often. Ordinary IC SEU rates have been reported to be about 100× of permanent fault rates. In addition, we found that some SEUs in digital imagers do not impact a single pixel, as do hot pixels, but can create a line of injected charges which appears as a bright line in the dark image.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131638007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/DFT.2015.7315168
Mohammad Raashid Ansari, Shucheng Yu, Qiaoyan Yu
Controller Area Network (CAN) is the main bus network that connects electronic control units in automobiles. Although CAN protocols have been revised to improve the vehicle safety, the security weaknesses of CAN have not been fully addressed. Security threats on automobiles might be from external wireless communication or from internal malicious CAN nodes mounted on the CAN bus. Despite of various threat sources, the security weakness of CAN is the root of security problems. Due to the limited computation power and storage capacity on each CAN node, there is a lack of hardware-efficient protection methods for the CAN system without losing the compatibility to CAN protocols. To save the cost and maintain the compatibility, we propose to exploit the built-in CAN fault confinement mechanism to detect the masquerade attacks originated from the malicious CAN devices on the CAN bus. Simulation results show that our method achieves the attack misdetection rate at the order of 10-5 and reduces the encryption latency by up to 68% over the complete frame encryption method.
{"title":"IntelliCAN: Attack-resilient Controller Area Network (CAN) for secure automobiles","authors":"Mohammad Raashid Ansari, Shucheng Yu, Qiaoyan Yu","doi":"10.1109/DFT.2015.7315168","DOIUrl":"https://doi.org/10.1109/DFT.2015.7315168","url":null,"abstract":"Controller Area Network (CAN) is the main bus network that connects electronic control units in automobiles. Although CAN protocols have been revised to improve the vehicle safety, the security weaknesses of CAN have not been fully addressed. Security threats on automobiles might be from external wireless communication or from internal malicious CAN nodes mounted on the CAN bus. Despite of various threat sources, the security weakness of CAN is the root of security problems. Due to the limited computation power and storage capacity on each CAN node, there is a lack of hardware-efficient protection methods for the CAN system without losing the compatibility to CAN protocols. To save the cost and maintain the compatibility, we propose to exploit the built-in CAN fault confinement mechanism to detect the masquerade attacks originated from the malicious CAN devices on the CAN bus. Simulation results show that our method achieves the attack misdetection rate at the order of 10-5 and reduces the encryption latency by up to 68% over the complete frame encryption method.","PeriodicalId":383972,"journal":{"name":"2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)","volume":"18 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133107205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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