Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00022
Gaoyang Dai, M. Mohaqeqi, W. Yi
Designing timing-anomaly free multiprocessor scheduling algorithms is a notoriously hard problem, especially for parallel tasks with non-preemptive execution regions. In this paper, we first propose a simple yet expressive model which abstracts a parallel task as a single computation unit, and then, present a sufficient condition for timing-anomaly free scheduling of such units. On top of this, we design an algorithm for scheduling a set of periodic parallel tasks, represented as DAG with non-preemptive subtasks, on multicore processors. The algorithm has several desirable properties, including timing-anomaly freedom, high resource utilization, and low memory requirement. Timing-anomaly freedom enables an exact schedulability test for the algorithm, which, as shown in our evaluations, provides a significantly high schedulability ratio compared to those state-of-the-art methods that suffer from timing anomalies.
{"title":"Timing-Anomaly Free Dynamic Scheduling of Periodic DAG Tasks with Non-Preemptive Nodes","authors":"Gaoyang Dai, M. Mohaqeqi, W. Yi","doi":"10.1109/RTCSA52859.2021.00022","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00022","url":null,"abstract":"Designing timing-anomaly free multiprocessor scheduling algorithms is a notoriously hard problem, especially for parallel tasks with non-preemptive execution regions. In this paper, we first propose a simple yet expressive model which abstracts a parallel task as a single computation unit, and then, present a sufficient condition for timing-anomaly free scheduling of such units. On top of this, we design an algorithm for scheduling a set of periodic parallel tasks, represented as DAG with non-preemptive subtasks, on multicore processors. The algorithm has several desirable properties, including timing-anomaly freedom, high resource utilization, and low memory requirement. Timing-anomaly freedom enables an exact schedulability test for the algorithm, which, as shown in our evaluations, provides a significantly high schedulability ratio compared to those state-of-the-art methods that suffer from timing anomalies.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"8 1","pages":"119-128"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84365328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00020
Tianning She, Zhishan Guo, Qijun Gu, Kecheng Yang
Mixed-criticality (MC) scheduling has been proposed to mitigate the pessimism in real-time schedulability analysis that must provide guarantees for the worst case. In most existing work on MC scheduling, low-critical tasks are either dropped or degraded at the criticality mode switch in order to preserve the temporal guarantees for high-critical tasks. Recently, a different direction, called precise MC scheduling, has been investigated. In precise MC scheduling, no low-critical task should be dropped or degraded; instead, the platform processing capacity is augmented at mode switch to accommodate the additional workload by high-critical tasks. In contrast to prior work on this topic with respect to varying processor speed, this work investigates the precise scheduling problem of MC tasks when the number of available processors may vary at the mode switch. To address this new problem, we propose two alternative algorithms by adapting virtual-deadline-based EDF and by fluid scheduling, respectively, and provide a sufficient schedulability test for each. We also conduct schedulability experiments with randomly generated task sets to demonstrate the effectiveness of the proposed algorithms and the benefits of the new scheduling model.
{"title":"Reserving Processors by Precise Scheduling of Mixed-Criticality Tasks","authors":"Tianning She, Zhishan Guo, Qijun Gu, Kecheng Yang","doi":"10.1109/RTCSA52859.2021.00020","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00020","url":null,"abstract":"Mixed-criticality (MC) scheduling has been proposed to mitigate the pessimism in real-time schedulability analysis that must provide guarantees for the worst case. In most existing work on MC scheduling, low-critical tasks are either dropped or degraded at the criticality mode switch in order to preserve the temporal guarantees for high-critical tasks. Recently, a different direction, called precise MC scheduling, has been investigated. In precise MC scheduling, no low-critical task should be dropped or degraded; instead, the platform processing capacity is augmented at mode switch to accommodate the additional workload by high-critical tasks. In contrast to prior work on this topic with respect to varying processor speed, this work investigates the precise scheduling problem of MC tasks when the number of available processors may vary at the mode switch. To address this new problem, we propose two alternative algorithms by adapting virtual-deadline-based EDF and by fluid scheduling, respectively, and provide a sufficient schedulability test for each. We also conduct schedulability experiments with randomly generated task sets to demonstrate the effectiveness of the proposed algorithms and the benefits of the new scheduling model.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"1990 1","pages":"103-108"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82320395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00016
Sharmila Devi Kannivelu, Sunwoong Kim
Homomorphic encryption (HE) is an important cryptographic technique that allows one to directly perform computation on encrypted data without decryption. In HE-based applications using digital images, a user often encrypts a private image captured on a local device. This image can contain noise that negatively affects the results of HE-based applications. To solve this problem, this paper proposes an HE-based adaptive image filter. For small-sized encrypted input data, pixels that have no dependency when sliding a window are encoded into the same ciphertext. For division in the adaptive filter, which is not supported by conventional HE schemes, a numerical approach is adopted. To the best of the authors’ knowledge, this paper is the first work that applies division over encrypted data to an image processing algorithm. We implemented the proposed HE-based adaptive filter as a proof-of-concept client-server model. The proposed design can address important privacy issues in image processing applications in internet-of-things and cyber-physical systems, where many devices are connected through a vulnerable network.
{"title":"A Homomorphic Encryption-based Adaptive Image Filter Using Division Over Encrypted Data","authors":"Sharmila Devi Kannivelu, Sunwoong Kim","doi":"10.1109/RTCSA52859.2021.00016","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00016","url":null,"abstract":"Homomorphic encryption (HE) is an important cryptographic technique that allows one to directly perform computation on encrypted data without decryption. In HE-based applications using digital images, a user often encrypts a private image captured on a local device. This image can contain noise that negatively affects the results of HE-based applications. To solve this problem, this paper proposes an HE-based adaptive image filter. For small-sized encrypted input data, pixels that have no dependency when sliding a window are encoded into the same ciphertext. For division in the adaptive filter, which is not supported by conventional HE schemes, a numerical approach is adopted. To the best of the authors’ knowledge, this paper is the first work that applies division over encrypted data to an image processing algorithm. We implemented the proposed HE-based adaptive filter as a proof-of-concept client-server model. The proposed design can address important privacy issues in image processing applications in internet-of-things and cyber-physical systems, where many devices are connected through a vulnerable network.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"2 1","pages":"67-72"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89833696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00008
A. Friebe, Filip Marković, A. Papadopoulos, Thomas Nolte
In the recent works that analyzed execution-time variation of real-time tasks, it was shown that such variation may conform to regular behavior. This regularity may arise from multiple sources, e.g., due to periodic changes in hardware or program state, program structure, inter-task dependence or inter-task interference. Such complexity can be better captured by a Markov Model, compared to the common approach of assuming independent and identically distributed random variables. However, despite the regularity that may be described with a Markov model, over time, the execution times may change, due to irregular changes in input, hardware state, or program state. In this paper, we propose a Bayesian approach to adapt the emission distributions of the Markov Model at runtime, in order to account for such irregular variation. A preprocessing step determines the number of states and the transition matrix of the Markov Model from a portion of the execution time sequence. In the preprocessing step, segments of the execution time trace with similar properties are identified and combined into clusters. At runtime, the proposed method switches between these clusters based on a Generalized Likelihood Ratio (GLR). Using a Bayesian approach, clusters are updated and emission distributions estimated. New clusters can be identified and clusters can be merged at runtime. The time complexity of the online step is $O(N^{2}+ NC)$ where N is the number of states in the Hidden Markov Model (HMM) that is fixed after the preprocessing step, and C is the number of clusters.
{"title":"Adaptive Runtime Estimate of Task Execution Times using Bayesian Modeling","authors":"A. Friebe, Filip Marković, A. Papadopoulos, Thomas Nolte","doi":"10.1109/RTCSA52859.2021.00008","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00008","url":null,"abstract":"In the recent works that analyzed execution-time variation of real-time tasks, it was shown that such variation may conform to regular behavior. This regularity may arise from multiple sources, e.g., due to periodic changes in hardware or program state, program structure, inter-task dependence or inter-task interference. Such complexity can be better captured by a Markov Model, compared to the common approach of assuming independent and identically distributed random variables. However, despite the regularity that may be described with a Markov model, over time, the execution times may change, due to irregular changes in input, hardware state, or program state. In this paper, we propose a Bayesian approach to adapt the emission distributions of the Markov Model at runtime, in order to account for such irregular variation. A preprocessing step determines the number of states and the transition matrix of the Markov Model from a portion of the execution time sequence. In the preprocessing step, segments of the execution time trace with similar properties are identified and combined into clusters. At runtime, the proposed method switches between these clusters based on a Generalized Likelihood Ratio (GLR). Using a Bayesian approach, clusters are updated and emission distributions estimated. New clusters can be identified and clusters can be merged at runtime. The time complexity of the online step is $O(N^{2}+ NC)$ where N is the number of states in the Hidden Markov Model (HMM) that is fixed after the preprocessing step, and C is the number of clusters.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"55 s61","pages":"1-10"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72389793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00009
Yao-Hung Huang, Jen-Wei Hsieh
Spin-transfer torque RAM (STT-RAM) has been considered as a promising candidate for the next generation on-chip last-level cache (LLC) due to its high cell density, non-volatility, and near-zero standby power. To further improve cell density, multi-level cell (MLC) STT-RAM has been proposed and widely adopted. However, applying MLC STT-RAM to LLC might suffer from both write disturbance (WD) and read disturbance (RD). WD that needs two-step write operations to write data in MLC STT-RAM cell incurs extra energy consumption and latency overhead. RD means that reading data from a cell will also disturb the original data. In this paper, we propose a read/write disturbance-aware (RWDA) design for MLC STT-RAM-based cache to reduce the overhead caused by the WD and RD. We delay restore operations to mitigate the adverse impacts of disturbances. Instead of the typical LRU replacement policy, we propose a priority-based victim selection policy to meet the very distinct characteristics of MLC STT-RAM. Since accessing soft bits is much more beneficial than accessing hard bits in terms of access latency and energy consumption, we adopt a swapping mechanism to exchange frequently accessed data from hard bits to soft bits. The experimental results showed that the proposed design could averagely achieve 26.6% energy-consumption reduction and 29.5% IPC of system-performance improvement, compared with the conventional design of MLC STT-RAM cache.
{"title":"Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache","authors":"Yao-Hung Huang, Jen-Wei Hsieh","doi":"10.1109/RTCSA52859.2021.00009","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00009","url":null,"abstract":"Spin-transfer torque RAM (STT-RAM) has been considered as a promising candidate for the next generation on-chip last-level cache (LLC) due to its high cell density, non-volatility, and near-zero standby power. To further improve cell density, multi-level cell (MLC) STT-RAM has been proposed and widely adopted. However, applying MLC STT-RAM to LLC might suffer from both write disturbance (WD) and read disturbance (RD). WD that needs two-step write operations to write data in MLC STT-RAM cell incurs extra energy consumption and latency overhead. RD means that reading data from a cell will also disturb the original data. In this paper, we propose a read/write disturbance-aware (RWDA) design for MLC STT-RAM-based cache to reduce the overhead caused by the WD and RD. We delay restore operations to mitigate the adverse impacts of disturbances. Instead of the typical LRU replacement policy, we propose a priority-based victim selection policy to meet the very distinct characteristics of MLC STT-RAM. Since accessing soft bits is much more beneficial than accessing hard bits in terms of access latency and energy consumption, we adopt a swapping mechanism to exchange frequently accessed data from hard bits to soft bits. The experimental results showed that the proposed design could averagely achieve 26.6% energy-consumption reduction and 29.5% IPC of system-performance improvement, compared with the conventional design of MLC STT-RAM cache.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"72 1","pages":"11-20"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85976560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00011
Abderaouf N. Amalou, I. Puaut, Gilles Muller
Modern processors raise a challenge for WCET estimation, since detailed knowledge of the processor microarchitecture is not available. This paper proposes a novel hybrid WCET estimation technique, WE-HML, in which the longest path is estimated using static techniques, whereas machine learning (ML) is used to determine the WCET of basic blocks. In contrast to existing literature using ML techniques for WCET estimation, WE-HML (i) operates on binary code for improved precision of learning, as compared to the related techniques operating at source code or intermediate code level; (ii) trains the ML algorithms on a large set of automatically generated programs for improved quality of learning; (iii) proposes a technique to take into account data caches. Experiments on an ARM Cortex-A53 processor show that for all benchmarks, WCET estimates obtained by WE-HML are larger than all possible execution times. Moreover, the cache modeling technique of WE-HML allows an improvement of 65 percent on average of WCET estimates compared to its cache-agnostic equivalent.
{"title":"WE-HML: hybrid WCET estimation using machine learning for architectures with caches","authors":"Abderaouf N. Amalou, I. Puaut, Gilles Muller","doi":"10.1109/RTCSA52859.2021.00011","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00011","url":null,"abstract":"Modern processors raise a challenge for WCET estimation, since detailed knowledge of the processor microarchitecture is not available. This paper proposes a novel hybrid WCET estimation technique, WE-HML, in which the longest path is estimated using static techniques, whereas machine learning (ML) is used to determine the WCET of basic blocks. In contrast to existing literature using ML techniques for WCET estimation, WE-HML (i) operates on binary code for improved precision of learning, as compared to the related techniques operating at source code or intermediate code level; (ii) trains the ML algorithms on a large set of automatically generated programs for improved quality of learning; (iii) proposes a technique to take into account data caches. Experiments on an ARM Cortex-A53 processor show that for all benchmarks, WCET estimates obtained by WE-HML are larger than all possible execution times. Moreover, the cache modeling technique of WE-HML allows an improvement of 65 percent on average of WCET estimates compared to its cache-agnostic equivalent.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"309 5","pages":"31-40"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72564853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00026
Ondřej Benedikt, M. Sojka, P. Zaykov, David Hornof, Matěj Kafka, P. Šůcha, Z. Hanzálek
The demand for high-performance computing leads to the adoption of modern Multi-Processor System-on-Chip platforms in the avionics domain, where many applications are safety-critical. To fulfill the safety requirements, it is vital to avoid the platform’s overheating. In this paper, we propose a task mapping method, MultiPAWS, for thermal-aware allocation of the safety-critical avionics workloads under time isolation constraints. With the help of MultiPAWS, we jointly find an optimal number of scheduling windows and their lengths and optimal mapping of the workload to these windows and available CPU cores. To guide the optimization, we introduce a thermal model based on power-characteristic coefficients, which we experimentally identify for a benchmark dataset on NXP i.MX8QuadMax platform (based on ARMv8 big.LITTLE architecture). Furthermore, to mimic the execution of safety-critical avionics applications, we introduce DEmOS, an open-source Linux-based scheduler. DEmOS provides a time-partitioned scheduling similar to the ARINC 653 standard. We use DEmOS for the experimental evaluation on the i.MX8 platform. The experimental results suggest that MultiPAWS achieves over a 12% decrease of the platform temperature compared to the minimum-utilization-based approach. Moreover, we demonstrate how MultiPAWS can be used in design space exploration for finding the tradeoff between the platform temperature and the length of the scheduling hyper-period.
{"title":"Thermal-Aware Scheduling for MPSoC in the Avionics Domain: Tooling and Initial Results","authors":"Ondřej Benedikt, M. Sojka, P. Zaykov, David Hornof, Matěj Kafka, P. Šůcha, Z. Hanzálek","doi":"10.1109/RTCSA52859.2021.00026","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00026","url":null,"abstract":"The demand for high-performance computing leads to the adoption of modern Multi-Processor System-on-Chip platforms in the avionics domain, where many applications are safety-critical. To fulfill the safety requirements, it is vital to avoid the platform’s overheating. In this paper, we propose a task mapping method, MultiPAWS, for thermal-aware allocation of the safety-critical avionics workloads under time isolation constraints. With the help of MultiPAWS, we jointly find an optimal number of scheduling windows and their lengths and optimal mapping of the workload to these windows and available CPU cores. To guide the optimization, we introduce a thermal model based on power-characteristic coefficients, which we experimentally identify for a benchmark dataset on NXP i.MX8QuadMax platform (based on ARMv8 big.LITTLE architecture). Furthermore, to mimic the execution of safety-critical avionics applications, we introduce DEmOS, an open-source Linux-based scheduler. DEmOS provides a time-partitioned scheduling similar to the ARINC 653 standard. We use DEmOS for the experimental evaluation on the i.MX8 platform. The experimental results suggest that MultiPAWS achieves over a 12% decrease of the platform temperature compared to the minimum-utilization-based approach. Moreover, we demonstrate how MultiPAWS can be used in design space exploration for finding the tradeoff between the platform temperature and the length of the scheduling hyper-period.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"79 1","pages":"159-168"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90608925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00015
Francis Akowuah, Romesh Prasad, Carlos Omar Espinoza, Fanxin Kong
Autonomous cyber-physical systems (CPS) are susceptible to non-invasive physical attacks such as sensor spoofing attacks that are beyond the classical cybersecurity domain. These attacks have motivated numerous research efforts on attack detection, but little attention on what to do after detecting an attack. The importance of attack recovery is emphasized by the need to mitigate the attack’s impact on a system and restore it to continue functioning. There are only a few works addressing attack recovery, but they all rely on prior knowledge of system dynamics. To overcome this limitation, we propose Recovery-by-Learning, a data-driven attack recovery framework that restores CPS from sensor attacks. The framework leverages natural redundancy among heterogeneous sensors and historical data for attack recovery. Specially, the framework consists of two major components: state predictor and data checkpointer. First, the predictor is triggered to estimate systems states after the detection of an attack. We propose a deep learning-based prediction model that exploits the temporal correlation among heterogeneous sensors. Second, the checkpointer executes when no attack is detected. We propose a double sliding window based checkpointing protocol to remove compromised data and keep trustful data as input to the state predictor. Third, we implement and evaluate the effectiveness of our framework using a realistic data set and a ground vehicle simulator. The results show that our method restores a system to continue functioning in presence of sensor attacks.
{"title":"Recovery-by-Learning: Restoring Autonomous Cyber-physical Systems from Sensor Attacks","authors":"Francis Akowuah, Romesh Prasad, Carlos Omar Espinoza, Fanxin Kong","doi":"10.1109/RTCSA52859.2021.00015","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00015","url":null,"abstract":"Autonomous cyber-physical systems (CPS) are susceptible to non-invasive physical attacks such as sensor spoofing attacks that are beyond the classical cybersecurity domain. These attacks have motivated numerous research efforts on attack detection, but little attention on what to do after detecting an attack. The importance of attack recovery is emphasized by the need to mitigate the attack’s impact on a system and restore it to continue functioning. There are only a few works addressing attack recovery, but they all rely on prior knowledge of system dynamics. To overcome this limitation, we propose Recovery-by-Learning, a data-driven attack recovery framework that restores CPS from sensor attacks. The framework leverages natural redundancy among heterogeneous sensors and historical data for attack recovery. Specially, the framework consists of two major components: state predictor and data checkpointer. First, the predictor is triggered to estimate systems states after the detection of an attack. We propose a deep learning-based prediction model that exploits the temporal correlation among heterogeneous sensors. Second, the checkpointer executes when no attack is detected. We propose a double sliding window based checkpointing protocol to remove compromised data and keep trustful data as input to the state predictor. Third, we implement and evaluate the effectiveness of our framework using a realistic data set and a ground vehicle simulator. The results show that our method restores a system to continue functioning in presence of sensor attacks.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"46 1","pages":"61-66"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87551289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00035
Pan Yang, Pan Dong, Zhe Jiang, Jintao Xia, Yan Ding
In modern safety-critical embedded systems (e.g., automotive/avionic systems), it is increasingly important to integrate components with different critical levels into one physical platform considering space, weight, and heat generation. The most common case is a mixed-time-sensitive system (MTSS), which is usually composed of an RTOS (Real-Time Operating System) and a GPOS (General-Purpose Operating System). In MTSS, cache sharing between RTOS and GPOS often causes inter-task interference, making WCET estimation overly pessimistic due to the increase of cache miss rate and task execution time variances. The existing cache management solutions, such as dynamic and static schemes, are challenging to be applied to MTSS. In this paper, we propose a novel practical method, termed cacheSPM, to eliminate the cache interference in MTSS. CacheSPM statically partitions cache resources during the compilation phase, effectively preventing the GPOS from influencing the cache resources belonged to the RTOS. Compared to the traditional partition schemes, cacheSPM has no intervention of memory manager and additional runtime overhead. Evaluation reveals that this method improves the memory utilization and reduces overhead in a balanced way, with the memory access latency reduced by 80.7% on average, and guarantees the real-time capability of RTOS without negatively affecting the performance of GPOS.
{"title":"Work-in-Progress: a static partition for shared cache in mixed-time-sensitive system with balanced performance","authors":"Pan Yang, Pan Dong, Zhe Jiang, Jintao Xia, Yan Ding","doi":"10.1109/RTCSA52859.2021.00035","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00035","url":null,"abstract":"In modern safety-critical embedded systems (e.g., automotive/avionic systems), it is increasingly important to integrate components with different critical levels into one physical platform considering space, weight, and heat generation. The most common case is a mixed-time-sensitive system (MTSS), which is usually composed of an RTOS (Real-Time Operating System) and a GPOS (General-Purpose Operating System). In MTSS, cache sharing between RTOS and GPOS often causes inter-task interference, making WCET estimation overly pessimistic due to the increase of cache miss rate and task execution time variances. The existing cache management solutions, such as dynamic and static schemes, are challenging to be applied to MTSS. In this paper, we propose a novel practical method, termed cacheSPM, to eliminate the cache interference in MTSS. CacheSPM statically partitions cache resources during the compilation phase, effectively preventing the GPOS from influencing the cache resources belonged to the RTOS. Compared to the traditional partition schemes, cacheSPM has no intervention of memory manager and additional runtime overhead. Evaluation reveals that this method improves the memory utilization and reduces overhead in a balanced way, with the memory access latency reduced by 80.7% on average, and guarantees the real-time capability of RTOS without negatively affecting the performance of GPOS.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"12 1","pages":"210-212"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84622107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/rtcsa52859.2021.00003
{"title":"[Copyright notice]","authors":"","doi":"10.1109/rtcsa52859.2021.00003","DOIUrl":"https://doi.org/10.1109/rtcsa52859.2021.00003","url":null,"abstract":"","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"48 1","pages":""},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85122945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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