Most onboard embedded systems have real-time requirements. The SpaceFibre standard is developed for onboard local networks. However, the current version of the SpaceFibre standard does not specify any time synchronization mechanisms. The authors consider the mechanisms of time synchronization that are used in the data transmission standards, which are currently used for networks with real-time requirements. In the paper, the authors proposed possible time synchronization mechanisms for the SpaceFibre network, evaluate their characteristics. The authors proposed dynamically reconfigurable Local time controller for implementation of these mechanisms with ASIC.
{"title":"TIME SYNCHRONIZATION MECHANISMS FOR SPACEFIBRE NETWORKS AND THEIR IMPLEMENTATIONS","authors":"","doi":"10.4018/ijertcs.302109","DOIUrl":"https://doi.org/10.4018/ijertcs.302109","url":null,"abstract":"Most onboard embedded systems have real-time requirements. The SpaceFibre standard is developed for onboard local networks. However, the current version of the SpaceFibre standard does not specify any time synchronization mechanisms. The authors consider the mechanisms of time synchronization that are used in the data transmission standards, which are currently used for networks with real-time requirements. In the paper, the authors proposed possible time synchronization mechanisms for the SpaceFibre network, evaluate their characteristics. The authors proposed dynamically reconfigurable Local time controller for implementation of these mechanisms with ASIC.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":" ","pages":""},"PeriodicalIF":0.7,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47662880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Data mining is applied in various domains for extracting knowledge from domain data. The efficiency of DM algorithms usage in practice depends on the context including data characteristics, task requirements, and available resources. Semantic meta mining is the technique of building DM workflows through algorithm/model selection using a description framework that clarifies the complex relationships between tasks, data, and algorithms at different stages in the DM process. In this article, an architecture of semantic meta mining assistant for domain-oriented data processing is proposed. A case study applied proposed architecture on time series classification tasks is discussed.
{"title":"An architecture of the semantic meta mining assistant for adaptive domain-oriented data processing","authors":"","doi":"10.4018/ijertcs.302111","DOIUrl":"https://doi.org/10.4018/ijertcs.302111","url":null,"abstract":"Data mining is applied in various domains for extracting knowledge from domain data. The efficiency of DM algorithms usage in practice depends on the context including data characteristics, task requirements, and available resources. Semantic meta mining is the technique of building DM workflows through algorithm/model selection using a description framework that clarifies the complex relationships between tasks, data, and algorithms at different stages in the DM process. In this article, an architecture of semantic meta mining assistant for domain-oriented data processing is proposed. A case study applied proposed architecture on time series classification tasks is discussed.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"1 1","pages":""},"PeriodicalIF":0.7,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42499478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Encryption is an essential process in electronic data transmission because it securely protects the data from unauthorized access. In this digital era, information and its security are of great concern with technology advancements. As we have entered into 5G technology that targets end-to-end security and speed to communicate with intelligent devices. These devices and systems need an AES module having both the operation as encryption and decryption in a single module to communicate in duplex mode to access the information in a real-time environment. This article has architecture of a unified module with modified round operation and has been implemented on Virtex-7 FPGA platform. Mix column adds vertical alteration in the algorithm and this design has managed the utilization of Mix column block to make an optimized AES algorithm. The unified AES has achieved a maximum frequency of 290.3MHz and resource utilization of 9416 slice LUTs design, including some modification in traditional AES, resulting in less resource utilization and high throughput.
{"title":"An Improved Unified AES Implementation using FPGA","authors":"","doi":"10.4018/ijertcs.302110","DOIUrl":"https://doi.org/10.4018/ijertcs.302110","url":null,"abstract":"Encryption is an essential process in electronic data transmission because it securely protects the data from unauthorized access. In this digital era, information and its security are of great concern with technology advancements. As we have entered into 5G technology that targets end-to-end security and speed to communicate with intelligent devices. These devices and systems need an AES module having both the operation as encryption and decryption in a single module to communicate in duplex mode to access the information in a real-time environment. This article has architecture of a unified module with modified round operation and has been implemented on Virtex-7 FPGA platform. Mix column adds vertical alteration in the algorithm and this design has managed the utilization of Mix column block to make an optimized AES algorithm. The unified AES has achieved a maximum frequency of 290.3MHz and resource utilization of 9416 slice LUTs design, including some modification in traditional AES, resulting in less resource utilization and high throughput.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":" ","pages":""},"PeriodicalIF":0.7,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48641022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded systems are proceeding towards exploiting virtualization technology to have the benefits of Real-Time Operating System (RTOS) and General-Purpose Operating System (GPOS) in the same system. This combination provides both a timely and deterministic behavior and a general-purpose application codebase. There still exist concerns about the real-time responsiveness of RTOS running inside a Virtual Machine (VM). In this paper, the real-time performance of Kernel-based Virtual Machine (KVM) virtualization architecture is analyzed on a multi-core system. Here, a preemptible Linux kernel with the PREEMPT_RT patch is used for RTOS, while a standard Linux kernel is used for GPOS. The interrupt latency inside the real-time guest VM is analyzed by applying various amounts of CPU, memory, and I/O stresses on the guest and host systems. A VM resource monitoring tool ‘VM_stat’ is developed to know the resource usage of the guest VMs, which is useful for effectively tuning the system. Different real-time tuning measures are applied on the host/guest systems and the performance is analyzed.
{"title":"Real-Time Performance Analysis and Tuning of Embedded System Virtualization Architecture based on KVM","authors":"","doi":"10.4018/ijertcs.302113","DOIUrl":"https://doi.org/10.4018/ijertcs.302113","url":null,"abstract":"Embedded systems are proceeding towards exploiting virtualization technology to have the benefits of Real-Time Operating System (RTOS) and General-Purpose Operating System (GPOS) in the same system. This combination provides both a timely and deterministic behavior and a general-purpose application codebase. There still exist concerns about the real-time responsiveness of RTOS running inside a Virtual Machine (VM). In this paper, the real-time performance of Kernel-based Virtual Machine (KVM) virtualization architecture is analyzed on a multi-core system. Here, a preemptible Linux kernel with the PREEMPT_RT patch is used for RTOS, while a standard Linux kernel is used for GPOS. The interrupt latency inside the real-time guest VM is analyzed by applying various amounts of CPU, memory, and I/O stresses on the guest and host systems. A VM resource monitoring tool ‘VM_stat’ is developed to know the resource usage of the guest VMs, which is useful for effectively tuning the system. Different real-time tuning measures are applied on the host/guest systems and the performance is analyzed.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":" ","pages":""},"PeriodicalIF":0.7,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47388669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The article proposes a state forecasting method for telecommunications networks (TN) that is based on the analysis of behavioral models observed on users' network devices. The method applies user behavior that makes it possible to forecast with more accuracy both the network parameters and the load at various back-ends. Suggested forecasts facilitate implementing reasonable reconfiguration of the TN. The new method proposed as a further development of TN states the forecasting method presented by the authors before. In this new version, forecasting algorithm users' behavioral models are involved. The models refer to a class of time diagrams of device transitions between different states. The novelty of the proposed method is that resulting TN models enable forecasting device state transitions represented in a device state diagram in the form of knowledge graph, in particular changes in loads of different back-ends. The provided case study for a subgroup of network devices demonstrated how their states can be forecasted using behavioral models obtained from log files.
{"title":"Forecasting Telecommunication Network States on the Basis of Log Patterns Analysis and Knowledge Graphs Modeling","authors":"K. Krinkin, A. Vodyaho, I. Kulikov, N. Zhukova","doi":"10.4018/ijertcs.311464","DOIUrl":"https://doi.org/10.4018/ijertcs.311464","url":null,"abstract":"The article proposes a state forecasting method for telecommunications networks (TN) that is based on the analysis of behavioral models observed on users' network devices. The method applies user behavior that makes it possible to forecast with more accuracy both the network parameters and the load at various back-ends. Suggested forecasts facilitate implementing reasonable reconfiguration of the TN. The new method proposed as a further development of TN states the forecasting method presented by the authors before. In this new version, forecasting algorithm users' behavioral models are involved. The models refer to a class of time diagrams of device transitions between different states. The novelty of the proposed method is that resulting TN models enable forecasting device state transitions represented in a device state diagram in the form of knowledge graph, in particular changes in loads of different back-ends. The provided case study for a subgroup of network devices demonstrated how their states can be forecasted using behavioral models obtained from log files.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":" ","pages":""},"PeriodicalIF":0.7,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46404162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Improving smart environment communication remains a final unachievable destination. Continuous optimization in smart environment communication is mandatory because of an emerging number of connected devices. Carefully observing its parameters and demands leads to acknowledging existing challenges and boundaries regarding areas covered with signal and possibilities of approaching network architecture, limited battery resources in certain nodes of network architecture, privacy, and security of existing data transfer. One approach to dealing with these communication challenges and boundaries is focusing on important technical parameters respectively, signal processing speed, communication nodes distance, and communication channel security. The aim of this article is to point out these most important communication parameters in smart environments and how changing those can affect communication. Its original contribution is represented in establishing principles for governing security parameters by using permanent magnets in order to produce Faraday's rotation and thus manipulate the whole process of communication in a smart environment.
{"title":"One Approach to Improving Smart Environment Communication via the Security Parameter","authors":"Narves Behlilovic","doi":"10.4018/ijertcs.313042","DOIUrl":"https://doi.org/10.4018/ijertcs.313042","url":null,"abstract":"Improving smart environment communication remains a final unachievable destination. Continuous optimization in smart environment communication is mandatory because of an emerging number of connected devices. Carefully observing its parameters and demands leads to acknowledging existing challenges and boundaries regarding areas covered with signal and possibilities of approaching network architecture, limited battery resources in certain nodes of network architecture, privacy, and security of existing data transfer. One approach to dealing with these communication challenges and boundaries is focusing on important technical parameters respectively, signal processing speed, communication nodes distance, and communication channel security. The aim of this article is to point out these most important communication parameters in smart environments and how changing those can affect communication. Its original contribution is represented in establishing principles for governing security parameters by using permanent magnets in order to produce Faraday's rotation and thus manipulate the whole process of communication in a smart environment.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":" ","pages":""},"PeriodicalIF":0.7,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46500734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-31DOI: 10.1109/RTCSA55878.2022.00017
H. Zahaf, Nicola Capodieci
Real-time and latency sensitive applications such as autonomous driving, feature an increasing need of computational power that traditional multi-core platforms can not provide. For this purpose, many heterogeneous embedded platforms have been released recently. They offer a set of diverse processing elements (e.g. GPUs, DSPs, ASICs, etc...) in order to manage the computational demands of data hungry applications. The system engineer, therefore, can choose the fittest processing element for each specific subtask. In this context, timing constraints and related task models are of paramount importance.The HPC-DAG (Heterogeneous Parallel Directed Acyclic Graph) task model has been recently proposed to capture real-time workload execution on modern heterogeneous platforms. It expresses the Instruction Set Architecture (ISA) heterogeneity across the different compute accelerators, but also their differences in terms of possible scheduling policies such as preemption.In this paper, we propose a time-table scheduling approach to allocate and schedule a set of HPC-DAG tasks onto a set of heterogeneous cores, by the mean of Integer Linear Programming (ILP). Our design allows the system engineer to handle heterogeneity of resources, of on-line execution costs, and of a part of the tasks and sub-tasks allocation to cores. It improves the solving time compared to the state of the art by gradually exploring the design space.
{"title":"Building Time-Triggered Schedules for Typed-DAG Tasks with Alternative Implementations","authors":"H. Zahaf, Nicola Capodieci","doi":"10.1109/RTCSA55878.2022.00017","DOIUrl":"https://doi.org/10.1109/RTCSA55878.2022.00017","url":null,"abstract":"Real-time and latency sensitive applications such as autonomous driving, feature an increasing need of computational power that traditional multi-core platforms can not provide. For this purpose, many heterogeneous embedded platforms have been released recently. They offer a set of diverse processing elements (e.g. GPUs, DSPs, ASICs, etc...) in order to manage the computational demands of data hungry applications. The system engineer, therefore, can choose the fittest processing element for each specific subtask. In this context, timing constraints and related task models are of paramount importance.The HPC-DAG (Heterogeneous Parallel Directed Acyclic Graph) task model has been recently proposed to capture real-time workload execution on modern heterogeneous platforms. It expresses the Instruction Set Architecture (ISA) heterogeneity across the different compute accelerators, but also their differences in terms of possible scheduling policies such as preemption.In this paper, we propose a time-table scheduling approach to allocate and schedule a set of HPC-DAG tasks onto a set of heterogeneous cores, by the mean of Integer Linear Programming (ILP). Our design allows the system engineer to handle heterogeneity of resources, of on-line execution costs, and of a part of the tasks and sub-tasks allocation to cores. It improves the solving time compared to the state of the art by gradually exploring the design space.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"6 1","pages":"103-112"},"PeriodicalIF":0.7,"publicationDate":"2021-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88794766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00033
L. Cucu-Grosjean, A. Bar-Hen, Y. Sorel, Hadrien A. Clarke
Designers of embedded real-time systems derive, in general, their time parameters such as activation periods from those of sensors or actuators. By designers, we mean the team in charge of conceiving embedded real-time systems. This team includes Control Theory designers and Computer Science designers. Within this paper we present the point of view of Computer Science designers, while the periods proposed by Control Theory designers are supposed robust with respect to the physical behavior of the system. The execution times are, then, estimated by studying statically the programs structure or dynamically the programs execution. In some cases, both activation periods and execution times depend on a sensor information. For instance, they depend on the angular speed of wheels within an automotive embedded real-time system and such systems follow a rate-dependent model. Elastic tasks is another model, where one may consider execution time variation depending on the selected period. Within this paper, we are interested in describing statistically the relationship between activation periods and execution times of programs. More precisely, we study the impact of the period variation on the distributions of the execution times. To illustrate our preliminary results, we consider, as case study, the set of programs executing the autopilot of an open-source PX4 drone.
{"title":"Work-in-Progress Abstract: The impact of the period variation on execution time distributions of programs","authors":"L. Cucu-Grosjean, A. Bar-Hen, Y. Sorel, Hadrien A. Clarke","doi":"10.1109/RTCSA52859.2021.00033","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00033","url":null,"abstract":"Designers of embedded real-time systems derive, in general, their time parameters such as activation periods from those of sensors or actuators. By designers, we mean the team in charge of conceiving embedded real-time systems. This team includes Control Theory designers and Computer Science designers. Within this paper we present the point of view of Computer Science designers, while the periods proposed by Control Theory designers are supposed robust with respect to the physical behavior of the system. The execution times are, then, estimated by studying statically the programs structure or dynamically the programs execution. In some cases, both activation periods and execution times depend on a sensor information. For instance, they depend on the angular speed of wheels within an automotive embedded real-time system and such systems follow a rate-dependent model. Elastic tasks is another model, where one may consider execution time variation depending on the selected period. Within this paper, we are interested in describing statistically the relationship between activation periods and execution times of programs. More precisely, we study the impact of the period variation on the distributions of the execution times. To illustrate our preliminary results, we consider, as case study, the set of programs executing the autopilot of an open-source PX4 drone.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"516 1","pages":"204-206"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77117673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1109/RTCSA52859.2021.00034
S. Staroletov
Building robust software can be considered a major challenge in current software engineering processes. This task is especially relevant for the code of cyber-physical systems (CPS) that interact with tangible data of the environment and make decisions that have an impact on the real world. The study of good practices of the architectural organization of such software systems is suitable to conduct on solutions with open-source code, which are developed by large communities of enthusiasts. Such a code bears a long history and has been tested many times on real devices in a real-world environment. The construction of various models using the program code allows us to understand stable architectural solutions, to present them in a graphical form; these solutions can be used in STEM centers when designing other systems, taking into account all the achievements of the communities. In addition, it is possible to propose methods for analyzing models to prove various properties of cyber-physical systems. In this paper, we analyze ArduPilot Mega (APM), an Arduino-compatible solution for building DIY driving and flying systems. The solution is based on a specially designed board with a controller and necessary peripherals, as well as a firmware code in a C++ -compatible dialect. Since there are many limitations associated with hardware, it is advisable to carry out a so-called co-modeling, taking into account both hardware and software sides. We consider modeling the interaction of equipment on connected pins and data transmission buses, the software part in the form of a class diagram for the solution. We then describe methods for analyzing the interactions between tasks running on the system through shared variables and evaluating the performance of the task scheduler.
构建健壮的软件可以被认为是当前软件工程过程中的一个主要挑战。这项任务与网络物理系统(CPS)的代码特别相关，这些系统与环境的有形数据相互作用，并做出对现实世界有影响的决策。对这类软件系统的架构组织的良好实践的研究适合于对由大型爱好者社区开发的开源代码的解决方案进行研究。这样的代码有很长的历史，并且已经在真实环境中的真实设备上进行了多次测试。使用程序代码构建各种模型使我们能够理解稳定的架构解决方案，并以图形形式呈现它们;这些解决方案可以在STEM中心设计其他系统时使用，同时考虑到社区的所有成就。此外，还可以提出分析模型的方法来证明网络物理系统的各种特性。在本文中，我们分析了ArduPilot Mega (APM)，一个arduino兼容的解决方案，用于构建DIY驾驶和飞行系统。该解决方案基于一个特殊设计的电路板，带有控制器和必要的外围设备，以及c++兼容方言的固件代码。由于存在与硬件相关的许多限制，因此建议执行所谓的协同建模，同时考虑硬件和软件方面。我们考虑对连接的引脚和数据传输总线上的设备的交互进行建模，软件部分以类图的形式提供解决方案。然后，我们描述了通过共享变量分析系统上运行的任务之间的交互以及评估任务调度器性能的方法。
{"title":"Work-in-Progress Abstract: Revealing and Analyzing Architectural Models in Open-source ArduPilot","authors":"S. Staroletov","doi":"10.1109/RTCSA52859.2021.00034","DOIUrl":"https://doi.org/10.1109/RTCSA52859.2021.00034","url":null,"abstract":"Building robust software can be considered a major challenge in current software engineering processes. This task is especially relevant for the code of cyber-physical systems (CPS) that interact with tangible data of the environment and make decisions that have an impact on the real world. The study of good practices of the architectural organization of such software systems is suitable to conduct on solutions with open-source code, which are developed by large communities of enthusiasts. Such a code bears a long history and has been tested many times on real devices in a real-world environment. The construction of various models using the program code allows us to understand stable architectural solutions, to present them in a graphical form; these solutions can be used in STEM centers when designing other systems, taking into account all the achievements of the communities. In addition, it is possible to propose methods for analyzing models to prove various properties of cyber-physical systems. In this paper, we analyze ArduPilot Mega (APM), an Arduino-compatible solution for building DIY driving and flying systems. The solution is based on a specially designed board with a controller and necessary peripherals, as well as a firmware code in a C++ -compatible dialect. Since there are many limitations associated with hardware, it is advisable to carry out a so-called co-modeling, taking into account both hardware and software sides. We consider modeling the interaction of equipment on connected pins and data transmission buses, the software part in the form of a class diagram for the solution. We then describe methods for analyzing the interactions between tasks running on the system through shared variables and evaluating the performance of the task scheduler.","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"29 1","pages":"207-209"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82583185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-01DOI: 10.1007/s11241-022-09391-w
Guangli Dai, Pavan Kumar Paluri, A. Cheng
{"title":"Enhanced Schedulability Tests for Real-Time Regularity-Based Virtualized Systems with Dependent and Self-Suspension Tasks","authors":"Guangli Dai, Pavan Kumar Paluri, A. Cheng","doi":"10.1007/s11241-022-09391-w","DOIUrl":"https://doi.org/10.1007/s11241-022-09391-w","url":null,"abstract":"","PeriodicalId":38446,"journal":{"name":"International Journal of Embedded and Real-Time Communication Systems (IJERTCS)","volume":"4 1","pages":"51-60"},"PeriodicalIF":0.7,"publicationDate":"2021-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72907684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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