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2012 13th International Workshop on Cellular Nanoscale Networks and their Applications最新文献

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Memory access optimization for computations on unstructured meshes 非结构化网格计算的内存访问优化
Antal Hiba, Zoltán Nagy, Miklos Ruszinko
Many real-life applications of processor-arrays suffer from memory bandwidth limitations. In many cases an unstructured mesh is given (computation on sensor data, simulations of physical systems - PDEs), where the vertices represent computations with dependencies represented by the edges. Utilization of processing elements (PEs) during these computations is mainly depends on the node indexing of the mesh. If the adjacent nodes are stored close to each other in main memory, the reloading of node data can be significantly decreased. In case of FPGA the memory accesses can be fully determined by the designer. The mesh and an ordering of its nodes, define the graph bandwidth, which determines the minimum size of on-chip memory to avoid reloading of the nodes from the off-chip memory. If the required on-chip memory size is higher than the available resources, the mesh must be divided into parts. In this paper a novel geometry-based method is presented, which constructs reordered parts from a given unstructured mesh, where each part meets some predefined constraints on graph bandwidth.
处理器阵列的许多实际应用都受到内存带宽限制的影响。在许多情况下,给出了一个非结构化网格(传感器数据的计算,物理系统的模拟- PDEs),其中顶点表示由边缘表示的依赖关系的计算。在这些计算过程中,处理单元(PEs)的利用率主要取决于网格的节点索引。如果相邻节点在主存中存储得很近,可以显著减少节点数据的重载。对于FPGA,存储器的访问完全可以由设计者决定。网格及其节点的排序定义了图带宽,它决定了片上存储器的最小大小,以避免从片外存储器重新加载节点。如果所需的片上内存大小高于可用资源,则必须将网格划分为多个部分。本文提出了一种新的基于几何的方法,该方法从给定的非结构化网格中构造重新排序的部分,其中每个部分满足预定义的图带宽约束。
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引用次数: 1
Realization of a fully configurable complex network of non linear Chua's oscillators 一个完全可配置的非线性蔡氏振荡器复杂网络的实现
M. Colandrea, M. Magistris, C. Petrarca, M. Bernardo, S. Manfredi
We describe the realization of a new experimental setup for the analysis and characterization of complex networks of Chua's circuits. It is characterized by full configurability of the node's parameters and the network structure (topology and link impedances), and designed for easy scalability to high number of nodes. The set-up is automated in terms of control of the network and data acquisition by means of USB interfaced boards. A portable version of the set-up with 8 nodes is realized for demonstration purposes.
我们描述了一种新的实验装置的实现,用于分析和表征蔡氏电路的复杂网络。它的特点是节点参数和网络结构(拓扑和链路阻抗)的完全可配置性,并且易于扩展到大量节点。该装置在网络控制和通过USB接口板采集数据方面是自动化的。为了演示目的,实现了具有8个节点的可移植版本。
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引用次数: 0
Coarse grain mapping method for image processing on fine grain cellular processor arrays 细粒元胞处理器阵列上图像处理的粗粒映射方法
Bin Wang, P. Dudek
This paper introduces a mapping method for adding a coarse grain (multiple pixels per processor) processing mode to massively parallel cellular processor arrays. The main motivation is to provide the fine grain pixel-parallel processor array with the ability of processing images with higher resolution than the array itself, in a way that is transparent to the programmer. The proposed method accomplishes the mapping work entirely during the code compilation process, which has four main advantages. Firstly, there is no extra overhead during processing. Secondly, the source code for fine grain mode can be used in coarse grain mode without modification. Thirdly, the proposed method does not introduce any restrictions of the number of pixels stored in a processing element. Finally, the proposed method is easy to implement, as it does not require any modifications to the hardware design of the pixel-parallel processor array or its controller, but only to the software compiler. The mapping method and its software implementation are presented in this paper.
本文介绍了一种将粗粒度(每处理器多像素)处理模式添加到大规模并行蜂窝处理器阵列的映射方法。其主要动机是提供细粒度像素并行处理器阵列,使其能够以一种对程序员透明的方式处理比阵列本身更高分辨率的图像。该方法完全在代码编译过程中完成映射工作,具有四个主要优点。首先,在处理期间没有额外的开销。其次,细粒模式的源代码无需修改即可用于粗粒模式。第三,所提出的方法不引入存储在处理单元中的像素数的任何限制。最后,该方法易于实现,不需要修改像素并行处理器阵列及其控制器的硬件设计,只需要修改软件编译器。本文给出了映射方法及其软件实现。
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引用次数: 5
Demo: An improved FPGA implementation of CNN Gabor-type Filters 演示:CNN gabor型滤波器的改进FPGA实现
E. Cesur, N. Yildiz, V. Tavsanoglu
In this paper, a new Cellular Neural Network (CNN) structure for implementing two dimensional Gabor-type filters is proposed over our previous design. The structure is coded in VHDL and realized on a state of the art Altera Stratix IV 230 FPGA. The prototype supports Full-HD 1080p resolution and 60 Hz frame rate. One dedicated processor is used for each Euler iteration, where time step is taken as the same as optimum step size, and 50 iterations are implemented. The input/output, control, RAM and communication blocks of the realization are taken from our second generation real time CNN emulator (RTCNNP-v2).
本文提出了一种新的细胞神经网络(CNN)结构,用于实现二维gabor型滤波器。该结构用VHDL编码,并在Altera Stratix iv230 FPGA上实现。原型机支持全高清1080p分辨率和60hz帧率。每个Euler迭代使用一个专用处理器,其中时间步长与最佳步长相同,并实现50个迭代。实现的输入/输出、控制、RAM和通信模块均取自我们的第二代实时CNN模拟器(RTCNNP-v2)。
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引用次数: 3
期刊
2012 13th International Workshop on Cellular Nanoscale Networks and their Applications
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