Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331418
J. Albó-Canals, G. E. Pazienza
Time-Derivative CNNs (TDCNNs) have been recently proposed as a novel paradigm realizing spatiotemporal transfer functions for linear filtering. Their dynamics is usually simulated with SIMULINK because VLSI chips are still in the preliminary phase. In order to make TDCNNs available to a larger audience, we present here their implementation on a Xilinx Spartan-6 FPGA. The results concerning an 8×8 network are promising and consistent with the SW simulations.
{"title":"Implementing Time-Derivative CNNs on a Xilinx Spartan FPGA","authors":"J. Albó-Canals, G. E. Pazienza","doi":"10.1109/CNNA.2012.6331418","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331418","url":null,"abstract":"Time-Derivative CNNs (TDCNNs) have been recently proposed as a novel paradigm realizing spatiotemporal transfer functions for linear filtering. Their dynamics is usually simulated with SIMULINK because VLSI chips are still in the preliminary phase. In order to make TDCNNs available to a larger audience, we present here their implementation on a Xilinx Spartan-6 FPGA. The results concerning an 8×8 network are promising and consistent with the SW simulations.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127804675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331423
V. Tavsanoglu, S. N. Tural Polat
In this paper 2-D discrete-space filters are generated from their analog counterparts and implemented by Cellular Neural Networks (CNN). To this end, first 2-D analog transfer functions are obtained from their 1-D counterparts. Then, the corresponding difference equations are obtained by discretization of 2-D analog filter differential equations, which are then implemented by CNN. Simulation results are presented.
{"title":"2nd order 2-D spatial filters and Cellular Neural Network implementations","authors":"V. Tavsanoglu, S. N. Tural Polat","doi":"10.1109/CNNA.2012.6331423","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331423","url":null,"abstract":"In this paper 2-D discrete-space filters are generated from their analog counterparts and implemented by Cellular Neural Networks (CNN). To this end, first 2-D analog transfer functions are obtained from their 1-D counterparts. Then, the corresponding difference equations are obtained by discretization of 2-D analog filter differential equations, which are then implemented by CNN. Simulation results are presented.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115276889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331416
Renyuan Zhang, T. Shibata
A feasibility study of VLSI hardware implementation of support vector domain description (SVDD) has been done in this work. The on-chip learning operation of SVDD algorithm was implemented by an analog Gaussian-cell array. By using a compact analog Gaussian-generation circuit, the center, height and width of the generated Gaussian kernel function feature can be programmed. Based on this Gaussian-generation circuit, a fully parallel architecture is developed to implement the on-chip learning operation, which is carried out by the proposed method. In this manner, the learning operation autonomously proceeds without any clock-based iteration, and self-converges with a high speed. A proof-of-concept processor is designed for sixteen learning sample vectors. From the circuit simulation results, the entire learning operation is accomplished within 0.6 μs, and the domain of sample space is described by a reduced number of sample vectors. In addition, the various forms of domain description can be realized by tuning the kernel function feature dynamically.
{"title":"A VLSI hardware implementation study of SVDD algorithm using analog Gaussian-cell array for on-chip learning","authors":"Renyuan Zhang, T. Shibata","doi":"10.1109/CNNA.2012.6331416","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331416","url":null,"abstract":"A feasibility study of VLSI hardware implementation of support vector domain description (SVDD) has been done in this work. The on-chip learning operation of SVDD algorithm was implemented by an analog Gaussian-cell array. By using a compact analog Gaussian-generation circuit, the center, height and width of the generated Gaussian kernel function feature can be programmed. Based on this Gaussian-generation circuit, a fully parallel architecture is developed to implement the on-chip learning operation, which is carried out by the proposed method. In this manner, the learning operation autonomously proceeds without any clock-based iteration, and self-converges with a high speed. A proof-of-concept processor is designed for sixteen learning sample vectors. From the circuit simulation results, the entire learning operation is accomplished within 0.6 μs, and the domain of sample space is described by a reduced number of sample vectors. In addition, the various forms of domain description can be realized by tuning the kernel function feature dynamically.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331441
L. Orzó, A. Fehér, S. Tõkés
Background estimation and elimination is an indispensable step of hologram processing. Its application ensures that the fix pattern noise caused by the deposits, dirt and other impurities of the measuring chamber and the optical system do not contaminate the reconstructed holograms and improves the efficiency of the object segmentation. It is conventionally solved by averaging large number of holograms with altering objects within the flow-through cell. Due to the possible illumination changes the background should be updated incessantly during the hologram measuring process. Here we introduce an improved background estimation method where the holographic contributions of the segmented and reconstructed objects are excluded from the running average. The applied segmentation is based on the 3D positions of the objects within the flow-through measuring chamber. Therefore the objects can be distinguished from the impurities and deposits, which customary located at the walls of the measuring chamber. This way, an elevated speed, more adaptive background estimation becomes achievable with reduced noise. The applied object segmentation and hologram subtraction methods are presented also. To accelerate the processing of the measured holograms the application of some parallel computing implementation seems essential. Using stream processors (GPU) we were able to increase the algorithm speed considerably, without perceptible reconstruction accuracy loss.
{"title":"Advanced background elimination in digital holographic microscopy","authors":"L. Orzó, A. Fehér, S. Tõkés","doi":"10.1109/CNNA.2012.6331441","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331441","url":null,"abstract":"Background estimation and elimination is an indispensable step of hologram processing. Its application ensures that the fix pattern noise caused by the deposits, dirt and other impurities of the measuring chamber and the optical system do not contaminate the reconstructed holograms and improves the efficiency of the object segmentation. It is conventionally solved by averaging large number of holograms with altering objects within the flow-through cell. Due to the possible illumination changes the background should be updated incessantly during the hologram measuring process. Here we introduce an improved background estimation method where the holographic contributions of the segmented and reconstructed objects are excluded from the running average. The applied segmentation is based on the 3D positions of the objects within the flow-through measuring chamber. Therefore the objects can be distinguished from the impurities and deposits, which customary located at the walls of the measuring chamber. This way, an elevated speed, more adaptive background estimation becomes achievable with reduced noise. The applied object segmentation and hologram subtraction methods are presented also. To accelerate the processing of the measured holograms the application of some parallel computing implementation seems essential. Using stream processors (GPU) we were able to increase the algorithm speed considerably, without perceptible reconstruction accuracy loss.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114892632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331413
M. Niemier, G. Csaba, A. Dingler, X. Hu, W. Porod, X. Ju, M. Becherer, Doris Schmitt-Landsiedel, Paolo Lugli
We present the design and simulation of information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic - or oNML). We first describe the design and evaluation of oNML hardware that can identify instances of a preprogrammed bit sequence in streaming data. Systolic arrays (that process information using Boolean logic gates) are employed as a system-level architecture which can (i) mitigate less desirable features of the oNML device architecture (nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor), and (ii) exploit unique features of the device architecture (non-volatility and inherently pipelined logic with no overhead). We conclude the paper with a discussion as to how oNML might be employed for non-Boolean information processing. A simple image processing function is used as an initial case study.
{"title":"Boolean and non-boolean nearest neighbor architectures for out-of-plane nanomagnet logic","authors":"M. Niemier, G. Csaba, A. Dingler, X. Hu, W. Porod, X. Ju, M. Becherer, Doris Schmitt-Landsiedel, Paolo Lugli","doi":"10.1109/CNNA.2012.6331413","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331413","url":null,"abstract":"We present the design and simulation of information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic - or oNML). We first describe the design and evaluation of oNML hardware that can identify instances of a preprogrammed bit sequence in streaming data. Systolic arrays (that process information using Boolean logic gates) are employed as a system-level architecture which can (i) mitigate less desirable features of the oNML device architecture (nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor), and (ii) exploit unique features of the device architecture (non-volatility and inherently pipelined logic with no overhead). We conclude the paper with a discussion as to how oNML might be employed for non-Boolean information processing. A simple image processing function is used as an initial case study.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114893646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331476
V. Mladenov, S. Kirilov
In the present paper the structure and principle of action of Williams's memristor are described. There are presented its basic parameters and the basic physical dependencies are confirmed. The analysis described here considers linear drift model of Williams's memristor. A SIMULINK model of circuit with two memristors is build with obtained formulae and Kirchhoff's voltage law. The basic results by the simulations organized in MATLAB and SIMULINK environment are given in graphical form. These results are associated with distortions of plateaus of impulses at different ratios between resistances of “opened” and “closed” states of Williams's memristor - ROFF and RON. There are given also interpreting of results, which confirms that a memristor with high ratio r is better than a memristor with small value of r. In conclusion there are given basic deductions and perspectives for future applications of memristor circuits.
{"title":"Analysis of a serial circuit with two memristors and voltage source at sine and impulse regime","authors":"V. Mladenov, S. Kirilov","doi":"10.1109/CNNA.2012.6331476","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331476","url":null,"abstract":"In the present paper the structure and principle of action of Williams's memristor are described. There are presented its basic parameters and the basic physical dependencies are confirmed. The analysis described here considers linear drift model of Williams's memristor. A SIMULINK model of circuit with two memristors is build with obtained formulae and Kirchhoff's voltage law. The basic results by the simulations organized in MATLAB and SIMULINK environment are given in graphical form. These results are associated with distortions of plateaus of impulses at different ratios between resistances of “opened” and “closed” states of Williams's memristor - ROFF and RON. There are given also interpreting of results, which confirms that a memristor with high ratio r is better than a memristor with small value of r. In conclusion there are given basic deductions and perspectives for future applications of memristor circuits.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127792285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331405
A. Slavova, P. Zecca
In this paper CNN modeling of tsunami waves is presented. Two models are studied: two-component Camassa-Holm type equation is studied and generalized KdV equation. For these cases CNN models are constructed and traveling wave solutions are obtained theoretically and via simulations. New type of traveling wave solutions are introduced - peak type, called peakon. Discussion and example of tsunami waves are provided at the end of the paper.
{"title":"Cellular Neural Networks modeling of tsunami waves","authors":"A. Slavova, P. Zecca","doi":"10.1109/CNNA.2012.6331405","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331405","url":null,"abstract":"In this paper CNN modeling of tsunami waves is presented. Two models are studied: two-component Camassa-Holm type equation is studied and generalized KdV equation. For these cases CNN models are constructed and traveling wave solutions are obtained theoretically and via simulations. New type of traveling wave solutions are introduced - peak type, called peakon. Discussion and example of tsunami waves are provided at the end of the paper.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"29 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123217788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331433
Kyoungrok Cho, Sang-Jin Lee, Kwang-Seok Oh, Ca-Ram Han, O. Kavehei, K. Eshraghian
Emergence of new materials and in particular the recent progress in Memristor and related memory technologies encouraged the research community for a renewed approach towards formulation of architectures such as those that depend upon associate memory constructs to take the advantages being offered within this new design domain. In this paper we address a key issue in pattern matching and classification process and hence suggest an alternative approach for image vector matching combining Complementary Resistive Switch (CRS) array and bump circuits. We emulated an experimental pattern matching with two approaches which are based on Hamming distance and threshold level of the image: the former finds an exact image with a bump circuit and the later finds similar patterns from the stored images combining comparators. The proposed hardware oriented architecture is high speed and smaller size that is easier to implement on conventional CMOS technology.
{"title":"Pattern matching and classification based on an associative memory architecture using CRS","authors":"Kyoungrok Cho, Sang-Jin Lee, Kwang-Seok Oh, Ca-Ram Han, O. Kavehei, K. Eshraghian","doi":"10.1109/CNNA.2012.6331433","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331433","url":null,"abstract":"Emergence of new materials and in particular the recent progress in Memristor and related memory technologies encouraged the research community for a renewed approach towards formulation of architectures such as those that depend upon associate memory constructs to take the advantages being offered within this new design domain. In this paper we address a key issue in pattern matching and classification process and hence suggest an alternative approach for image vector matching combining Complementary Resistive Switch (CRS) array and bump circuits. We emulated an experimental pattern matching with two approaches which are based on Hamming distance and threshold level of the image: the former finds an exact image with a bump circuit and the later finds similar patterns from the stored images combining comparators. The proposed hardware oriented architecture is high speed and smaller size that is easier to implement on conventional CMOS technology.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131394471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1007/978-3-319-02630-5_28
T. Asai
{"title":"Reaction-diffusion media with excitable oregonators coupled by memristors","authors":"T. Asai","doi":"10.1007/978-3-319-02630-5_28","DOIUrl":"https://doi.org/10.1007/978-3-319-02630-5_28","url":null,"abstract":"","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131873245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331431
T. Zsedrovits, Á. Zarándy, B. Vanek, T. Péni, J. Bokor, T. Roska
Visual detection based sense and avoid problem is more and more important nowadays as UAVs are getting closer to entering remotely piloted or autonomously into the airspace. It is critical to gain as much information as possible from the silhouettes of the distant aircrafts. In our paper, we investigate the reachable accuracy of the orientation information of remote planes under different geometrical condition, by identifying their wing lines from their detected wingtips. Under the assumption that the remote airplane is on a straight course, the error of the spatial discretization (pixelization), and the automatic detection error is calculated.
{"title":"Azimuth estimation of distant, approaching airplane in See-and-avoid Systems","authors":"T. Zsedrovits, Á. Zarándy, B. Vanek, T. Péni, J. Bokor, T. Roska","doi":"10.1109/CNNA.2012.6331431","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331431","url":null,"abstract":"Visual detection based sense and avoid problem is more and more important nowadays as UAVs are getting closer to entering remotely piloted or autonomously into the airspace. It is critical to gain as much information as possible from the silhouettes of the distant aircrafts. In our paper, we investigate the reachable accuracy of the orientation information of remote planes under different geometrical condition, by identifying their wing lines from their detected wingtips. Under the assumption that the remote airplane is on a straight course, the error of the spatial discretization (pixelization), and the automatic detection error is calculated.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131810428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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