Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331406
M. Di Marco, M. Forti, M. Grazzini, L. Pancioni
The paper considers the full-range (FR) model of cellular neural networks (CNNs) with ideal hard-limiter non-linearities that limit the allowable range of the neuron state variables. It is also supposed that there is a concentrated delay (D) in the neuron interconnections. Due to the presence of multivalued nonlinearities the D-FRCNN model is mathematically described by a retarded differential inclusion. The main result is a rigorous proof that, in the case of nonsymmetric cooperative (nonnegative) interconnections, and delayed interconnections, the semiflow generated by D-FRCNNs is monotone, and that monotonicity implies some basic restrictions on the long-term behavior of the solutions. The result is compared with recent results in the literature on semiflows generated by cooperative standard CNNs, with and without delays.
{"title":"Monotonicity of semiflows generated by cooperative delayed full-range CNNs","authors":"M. Di Marco, M. Forti, M. Grazzini, L. Pancioni","doi":"10.1109/CNNA.2012.6331406","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331406","url":null,"abstract":"The paper considers the full-range (FR) model of cellular neural networks (CNNs) with ideal hard-limiter non-linearities that limit the allowable range of the neuron state variables. It is also supposed that there is a concentrated delay (D) in the neuron interconnections. Due to the presence of multivalued nonlinearities the D-FRCNN model is mathematically described by a retarded differential inclusion. The main result is a rigorous proof that, in the case of nonsymmetric cooperative (nonnegative) interconnections, and delayed interconnections, the semiflow generated by D-FRCNNs is monotone, and that monotonicity implies some basic restrictions on the long-term behavior of the solutions. The result is compared with recent results in the literature on semiflows generated by cooperative standard CNNs, with and without delays.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"57 6 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116518139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331467
D. Barr, S. Carey, P. Dudek
A low-power demonstration system using a SCAMP-3 vision chip to track and count multiple objects with unpredictable trajectories is presented. The system can track as many discrete objects that can fit into its visual field. The compact, self-contained hardware consists of a battery, an ARM Cortex-M3 coprocessor, and the sensor/processor array device. The tracking algorithm is performed entirely by the processor array and the complete system draws 7.3mA during operation.
{"title":"Low power multiple object tracking and counting using a SCAMP cellular processor array","authors":"D. Barr, S. Carey, P. Dudek","doi":"10.1109/CNNA.2012.6331467","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331467","url":null,"abstract":"A low-power demonstration system using a SCAMP-3 vision chip to track and count multiple objects with unpredictable trajectories is presented. The system can track as many discrete objects that can fit into its visual field. The compact, self-contained hardware consists of a battery, an ARM Cortex-M3 coprocessor, and the sensor/processor array device. The tracking algorithm is performed entirely by the processor array and the complete system draws 7.3mA during operation.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123427772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331452
Shuang Pi, P. Lin, Q. Xia
We used diluted hydrofluoric acid to shrink the feature size of a silicon dioxide nanoimprint mold to sub-10 nm regime. Using this mold, we have fabricated memristor crossbar arrays using nanoimprint lithography. We demonstrated that memristor devices with small junction areas exhibited bipolar non-volatile switching behavior with high ON/OFF ratio and low operational current.
{"title":"Memristor crossbar arrays with junction areas towards sub-10 × 10 nm2","authors":"Shuang Pi, P. Lin, Q. Xia","doi":"10.1109/CNNA.2012.6331452","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331452","url":null,"abstract":"We used diluted hydrofluoric acid to shrink the feature size of a silicon dioxide nanoimprint mold to sub-10 nm regime. Using this mold, we have fabricated memristor crossbar arrays using nanoimprint lithography. We demonstrated that memristor devices with small junction areas exhibited bipolar non-volatile switching behavior with high ON/OFF ratio and low operational current.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121708746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331404
L. Nicolosi, R. Tetzlaff, F. Abt, A. Blug, H. Höfler
Laser beam welding (LBW) has been largely used in manufacturing processes ranging from automobile production to precision mechanics. The complexity of LBW requires the development of strategies for the real-time control of the process. Most of the available feedback systems lack of temporal and/or spatial resolution and, therefore, they hardly allow observing more than one characteristic of the process. In the last years, we proposed some high-speed visual algorithms for image feature extraction from process images. The detection of the full penetration hole (FPH) allowed controlling the laser power at rates of up to 14 kHz. Another strategy enables observing the occurrence of spatters at monitoring rates of 15 kHz. The achievement of these results was made possible by the adoption of a visual system including a focal plane processor programmable by typical Cellular Neural Network (CNN) operations. This paper is focused on a new visual algorithm for the simultaneous detection of FPH and spatters, which led to real-time control rates of about 8 kHz. Besides the algorithm description, some interesting experimental results will be presented.
{"title":"Multi-feature detection for quality assessment in laser beam welding: Experimental results","authors":"L. Nicolosi, R. Tetzlaff, F. Abt, A. Blug, H. Höfler","doi":"10.1109/CNNA.2012.6331404","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331404","url":null,"abstract":"Laser beam welding (LBW) has been largely used in manufacturing processes ranging from automobile production to precision mechanics. The complexity of LBW requires the development of strategies for the real-time control of the process. Most of the available feedback systems lack of temporal and/or spatial resolution and, therefore, they hardly allow observing more than one characteristic of the process. In the last years, we proposed some high-speed visual algorithms for image feature extraction from process images. The detection of the full penetration hole (FPH) allowed controlling the laser power at rates of up to 14 kHz. Another strategy enables observing the occurrence of spatters at monitoring rates of 15 kHz. The achievement of these results was made possible by the adoption of a visual system including a focal plane processor programmable by typical Cellular Neural Network (CNN) operations. This paper is focused on a new visual algorithm for the simultaneous detection of FPH and spatters, which led to real-time control rates of about 8 kHz. Besides the algorithm description, some interesting experimental results will be presented.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125625310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331409
Jens Müller, Ralf Becker, Jan Müller, R. Tetzlaff
Complex dynamical systems establish offer entirely new possibilities to the development of groundbreaking data processing methods. In the domains of image and video processing, locally coupled cellular array computers, based on Cellular Nonlinear Networks (CNN), accelerate the computation of large amounts of data in real-time, due to their inherent concept of massive parallelism. Current VLSI implementations however, are accompanied by several distinct drawbacks. The computational accuracy of most currently available systems is limited to 8 bit, and the volatilely capacitively stored state values of analogue realisations often lead to errors when multiple tasks are processed sequentially. Moreover, the systems hardly allow to run a CNN program code to provide the full functionality of a CNN-UM. In this contribution, the novel CESAR architecture is proposed for the digital emulation of a time-discrete CNN-UM. The programmable array computer facilitates the powerful computation of consecutive CNN operations and the cost-efficient implementation of several application-specific configurations with variable network size and data representation. The presented architecture retains the inherent parallel paradigm of CNN, and assigns one processing element to each cell of the network. The cell outputs are coupled and stored locally, thus minimising data exchange with external structures and maximising the computation speed. The internal fixed-point multiplications are accelerated by using on-chip DSP resources provided by current FPGAs. By this means, a CNN-based embedded system with 128 cells, a 3 × 3 neighbourhood and 18 bit data representation was implemented on a Xilinx Virtex-5 FPGA.
{"title":"CESAR: Emulating Cellular Networks on FPGA","authors":"Jens Müller, Ralf Becker, Jan Müller, R. Tetzlaff","doi":"10.1109/CNNA.2012.6331409","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331409","url":null,"abstract":"Complex dynamical systems establish offer entirely new possibilities to the development of groundbreaking data processing methods. In the domains of image and video processing, locally coupled cellular array computers, based on Cellular Nonlinear Networks (CNN), accelerate the computation of large amounts of data in real-time, due to their inherent concept of massive parallelism. Current VLSI implementations however, are accompanied by several distinct drawbacks. The computational accuracy of most currently available systems is limited to 8 bit, and the volatilely capacitively stored state values of analogue realisations often lead to errors when multiple tasks are processed sequentially. Moreover, the systems hardly allow to run a CNN program code to provide the full functionality of a CNN-UM. In this contribution, the novel CESAR architecture is proposed for the digital emulation of a time-discrete CNN-UM. The programmable array computer facilitates the powerful computation of consecutive CNN operations and the cost-efficient implementation of several application-specific configurations with variable network size and data representation. The presented architecture retains the inherent parallel paradigm of CNN, and assigns one processing element to each cell of the network. The cell outputs are coupled and stored locally, thus minimising data exchange with external structures and maximising the computation speed. The internal fixed-point multiplications are accelerated by using on-chip DSP resources provided by current FPGAs. By this means, a CNN-based embedded system with 128 cells, a 3 × 3 neighbourhood and 18 bit data representation was implemented on a Xilinx Virtex-5 FPGA.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125721993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331450
Declan Walsh, Piotr Dudek
An FPGA implementation of a fine grain general-purpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 × 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bit-serial operations). Binary and 8-bit greyscale image processing is performed and demonstrated.
{"title":"A compact FPGA implementation of a bit-serial SIMD cellular processor array","authors":"Declan Walsh, Piotr Dudek","doi":"10.1109/CNNA.2012.6331450","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331450","url":null,"abstract":"An FPGA implementation of a fine grain general-purpose SIMD processor array is presented. The processor architecture has a compact processing element which is encapsulated into two configurable logic blocks (CLBs) and is then replicated to form an array. A 32 × 32 processing element array is implemented on a low-cost Xilinx XC5VLX50 FPGA using four-neighbour connectivity with the possibility to scale up using a larger FPGA. The processor array operates at a frequency of 150 MHz and executes a peak of 153.6 GOPS (bit-serial operations). Binary and 8-bit greyscale image processing is performed and demonstrated.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129209069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331444
Yuhao Wang, Wei Fei, Hao Yu
Memristor is a two-terminal non-linear passive electrical device. After its recently successful fabrication, a variety of applications based on memristor have been explored, such as non-volatile memory, reconfigurable computing and neural network. However, one major challenge when designing hybrid CMOS memristor integrated circuit is the lack of SPICE-like simulator for design validation. Current approach is to describe memristor device with equivalent circuit, which is however extremely time-consuming for large scale design simulation due to additional modeling components. In this paper, a memristor SPICE simulator is introduced based on the recent new modified nodal analysis (MNA) framework, which can effectively support the non-conventional state variable such as doping ratio of memristor. As such, the memristor device can be stamped into state matrix similarly as one BSIM MOSFET. Compared with equivalent circuit simulation approach, our new MNA based approach exhibits 40x less simulation time for a 32×32 memristor crossbar circuit. A hybrid CMOS memristor circuit for classic conditioning training has also been studied by the developed SPICE simulator.
{"title":"SPICE simulator for hybrid CMOS memristor circuit and system","authors":"Yuhao Wang, Wei Fei, Hao Yu","doi":"10.1109/CNNA.2012.6331444","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331444","url":null,"abstract":"Memristor is a two-terminal non-linear passive electrical device. After its recently successful fabrication, a variety of applications based on memristor have been explored, such as non-volatile memory, reconfigurable computing and neural network. However, one major challenge when designing hybrid CMOS memristor integrated circuit is the lack of SPICE-like simulator for design validation. Current approach is to describe memristor device with equivalent circuit, which is however extremely time-consuming for large scale design simulation due to additional modeling components. In this paper, a memristor SPICE simulator is introduced based on the recent new modified nodal analysis (MNA) framework, which can effectively support the non-conventional state variable such as doping ratio of memristor. As such, the memristor device can be stamped into state matrix similarly as one BSIM MOSFET. Compared with equivalent circuit simulation approach, our new MNA based approach exhibits 40x less simulation time for a 32×32 memristor crossbar circuit. A hybrid CMOS memristor circuit for classic conditioning training has also been studied by the developed SPICE simulator.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127987227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331417
M. Bonnin, F. Corinto, M. Gilli
Oscillatory nonlinear networks represent a circuit architecture for image and information processing. It has been shown that they can be exploited to implement associative and dynamic memories. It has also been shown that phase noise play an important role as a limiting key factor for the performances of oscillatory cells. A tool of paramount importance for the design of oscillatory networks and the analysis of phase noise are phase models. These models require to treat the noise and the couplings among the cells as perturbations, and to identify the proper directions along which project the perturbations. In this paper we discuss the proper decomposition of the phase space for second order cells of oscillatory nonlinear networks, and we derive analytical formulas for the vectors spanning the directions for the proper phase space decomposition. We also discuss the implications of this decomposition in control theory and to what extent a simple orthogonal projection is correct.
{"title":"On the phase space decomposition for weakly connected oscillatory networks with 2nd order cells","authors":"M. Bonnin, F. Corinto, M. Gilli","doi":"10.1109/CNNA.2012.6331417","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331417","url":null,"abstract":"Oscillatory nonlinear networks represent a circuit architecture for image and information processing. It has been shown that they can be exploited to implement associative and dynamic memories. It has also been shown that phase noise play an important role as a limiting key factor for the performances of oscillatory cells. A tool of paramount importance for the design of oscillatory networks and the analysis of phase noise are phase models. These models require to treat the noise and the couplings among the cells as perturbations, and to identify the proper directions along which project the perturbations. In this paper we discuss the proper decomposition of the phase space for second order cells of oscillatory nonlinear networks, and we derive analytical formulas for the vectors spanning the directions for the proper phase space decomposition. We also discuss the implications of this decomposition in control theory and to what extent a simple orthogonal projection is correct.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132764614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331465
K. Choi, M. Awais, Hyung Chan Kim, Y. Doh
Fabrication of the printed memristors and their memristive behavior have been presented for different metal-insulator-metal (MIM) structures. The printing techniques studied for the current work includes electrohydrodynamic printing (EHDP) and roll-to-plate. The materials used for the electrode deposition are silver (Ag) and indium titanium oxide (ITO) while zirconium oxide (ZrO2) and graphene oxide (GO) have been used for the sandwich layer between two electrodes on a polyimide (PI) substrate. Electrically stable bipolar resistive switching behavior of all the MIM structures with significant Off/On ratio has been observed. The analysis regarding device dimensions and its current voltage (IV) behavior with respect to the employed printed electronic techniques confirms their feasibility for the cost-effective memristive device fabrication.
{"title":"Cost-effective printed memristor fabrication and analysis","authors":"K. Choi, M. Awais, Hyung Chan Kim, Y. Doh","doi":"10.1109/CNNA.2012.6331465","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331465","url":null,"abstract":"Fabrication of the printed memristors and their memristive behavior have been presented for different metal-insulator-metal (MIM) structures. The printing techniques studied for the current work includes electrohydrodynamic printing (EHDP) and roll-to-plate. The materials used for the electrode deposition are silver (Ag) and indium titanium oxide (ITO) while zirconium oxide (ZrO2) and graphene oxide (GO) have been used for the sandwich layer between two electrodes on a polyimide (PI) substrate. Electrically stable bipolar resistive switching behavior of all the MIM structures with significant Off/On ratio has been observed. The analysis regarding device dimensions and its current voltage (IV) behavior with respect to the employed printed electronic techniques confirms their feasibility for the cost-effective memristive device fabrication.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"424 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131741771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-18DOI: 10.1109/CNNA.2012.6331446
M. Kiss, Z. Gorocs, S. Tõkés
By developing a self referenced digital holographic microscope it becomes possible to record holograms and numerically reconstruct volumetric images of low coherence fluorescent objects such as (auto)fluorescent biological samples (e.g. algae). Our goal was to develop and construct a simple, compact portable device. In contrast to the common holographic approaches where there is a conventional reference beam, a reference beam should be produced together with the object beam from the same fluorescent source via imaging it by two separate optical paths (with near zero path length differences) to get interferences fringes. These interference forms separate holograms of all the point sources. The waves coming from the separate sources are mutually incoherent but have an inherent short coherence length. Initially we have tested the self referenced digital holographic microscope setup with test objects illuminated by LED light source that has similar spectral bandwidth as the fluorescence sources like chlorophyll. Digital reconstructions of the measured holograms need considerable processing. To accelerate the hologram processing a parallel implementation of processing seems essential. Using GPU-s we were able to enhance the algorithm's speed considerably, without the loss of the reconstruction accuracy.
{"title":"Self-referenced digital holographic microscopy","authors":"M. Kiss, Z. Gorocs, S. Tõkés","doi":"10.1109/CNNA.2012.6331446","DOIUrl":"https://doi.org/10.1109/CNNA.2012.6331446","url":null,"abstract":"By developing a self referenced digital holographic microscope it becomes possible to record holograms and numerically reconstruct volumetric images of low coherence fluorescent objects such as (auto)fluorescent biological samples (e.g. algae). Our goal was to develop and construct a simple, compact portable device. In contrast to the common holographic approaches where there is a conventional reference beam, a reference beam should be produced together with the object beam from the same fluorescent source via imaging it by two separate optical paths (with near zero path length differences) to get interferences fringes. These interference forms separate holograms of all the point sources. The waves coming from the separate sources are mutually incoherent but have an inherent short coherence length. Initially we have tested the self referenced digital holographic microscope setup with test objects illuminated by LED light source that has similar spectral bandwidth as the fluorescence sources like chlorophyll. Digital reconstructions of the measured holograms need considerable processing. To accelerate the hologram processing a parallel implementation of processing seems essential. Using GPU-s we were able to enhance the algorithm's speed considerably, without the loss of the reconstruction accuracy.","PeriodicalId":387536,"journal":{"name":"2012 13th International Workshop on Cellular Nanoscale Networks and their Applications","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133978007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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