{"title":"A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System","authors":"Qiaochu Zhao, Ittetsu Taniguchi, T. Onoye","doi":"10.2197/ipsjtsldm.14.21","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.14.21","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77317959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Experimental Evaluations of Parallel Tempering on an Ising Machine","authors":"Yosuke Mukasa, Shu Tanaka, N. Togawa","doi":"10.2197/ipsjtsldm.14.27","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.14.27","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86338829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Nishizawa, Shih-Ting Lin, Yih-Lang Li, H. Onodera
This paper reports a supplemental process design kit (PDK) for ASAP7 PDK using Synopsys design flow. ASAP7 is a PDK for “predictable” 7-nm FinFET technology node. ASAP7 PDK is useful for academical and educational purpose, however it only supports Cadence platform for Place and Route. A supplemental PDK is designed for ASAP7 to use Synopsys platform for Place and Route. This PDK is opened at the author’s GitHub site for both acamemical and educational usage.
{"title":"Supplemental PDK for ASAP7 Using Synopsys Flow","authors":"S. Nishizawa, Shih-Ting Lin, Yih-Lang Li, H. Onodera","doi":"10.2197/ipsjtsldm.14.24","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.14.24","url":null,"abstract":"This paper reports a supplemental process design kit (PDK) for ASAP7 PDK using Synopsys design flow. ASAP7 is a PDK for “predictable” 7-nm FinFET technology node. ASAP7 PDK is useful for academical and educational purpose, however it only supports Cadence platform for Place and Route. A supplemental PDK is designed for ASAP7 to use Synopsys platform for Place and Route. This PDK is opened at the author’s GitHub site for both acamemical and educational usage.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75250538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yukio Miyasaka, Akihiro Goda, A. Mittal, M. Fujita
Recently, there have been more chances to calculate matrix-vector multiplication due to the growing use of the neural network. We have proposed the method to automatically synthesize the optimum parallel algorithm for the given environment and synthesized an algorithm for matrix-vector multiplication of a specific size matrix with 4 nodes connected in a oneway ring. This paper proposes a method to generalize the synthesized algorithm to deal with any size matrix. We generalized the synthesized algorithm for the 32 × 32 matrix to calculate N × N matrix-vector multiplication.
{"title":"Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication","authors":"Yukio Miyasaka, Akihiro Goda, A. Mittal, M. Fujita","doi":"10.2197/ipsjtsldm.13.31","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.13.31","url":null,"abstract":"Recently, there have been more chances to calculate matrix-vector multiplication due to the growing use of the neural network. We have proposed the method to automatically synthesize the optimum parallel algorithm for the given environment and synthesized an algorithm for matrix-vector multiplication of a specific size matrix with 4 nodes connected in a oneway ring. This paper proposes a method to generalize the synthesized algorithm to deal with any size matrix. We generalized the synthesized algorithm for the 32 × 32 matrix to calculate N × N matrix-vector multiplication.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85376102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takumi Hosaka, S. Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi
In this paper, a simple and compact Negative Bias Temperature Instability (NBTI) model is proposed. It is based on the reaction-diffusion (tn) and hole-trapping (log(t)) theories. A single shot of DC stress and recovery data is utilized to express duty cycle dependence of NBTI degradation and recovery. Parameter fitting is proceeded by considering that the amount of recovery cannot be larger than stress degradation. The proposed universal model is applied to two types of transistors in different fabrication process technologies, and evaluate its feasibility to show the universality of our proposed model. It replicates stress and recovery successfully with various duty cycles.
{"title":"Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement","authors":"Takumi Hosaka, S. Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi","doi":"10.2197/ipsjtsldm.13.56","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.13.56","url":null,"abstract":"In this paper, a simple and compact Negative Bias Temperature Instability (NBTI) model is proposed. It is based on the reaction-diffusion (tn) and hole-trapping (log(t)) theories. A single shot of DC stress and recovery data is utilized to express duty cycle dependence of NBTI degradation and recovery. Parameter fitting is proceeded by considering that the amount of recovery cannot be larger than stress degradation. The proposed universal model is applied to two types of transistors in different fabrication process technologies, and evaluate its feasibility to show the universality of our proposed model. It replicates stress and recovery successfully with various duty cycles.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88130726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interconnect Electromigration Modeling and Analysis for Nanometer ICs: From Physics to Full-Chip","authors":"S. Tan, Zeyu Sun, Sheriff Sadiqbatcha","doi":"10.2197/ipsjtsldm.13.42","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.13.42","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74716404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
: This paper presents experimental evaluations of operating speed, power consumption, and chip tempera- ture under various load conditions on commercial FPGAs. To measure the operating speed of FPGAs, we count the oscillation frequency of a ring oscillator (RO), which is implemented on one 4-input look-up table (LUT). The load condition on FPGAs can be controlled by the number of activated ROs in parallel around the measurement RO. The measurement results show that operating speed may be decreased more than10% with 142 ROs as load circuits and the degradation rates depend on the measurement location in an FPGA. The evaluation of die-to-die variations using four more FPGA boards show that there exists a non-negligible speed variation.
{"title":"Measurement of Variations in FPGAs under Various Load Conditions","authors":"Y. Mitsuyama, Takashi Asada, Makio Eguchi","doi":"10.2197/ipsjtsldm.13.39","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.13.39","url":null,"abstract":": This paper presents experimental evaluations of operating speed, power consumption, and chip tempera- ture under various load conditions on commercial FPGAs. To measure the operating speed of FPGAs, we count the oscillation frequency of a ring oscillator (RO), which is implemented on one 4-input look-up table (LUT). The load condition on FPGAs can be controlled by the number of activated ROs in parallel around the measurement RO. The measurement results show that operating speed may be decreased more than10% with 142 ROs as load circuits and the degradation rates depend on the measurement location in an FPGA. The evaluation of die-to-die variations using four more FPGA boards show that there exists a non-negligible speed variation.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89966464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ryota Ishikawa, Masashi Tawada, M. Yanagisawa, N. Togawa
{"title":"Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design","authors":"Ryota Ishikawa, Masashi Tawada, M. Yanagisawa, N. Togawa","doi":"10.2197/ipsjtsldm.13.10","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.13.10","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78158538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, M. Iida, Hiroaki Yasuda, Hiroto Ito
: Graph neural networks are a type of deep-learning model for classification of graph domains. To infer arithmetic functions in a netlist, we applied relational graph convolutional networks (R-GCN), which can directly treat relations between nodes and edges. However, because original R-GCN supports only for node level labeling, it cannot be directly used to infer set of functions in a netlist. In this paper, by considering the distribution of labels for each node, we show a R-GCN based function inference method and data augmentation technique for netlist having multi- ple functions. According to our result, 91.4% accuracy is obtained from 1,000 training data, thus demonstrating that R-GCN-based methods can be e ff ective for graphs with multiple functions.
{"title":"R-GCN Based Function Inference for Gate-level Netlist","authors":"M. Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, M. Iida, Hiroaki Yasuda, Hiroto Ito","doi":"10.2197/ipsjtsldm.13.69","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.13.69","url":null,"abstract":": Graph neural networks are a type of deep-learning model for classification of graph domains. To infer arithmetic functions in a netlist, we applied relational graph convolutional networks (R-GCN), which can directly treat relations between nodes and edges. However, because original R-GCN supports only for node level labeling, it cannot be directly used to infer set of functions in a netlist. In this paper, by considering the distribution of labels for each node, we show a R-GCN based function inference method and data augmentation technique for netlist having multi- ple functions. According to our result, 91.4% accuracy is obtained from 1,000 training data, thus demonstrating that R-GCN-based methods can be e ff ective for graphs with multiple functions.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2020-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84408268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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