{"title":"Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA","authors":"Seiya Shirakuni, Ittetsu Taniguchi, H. Tomiyama","doi":"10.2197/ipsjtsldm.12.42","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.12.42","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81864805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Message from the Editor-in-Chief","authors":"N. Togawa","doi":"10.2197/ipsjtsldm.12.1","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.12.1","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85717959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures","authors":"Kaname Shimada, Ittetsu Taniguchi, H. Tomiyama","doi":"10.2197/ipsjtsldm.12.65","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.12.65","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72532284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A conversion method of a netlist consisting of conventional logic gates for superconducting rapid single flux quantum (RSFQ) circuit realization is proposed. The method detects OR gates which can be replaced with confluence buffers (CBs) which converge their input pulses into their outputs. The detection problem of replaceable OR gates is treated as a SAT problem. Each OR gate requires clock input in RSFQ circuits. By replacing OR gates with CBs, wiring for clocking those OR gates are eliminated and the number of active devices known as Josephson junctions is reduced.
{"title":"Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses","authors":"Nobutaka Kito, K. Takagi, N. Takagi","doi":"10.2197/ipsjtsldm.12.78","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.12.78","url":null,"abstract":"A conversion method of a netlist consisting of conventional logic gates for superconducting rapid single flux quantum (RSFQ) circuit realization is proposed. The method detects OR gates which can be replaced with confluence buffers (CBs) which converge their input pulses into their outputs. The detection problem of replaceable OR gates is treated as a SAT problem. Each OR gate requires clock input in RSFQ circuits. By replacing OR gates with CBs, wiring for clocking those OR gates are eliminated and the number of active devices known as Josephson junctions is reduced.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75051418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a new adiabatic logic for cryptographic circuits, called as the Current Pass Optimized Symmetric Pass Gate Adiabatic Logic (CPO-SPGAL). The proposed circuit realizes a flat current waveform by considering the current path. The simulation results demonstrate that the proposed circuit can reduce the current fluctuation by approximately 84% and reduce the energy consumption fluctuation by approximately 79% as compared to the existing SPGAL circuits. This shows that it is more resistant to differential power analysis attacks than conventional circuits.
{"title":"Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits","authors":"Hiroki Koyasu, Yasuhiro Takahashi","doi":"10.2197/ipsjtsldm.12.50","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.12.50","url":null,"abstract":"We propose a new adiabatic logic for cryptographic circuits, called as the Current Pass Optimized Symmetric Pass Gate Adiabatic Logic (CPO-SPGAL). The proposed circuit realizes a flat current waveform by considering the current path. The simulation results demonstrate that the proposed circuit can reduce the current fluctuation by approximately 84% and reduce the energy consumption fluctuation by approximately 79% as compared to the existing SPGAL circuits. This shows that it is more resistant to differential power analysis attacks than conventional circuits.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86284453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures","authors":"Daisuke Oku, M. Yanagisawa, N. Togawa","doi":"10.2197/ipsjtsldm.11.16","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.11.16","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78260685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Message from the Editor-in-Chief","authors":"N. Togawa","doi":"10.2197/ipsjtsldm.11.1","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.11.1","url":null,"abstract":"","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89079250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
: In advanced technology nodes, transistors and interconnects with shrinking physical dimensions su ff er large process variations during manufacturing and are prone to reliability issues. These underlying changes require an overhaul of the design methodologies for digital circuits. In this paper, we provide an overview of techniques introduced recently to analyze the e ff ect of uncertainty in manufacturing and reliability issues of devices due to the diminishing feature size. These techniques range from variation / aging modeling to circuit-level analysis. In addition, active techniques to counter these e ff ects, such as clock skew tuning and voltage tuning are also covered in this paper.
{"title":"From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era","authors":"Bing Li, M. Hashimoto, Ulf Schlichtmann","doi":"10.2197/ipsjtsldm.11.2","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.11.2","url":null,"abstract":": In advanced technology nodes, transistors and interconnects with shrinking physical dimensions su ff er large process variations during manufacturing and are prone to reliability issues. These underlying changes require an overhaul of the design methodologies for digital circuits. In this paper, we provide an overview of techniques introduced recently to analyze the e ff ect of uncertainty in manufacturing and reliability issues of devices due to the diminishing feature size. These techniques range from variation / aging modeling to circuit-level analysis. In addition, active techniques to counter these e ff ects, such as clock skew tuning and voltage tuning are also covered in this paper.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86781681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Melanie Diepenbeck, U. Kühne, Mathias Soeken, Daniel Große, R. Drechsler
Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers. Hence, one of the biggest challenges in design and verification today is to find new ways to increase the productivity. For software development the agile methodology as an incremental approach has been proposed and is heavily used. Behavior Driven Development (BDD) as an agile technique additionally enables a direct link to natural language based testing. In this article, we show how BDD can be extended to make it viable for hardware design. In addition, we present a two-fold strategy which allows to specify textual acceptance tests and textual formal properties. Finally, this strategy is complemented by methods to generalize tests to properties, and to enhance design understanding by presenting debug and witness scenarios in natural language.
{"title":"Behaviour Driven Development for Hardware Design","authors":"Melanie Diepenbeck, U. Kühne, Mathias Soeken, Daniel Große, R. Drechsler","doi":"10.2197/ipsjtsldm.11.29","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.11.29","url":null,"abstract":"Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers. Hence, one of the biggest challenges in design and verification today is to find new ways to increase the productivity. For software development the agile methodology as an incremental approach has been proposed and is heavily used. Behavior Driven Development (BDD) as an agile technique additionally enables a direct link to natural language based testing. In this article, we show how BDD can be extended to make it viable for hardware design. In addition, we present a two-fold strategy which allows to specify textual acceptance tests and textual formal properties. Finally, this strategy is complemented by methods to generalize tests to properties, and to enhance design understanding by presenting debug and witness scenarios in natural language.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76433856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
: High-level synthesis (HLS) significantly reduces hardware design time. Unfortunately, the users of HLS usually have to manually rewrite algorithm C code for satisfactory synthesis results. These manual tunings of C code often cause extra design time and decrease the advantage of HLS. One of such manual tunings is array access optimiza- tion. Large arrays are implemented as RAMs in HLS, so reducing array accesses in C code can increase performance of synthesized hardware since access conflicts to the RAMs are reduced. Furthermore, the removal of all accesses to arrays leads to the complete removal of the RAMs corresponding to the arrays. By successful application of scalar replacement to C code, data read from RAMs or written to RAMs are stored in shift registers, and these shift regis- ters are accessed instead of the RAMs when reusing the accessed data, thus array accesses are completely removed. Unfortunately, the most advanced scalar replacement method for nested loops cannot appropriately handle array ac- cesses with constant subscripts. This paper proposes a scalar replacement method to solve the problem. In particular, we target a subset of C code called Static Control Part (SCoP) for which we can build the mathematical representa- tion called the polyhedral model. The proposed method builds elaborate reuse information tables with the polyhedral model. Di ff erently from the previous method, the proposed method replaces each reuse destination that has multiple reuse vectors with scalar variables. These scalar variables are referenced conditionally according to the conditions in the reuse information tables. With the experimental results, we demonstrate that the proposed method decreases the area of synthesized hardware significantly and improves circuit performance compared to the most advanced scalar replacement method for nested loops in the case of C code which contain array accesses with constant subscripts.
{"title":"Scalar Replacement with Polyhedral Model","authors":"Kenshu Seto","doi":"10.2197/ipsjtsldm.11.46","DOIUrl":"https://doi.org/10.2197/ipsjtsldm.11.46","url":null,"abstract":": High-level synthesis (HLS) significantly reduces hardware design time. Unfortunately, the users of HLS usually have to manually rewrite algorithm C code for satisfactory synthesis results. These manual tunings of C code often cause extra design time and decrease the advantage of HLS. One of such manual tunings is array access optimiza- tion. Large arrays are implemented as RAMs in HLS, so reducing array accesses in C code can increase performance of synthesized hardware since access conflicts to the RAMs are reduced. Furthermore, the removal of all accesses to arrays leads to the complete removal of the RAMs corresponding to the arrays. By successful application of scalar replacement to C code, data read from RAMs or written to RAMs are stored in shift registers, and these shift regis- ters are accessed instead of the RAMs when reusing the accessed data, thus array accesses are completely removed. Unfortunately, the most advanced scalar replacement method for nested loops cannot appropriately handle array ac- cesses with constant subscripts. This paper proposes a scalar replacement method to solve the problem. In particular, we target a subset of C code called Static Control Part (SCoP) for which we can build the mathematical representa- tion called the polyhedral model. The proposed method builds elaborate reuse information tables with the polyhedral model. Di ff erently from the previous method, the proposed method replaces each reuse destination that has multiple reuse vectors with scalar variables. These scalar variables are referenced conditionally according to the conditions in the reuse information tables. With the experimental results, we demonstrate that the proposed method decreases the area of synthesized hardware significantly and improves circuit performance compared to the most advanced scalar replacement method for nested loops in the case of C code which contain array accesses with constant subscripts.","PeriodicalId":38964,"journal":{"name":"IPSJ Transactions on System LSI Design Methodology","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87163488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：