Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218437
B. Preneel, R. Govaerts, J. Vandewalle
The protection of information authentication based on cryptographically secure hash functions is discussed. Two classes of hash functions are defined, namely keyed and keyless hash functions. It is shown that they can be applied under different circumstances to protect the authenticity of information. A taxonomy of existing schemes for information authentication is developed, and an overview of practical schemes is given.<>
{"title":"Hash functions for information authentication","authors":"B. Preneel, R. Govaerts, J. Vandewalle","doi":"10.1109/CMPEUR.1992.218437","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218437","url":null,"abstract":"The protection of information authentication based on cryptographically secure hash functions is discussed. Two classes of hash functions are defined, namely keyed and keyless hash functions. It is shown that they can be applied under different circumstances to protect the authenticity of information. A taxonomy of existing schemes for information authentication is developed, and an overview of practical schemes is given.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122635432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218424
E. Kwee-Christoph, B. Eschermann, O. Haberl, R. Kumar, A. Kunzmann
The authors address the problem of design flow management with special emphasis on tool selection strategies. To solve this problem the concept and implementation of a design consultant (CADEC) is described. The concept of this expert system based facility for tool selection and execution, which enriches the CAD framework, is presented. The various phases that are to be undergone for completion of the design process are embedded within this concept. The implementational aspects of this expert facility, using an object-oriented approach, are given. CADEC offers comprehensive support through all steps of the design process and guides the designer through the complex maze of tools and data. integrated within a framework.<>
{"title":"The CADEC VLSI design support methodology","authors":"E. Kwee-Christoph, B. Eschermann, O. Haberl, R. Kumar, A. Kunzmann","doi":"10.1109/CMPEUR.1992.218424","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218424","url":null,"abstract":"The authors address the problem of design flow management with special emphasis on tool selection strategies. To solve this problem the concept and implementation of a design consultant (CADEC) is described. The concept of this expert system based facility for tool selection and execution, which enriches the CAD framework, is presented. The various phases that are to be undergone for completion of the design process are embedded within this concept. The implementational aspects of this expert facility, using an object-oriented approach, are given. CADEC offers comprehensive support through all steps of the design process and guides the designer through the complex maze of tools and data. integrated within a framework.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125703699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218481
P. Hu, S. Wilbur
Two algorithms are given for maintaining the consistency of replicated files. One is called dynamic supporting; the other is an extension of dynamic supporting called dynamic supporting with a greatest copy. The algorithms are hybrids of some existing algorithms. The correctness of these two algorithms is proved. Since replicas and votes are conceptually separated, the algorithms can achieve very good performance while still keeping storage costs very low. The proposed algorithms make no further assumptions about the distributed environment than conventional voting algorithms, so they can even tolerate network partition failures.<>
{"title":"Low storage cost, partition-tolerant dynamic algorithms for replicated file systems","authors":"P. Hu, S. Wilbur","doi":"10.1109/CMPEUR.1992.218481","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218481","url":null,"abstract":"Two algorithms are given for maintaining the consistency of replicated files. One is called dynamic supporting; the other is an extension of dynamic supporting called dynamic supporting with a greatest copy. The algorithms are hybrids of some existing algorithms. The correctness of these two algorithms is proved. Since replicas and votes are conceptually separated, the algorithms can achieve very good performance while still keeping storage costs very low. The proposed algorithms make no further assumptions about the distributed environment than conventional voting algorithms, so they can even tolerate network partition failures.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129890802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218479
G. Ramanathan, V. Alagar
A unified framework is given for the specification of external consistency constraints, integrity constraints, and temporal consistency constraints of a real-time distributed database system. The formalism is event based and facilitates both relative and quantitative reasoning about time. The functional model of V.S. Alagar and G. Ramanathan (1991) is extended with constructs needed to specify the requirements of real-time databases. To illustrate the use of these constructs, the specification and proof of correctness of a real-time concurrency control protocol are presented.<>
{"title":"Specification of real-time distributed database systems","authors":"G. Ramanathan, V. Alagar","doi":"10.1109/CMPEUR.1992.218479","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218479","url":null,"abstract":"A unified framework is given for the specification of external consistency constraints, integrity constraints, and temporal consistency constraints of a real-time distributed database system. The formalism is event based and facilitates both relative and quantitative reasoning about time. The functional model of V.S. Alagar and G. Ramanathan (1991) is extended with constructs needed to specify the requirements of real-time databases. To illustrate the use of these constructs, the specification and proof of correctness of a real-time concurrency control protocol are presented.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121174114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218421
A. P. Casimiro, J. Sousa, F. Gonçalves, J. P. Teixeira
A methodology that provides a way to control the test quality of VLSI systems by predicting, diagnosing, and improving the IC defect coverage is presented for the case of the physical implementation of boundary scan circuitry, together with the software tools that implement it. The method allows the identification of hard-to-detect faults, their physical origin and layout location, leading to suggestions for design improvement by layout reconfiguration. The method is illustrated by the testability analysis of a full-custom design, implementing the boundary scan circuitry to be added to a core logic IC, in accordance with the IEEE P.1149 standard.<>
{"title":"Test quality improvement by physical testability enhancement","authors":"A. P. Casimiro, J. Sousa, F. Gonçalves, J. P. Teixeira","doi":"10.1109/CMPEUR.1992.218421","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218421","url":null,"abstract":"A methodology that provides a way to control the test quality of VLSI systems by predicting, diagnosing, and improving the IC defect coverage is presented for the case of the physical implementation of boundary scan circuitry, together with the software tools that implement it. The method allows the identification of hard-to-detect faults, their physical origin and layout location, leading to suggestions for design improvement by layout reconfiguration. The method is illustrated by the testability analysis of a full-custom design, implementing the boundary scan circuitry to be added to a core logic IC, in accordance with the IEEE P.1149 standard.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125239980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218509
B. Apolloni, G. Mauri, C. Trevisson, P. Valota, A. Zanaboni
A technique is proposed, based on neural networks for dealing with a particular problem of syntactical ambiguity in the process of building the syntactical tree of an Italian sentence, namely the PP-attachment problem. The neural network was used as a daemon for a top-down parser, when it faced multiple entries in the parsing table. The network was trained to solve PP-attachment ambiguities by the well known algorithm for error back-propagation. What is new is the knowledge representation technique in the network, which has been designed to represent the relevant pieces of information about the constituents of the sentence. Performance results are reported and discussed, together with future perspectives.<>
{"title":"Learning to solve PP-attachment ambiguities in natural language processing through neural networks","authors":"B. Apolloni, G. Mauri, C. Trevisson, P. Valota, A. Zanaboni","doi":"10.1109/CMPEUR.1992.218509","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218509","url":null,"abstract":"A technique is proposed, based on neural networks for dealing with a particular problem of syntactical ambiguity in the process of building the syntactical tree of an Italian sentence, namely the PP-attachment problem. The neural network was used as a daemon for a top-down parser, when it faced multiple entries in the parsing table. The network was trained to solve PP-attachment ambiguities by the well known algorithm for error back-propagation. What is new is the knowledge representation technique in the network, which has been designed to represent the relevant pieces of information about the constituents of the sentence. Performance results are reported and discussed, together with future perspectives.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121491088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218408
A. Bartoli, G. Dini
An application package which allows the user to explore the possibility of hiding communication latencies in message-passing multiprocessors is examined. The package is a neural network simulator for transputer-based machines. Simply by modifying few high-level directives in a configuration file, heuristic strategies for fully overlapping communication delays with internal computation, can be easily explored. The neural network model and the software architecture are described. An example is discussed.<>
{"title":"Hiding communication latencies in message-passing multiprocessors: a case study based on neural network simulation","authors":"A. Bartoli, G. Dini","doi":"10.1109/CMPEUR.1992.218408","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218408","url":null,"abstract":"An application package which allows the user to explore the possibility of hiding communication latencies in message-passing multiprocessors is examined. The package is a neural network simulator for transputer-based machines. Simply by modifying few high-level directives in a configuration file, heuristic strategies for fully overlapping communication delays with internal computation, can be easily explored. The neural network model and the software architecture are described. An example is discussed.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129094181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218488
A. Ciampolini, Antonio Corradi, L. Leonardi
A routing strategy is described, implemented for an object-oriented environment designed for a massively parallel architecture based on transputers, the MEIKO Computing Surface. The implemented routing algorithm belongs to the distance-vector family. The routing tool guarantees some pleasant properties: independence of topology, adaptability, nondeterministic behavior, and distribution of routing decision. The performance figures of the implementation are compared with the routing offered by CSSTools of MEIKO. The routing presented is adaptive and nondeterministic. It adapts both to traffic variation and to topology changes.<>
{"title":"An adaptive routing tool for transputer-based architectures","authors":"A. Ciampolini, Antonio Corradi, L. Leonardi","doi":"10.1109/CMPEUR.1992.218488","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218488","url":null,"abstract":"A routing strategy is described, implemented for an object-oriented environment designed for a massively parallel architecture based on transputers, the MEIKO Computing Surface. The implemented routing algorithm belongs to the distance-vector family. The routing tool guarantees some pleasant properties: independence of topology, adaptability, nondeterministic behavior, and distribution of routing decision. The performance figures of the implementation are compared with the routing offered by CSSTools of MEIKO. The routing presented is adaptive and nondeterministic. It adapts both to traffic variation and to topology changes.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130511374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218499
E. Macii, A. Lioy, A. Meo
Algorithms and implementation issues concerning a Boolean factorization based test generation package for gate level sequential machines are discussed. Practical aspects like justification and propagation weights computation and targeted test pattern generation are treated in depth, giving both theoretical and pseudo-code solutions. The experimental results showed that the proposed method was effective in generating sufficiently high fault coverage for the standard set of ISCAS'89 benchmark synchronous sequential circuits.<>
{"title":"Test generation for gate level sequential machines: algorithms and implementation issues","authors":"E. Macii, A. Lioy, A. Meo","doi":"10.1109/CMPEUR.1992.218499","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218499","url":null,"abstract":"Algorithms and implementation issues concerning a Boolean factorization based test generation package for gate level sequential machines are discussed. Practical aspects like justification and propagation weights computation and targeted test pattern generation are treated in depth, giving both theoretical and pseudo-code solutions. The experimental results showed that the proposed method was effective in generating sufficiently high fault coverage for the standard set of ISCAS'89 benchmark synchronous sequential circuits.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131575850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218402
J. Aull
Describes how computer assisted software engineering (CASE) tools were used in the process of validation of several reactor physics codes. ARCHY is a tool that automates most of the drudgery involved in making a programmer's reference manual. When FORTRAN source code is read by ARCHY, it outputs a data dictionary that includes a categorization of variables and common block information. It also prints structure charts and Yourdon diagrams in PostScript format. The author also describes how several off-the-shelf products were used in validating critical reactor analysis software. FORTRAN-Lint is a useful tool for correcting deviations from the FORTRAN-77 standard. DEC Test Manager and the IBM-MVS SuperCE utility are useful for regression testing. DEC's Performance and Coverage Analyzer is a powerful tool for assessing the completeness of a test suite.<>
描述计算机辅助软件工程(CASE)工具如何在几个反应堆物理代码的验证过程中使用。ARCHY是一个工具，它可以自动完成编写程序员参考手册所涉及的大部分苦差事。当ARCHY读取FORTRAN源代码时，它输出一个数据字典，其中包括变量分类和公共块信息。它还可以打印PostScript格式的结构图和Yourdon图。作者还描述了几种现成的产品如何用于验证临界反应器分析软件。FORTRAN-Lint是纠正偏离FORTRAN-77标准的有用工具。DEC Test Manager和IBM-MVS SuperCE实用程序对于回归测试非常有用。DEC的性能和覆盖率分析器是评估测试套件完整性的强大工具。
{"title":"Validation using CASE tools","authors":"J. Aull","doi":"10.1109/CMPEUR.1992.218402","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218402","url":null,"abstract":"Describes how computer assisted software engineering (CASE) tools were used in the process of validation of several reactor physics codes. ARCHY is a tool that automates most of the drudgery involved in making a programmer's reference manual. When FORTRAN source code is read by ARCHY, it outputs a data dictionary that includes a categorization of variables and common block information. It also prints structure charts and Yourdon diagrams in PostScript format. The author also describes how several off-the-shelf products were used in validating critical reactor analysis software. FORTRAN-Lint is a useful tool for correcting deviations from the FORTRAN-77 standard. DEC Test Manager and the IBM-MVS SuperCE utility are useful for regression testing. DEC's Performance and Coverage Analyzer is a powerful tool for assessing the completeness of a test suite.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133106352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：