Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218495
K. Goto, H. Tatsumi
A method is given for further minimizing the multilevel NAND gate circuit having single-rail inputs obtained by applying the inhibiting-loop method of K. Goto (1989) to the given function. Using several theorems proposed by the authors several rules are used to determine whether the same input exists in the preceding and succeeding gate levels, and to determine whether the common input exists at the same first level of some parallel multilevel NAND gates, or other conditions. The Lisp language program utilizing this method was run on the microVAX-II computer for three-variable P-equivalence classes and four-variable functions. As a result, the coincidences for the three-variable functions and four-variable functions between the ideal results and the obtained results were 40% and 11%, respectively, when using the inhibiting-loop method alone. However, the results improved to 90% and 64%, respectively, by the addition of this reducing method.<>
{"title":"Minimization of NAND circuits by rewriting-rules heuristic","authors":"K. Goto, H. Tatsumi","doi":"10.1109/CMPEUR.1992.218495","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218495","url":null,"abstract":"A method is given for further minimizing the multilevel NAND gate circuit having single-rail inputs obtained by applying the inhibiting-loop method of K. Goto (1989) to the given function. Using several theorems proposed by the authors several rules are used to determine whether the same input exists in the preceding and succeeding gate levels, and to determine whether the common input exists at the same first level of some parallel multilevel NAND gates, or other conditions. The Lisp language program utilizing this method was run on the microVAX-II computer for three-variable P-equivalence classes and four-variable functions. As a result, the coincidences for the three-variable functions and four-variable functions between the ideal results and the obtained results were 40% and 11%, respectively, when using the inhibiting-loop method alone. However, the results improved to 90% and 64%, respectively, by the addition of this reducing method.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114611242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218485
J. Alander
A description is given of the results of experiments to find the optimum population size for genetic algorithms as a function of problem complexity. It seems that for moderate problem complexity the optimal population size for problems coded as bitstrings is approximately the length of the string in bits for sequential machines. This result is also consistent with earlier experimentation. In parallel architectures the optimal population size is larger than in the corresponding sequential cases, but the exact figures seem to be sensitive to implementation details.<>
{"title":"On optimal population size of genetic algorithms","authors":"J. Alander","doi":"10.1109/CMPEUR.1992.218485","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218485","url":null,"abstract":"A description is given of the results of experiments to find the optimum population size for genetic algorithms as a function of problem complexity. It seems that for moderate problem complexity the optimal population size for problems coded as bitstrings is approximately the length of the string in bits for sequential machines. This result is also consistent with earlier experimentation. In parallel architectures the optimal population size is larger than in the corresponding sequential cases, but the exact figures seem to be sensitive to implementation details.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132109996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218482
D. Bell, M. Hull, F. F. Cai, D. Guthrie, C. Shapcott
The design and development of a parallel database machine using a transputer network is presented. To exploit several forms of parallelism for database applications and give maximum flexibility, the system uses a communicating process model both in the implementation of database operations, and in the provision of system services. Following an overview of the system architecture, the development of the major processing modules is described, which includes query evaluation, buffer management and the file system.<>
{"title":"A flexible parallel database system using transputers","authors":"D. Bell, M. Hull, F. F. Cai, D. Guthrie, C. Shapcott","doi":"10.1109/CMPEUR.1992.218482","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218482","url":null,"abstract":"The design and development of a parallel database machine using a transputer network is presented. To exploit several forms of parallelism for database applications and give maximum flexibility, the system uses a communicating process model both in the implementation of database operations, and in the provision of system services. Following an overview of the system architecture, the development of the major processing modules is described, which includes query evaluation, buffer management and the file system.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132982591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218452
J. Konorski, K. Nowicki, J. Wozniak
A unified local Markov model of an S-ALOHA multihop packet radio network with an automatic repeat request (ARQ)-type station-to-station transmission protocol is formulated to study the joint impact of the buffer, acknowledgment, and retransmission policy on the network performance. The accepted symmetry assumptions permit focus on a single station in isolation, for which a set of stochastic equations is obtained and solved via hybrid simulation to obtain credible estimates of the desired steady-state characteristics. Sample results and comparisons are presented.<>
{"title":"A unified local Markov model of a multihop packet radio network","authors":"J. Konorski, K. Nowicki, J. Wozniak","doi":"10.1109/CMPEUR.1992.218452","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218452","url":null,"abstract":"A unified local Markov model of an S-ALOHA multihop packet radio network with an automatic repeat request (ARQ)-type station-to-station transmission protocol is formulated to study the joint impact of the buffer, acknowledgment, and retransmission policy on the network performance. The accepted symmetry assumptions permit focus on a single station in isolation, for which a set of stochastic equations is obtained and solved via hybrid simulation to obtain credible estimates of the desired steady-state characteristics. Sample results and comparisons are presented.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116084496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218425
B. Žalik, N. Guid, A. Vesel
Symbolic and numerical techniques are coupled together in a proposed geometric modeling system. The geometric modeling system is based on geometrical constraints. It is unnecessary to give constraints in the correct order and the ability of replacing incorrect constraints with their inverse constraints exists in the system itself. A new structure, a biconnected constraint description graph, is used. A triggering mechanism for controlling of the constraint propagation is developed for this structure. An algorithm for converting the biconnected constraint description graph into an acyclic constraint description graph is outlined.<>
{"title":"Triggering mechanism for constraints solving in constraint-based geometric modeling system","authors":"B. Žalik, N. Guid, A. Vesel","doi":"10.1109/CMPEUR.1992.218425","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218425","url":null,"abstract":"Symbolic and numerical techniques are coupled together in a proposed geometric modeling system. The geometric modeling system is based on geometrical constraints. It is unnecessary to give constraints in the correct order and the ability of replacing incorrect constraints with their inverse constraints exists in the system itself. A new structure, a biconnected constraint description graph, is used. A triggering mechanism for controlling of the constraint propagation is developed for this structure. An algorithm for converting the biconnected constraint description graph into an acyclic constraint description graph is outlined.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127732031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218504
U. Arzt, J. Teich, M. Schumacher, L. Thiele
A hierarchical representation of parallel algorithms is described that can be systematically mapped onto a class of massive parallel architectures called processor arrays. A notation of hierarchical parallel programs is introduced for the representation of algorithms that can be mapped onto processor arrays. By means of a transformative approach, two provably correct program transformations are introduced to solve the problems of generating (CREATE) and of dissolving (FLATTEN) different levels of hierarchy. The program transformations CREATE and FLATTEN are formally described and explained by an example.<>
{"title":"Hierarchical concepts in the design of processor arrays","authors":"U. Arzt, J. Teich, M. Schumacher, L. Thiele","doi":"10.1109/CMPEUR.1992.218504","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218504","url":null,"abstract":"A hierarchical representation of parallel algorithms is described that can be systematically mapped onto a class of massive parallel architectures called processor arrays. A notation of hierarchical parallel programs is introduced for the representation of algorithms that can be mapped onto processor arrays. By means of a transformative approach, two provably correct program transformations are introduced to solve the problems of generating (CREATE) and of dissolving (FLATTEN) different levels of hierarchy. The program transformations CREATE and FLATTEN are formally described and explained by an example.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128059737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218511
E. Durr, J. Katwijk
Some general issues in the design of VDM++ are discussed. VDM++ extends VDM by offering classes, objects and inheritance and provides as an additional feature, a formalism to specify the allowed invocation sequence of methods. The design of VDM++ is such that any specification in VDM++ can be translated automatically into a specification in classical flat VDM, as defined in BSI/IST/5/50, thereby implicitly defining the semantics in terms of the semantics of VDM.<>
{"title":"VDM++, a formal specification language for object-oriented designs","authors":"E. Durr, J. Katwijk","doi":"10.1109/CMPEUR.1992.218511","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218511","url":null,"abstract":"Some general issues in the design of VDM++ are discussed. VDM++ extends VDM by offering classes, objects and inheritance and provides as an additional feature, a formalism to specify the allowed invocation sequence of methods. The design of VDM++ is such that any specification in VDM++ can be translated automatically into a specification in classical flat VDM, as defined in BSI/IST/5/50, thereby implicitly defining the semantics in terms of the semantics of VDM.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121050738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218440
J. Heistermann
The author discusses some of the capabilities of genetic algorithms (GAs). GAs are compared with other standard optimization methods like gradient descent or simulated annealing (SA). It is shown that SA is just a special case of GA. The role of a population in the optimization process is demonstrated by an example. GA was applied as a learning algorithm to neural networks.<>
{"title":"A mixed genetic approach to the optimization of neural controllers","authors":"J. Heistermann","doi":"10.1109/CMPEUR.1992.218440","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218440","url":null,"abstract":"The author discusses some of the capabilities of genetic algorithms (GAs). GAs are compared with other standard optimization methods like gradient descent or simulated annealing (SA). It is shown that SA is just a special case of GA. The role of a population in the optimization process is demonstrated by an example. GA was applied as a learning algorithm to neural networks.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121331192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218510
Valeriu Beiu, D. Ioan, M.C. Dumbrava
An introduction is given to the concept of a continuous Boltzmann machine (CBM) and an application to solve a class of partial differential equations (PDEs) is detailed. After briefly stating the problems, the BM is presented at a conceptual level. The basic ideas are taken to another level, and a fresh concept, CBM, is introduced, with the differences discussed in some detail. As Boltzmann machines have solved hard NP-complete optimization problems, the CBM has been used to solve large systems of elliptic PDEs arising in steady-state physical fields. Numerical results of simulations proved the characteristic features of the CBM.<>
{"title":"Continuous Boltzmann machines: theoretical aspects and applications","authors":"Valeriu Beiu, D. Ioan, M.C. Dumbrava","doi":"10.1109/CMPEUR.1992.218510","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218510","url":null,"abstract":"An introduction is given to the concept of a continuous Boltzmann machine (CBM) and an application to solve a class of partial differential equations (PDEs) is detailed. After briefly stating the problems, the BM is presented at a conceptual level. The basic ideas are taken to another level, and a fresh concept, CBM, is introduced, with the differences discussed in some detail. As Boltzmann machines have solved hard NP-complete optimization problems, the CBM has been used to solve large systems of elliptic PDEs arising in steady-state physical fields. Numerical results of simulations proved the characteristic features of the CBM.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"371 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120880879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-04DOI: 10.1109/CMPEUR.1992.218400
G. Klas, C. Wincheringer
Results on the performance of a Multibus II based automation system are presented. These are achieved by means of a generalized stochastic Petri net model which was solved by analytical techniques instead of by simulation. The mapping of this industry-standard protocol to a stochastic Petri net model is outlined. It is shown how protocol features like arbitration priorities, parking, and message passing can be conveniently and efficiently analyzed from a Petri net model. This allows the estimation of optimum values for system parameters like the message size, and the identification of bottlenecks in a given architecture.<>
{"title":"A generalized stochastic Petri net model of Multibus II","authors":"G. Klas, C. Wincheringer","doi":"10.1109/CMPEUR.1992.218400","DOIUrl":"https://doi.org/10.1109/CMPEUR.1992.218400","url":null,"abstract":"Results on the performance of a Multibus II based automation system are presented. These are achieved by means of a generalized stochastic Petri net model which was solved by analytical techniques instead of by simulation. The mapping of this industry-standard protocol to a stochastic Petri net model is outlined. It is shown how protocol features like arbitration priorities, parking, and message passing can be conveniently and efficiently analyzed from a Petri net model. This allows the estimation of optimum values for system parameters like the message size, and the identification of bottlenecks in a given architecture.<<ETX>>","PeriodicalId":390273,"journal":{"name":"CompEuro 1992 Proceedings Computer Systems and Software Engineering","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114789381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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