Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551355
F. Zheng, Lianfeng Huang, Zhiyuan Shi, Tao Yang
In this paper, a new variable step-size LMS algorithm based on computational verb rules is presented. This method allows the algorithm to converge faster and to produce smaller steady-state errors compared to other variable step-size LMS algorithms, even when the system is subjected to sudden changes. Furthermore, it provides a brand new framework that allows the designers to design adaptive algorithms in a simpler and more effective way by using computational verb rules to encode the designers' knowledge of dynamical processes. Simulation results are provided to show the usefulness of the proposed algorithm by comparing with other variable step-size LMS algorithms.
{"title":"Variable step-size LMS adaptive algorithm based on computational verb rules","authors":"F. Zheng, Lianfeng Huang, Zhiyuan Shi, Tao Yang","doi":"10.1109/ICASID.2010.5551355","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551355","url":null,"abstract":"In this paper, a new variable step-size LMS algorithm based on computational verb rules is presented. This method allows the algorithm to converge faster and to produce smaller steady-state errors compared to other variable step-size LMS algorithms, even when the system is subjected to sudden changes. Furthermore, it provides a brand new framework that allows the designers to design adaptive algorithms in a simpler and more effective way by using computational verb rules to encode the designers' knowledge of dynamical processes. Simulation results are provided to show the usefulness of the proposed algorithm by comparing with other variable step-size LMS algorithms.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130380200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551513
Qiwei Lin, Gui Feng
H.264/AVC video encoding standard is a successful video compression standard after the MPEG-2/H.262. It's received much attention from academic and industrial fields. In this paper, rate control algorithm is discussed. By noticing that the H.264/AVC rate control algorithm has some disadvantages, two frame layer rate control improvement strategies are proposed in this paper, which are based on the bit allocation and the RDO(Rate Distortion Optimization) mode respectively. The proposed rate control algorithm includes GOP layer rate control, frame-layer rate control and basic unit layer rate control. The improvement algorithm has two steps: The first step is the mode selection parameter and the quantification parameter separating; the second step is to adjust λMODE, according actual encoding bit rate. The algorithm is performed on the JM86 platform which implants the frame skip scheme. The simulation results show that the improved algorithm do have some advantages over the JM86 rate control algorithm, in the aspects on the buffer controlling, the accuracy of output rate, avoiding frame skip and the smoothness of the decoded sequence.
{"title":"The bit allocation and RDO mode based rate control algorithm","authors":"Qiwei Lin, Gui Feng","doi":"10.1109/ICASID.2010.5551513","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551513","url":null,"abstract":"H.264/AVC video encoding standard is a successful video compression standard after the MPEG-2/H.262. It's received much attention from academic and industrial fields. In this paper, rate control algorithm is discussed. By noticing that the H.264/AVC rate control algorithm has some disadvantages, two frame layer rate control improvement strategies are proposed in this paper, which are based on the bit allocation and the RDO(Rate Distortion Optimization) mode respectively. The proposed rate control algorithm includes GOP layer rate control, frame-layer rate control and basic unit layer rate control. The improvement algorithm has two steps: The first step is the mode selection parameter and the quantification parameter separating; the second step is to adjust λMODE, according actual encoding bit rate. The algorithm is performed on the JM86 platform which implants the frame skip scheme. The simulation results show that the improved algorithm do have some advantages over the JM86 rate control algorithm, in the aspects on the buffer controlling, the accuracy of output rate, avoiding frame skip and the smoothness of the decoded sequence.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129965957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551503
Liguang Wang, Zhijie Liu
The research on parameter calibration of traffic simulation model plays an important role in whether a model can well reflect the real traffic situation of the road. Thus it can provide evidence indirectly to traffic management and control. In this paper, the data verified in the traffic simulation software VISSIM is compared with the measured data, then we know that the model parameters after correction can better reflect the actual situation of the road. The method can also be extended to other roads and intersections in the parameters correction of simulation model.
{"title":"Research on correction method of traffic simulation model based on linear regression","authors":"Liguang Wang, Zhijie Liu","doi":"10.1109/ICASID.2010.5551503","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551503","url":null,"abstract":"The research on parameter calibration of traffic simulation model plays an important role in whether a model can well reflect the real traffic situation of the road. Thus it can provide evidence indirectly to traffic management and control. In this paper, the data verified in the traffic simulation software VISSIM is compared with the measured data, then we know that the model parameters after correction can better reflect the actual situation of the road. The method can also be extended to other roads and intersections in the parameters correction of simulation model.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551521
Xiaochao Li, Xiaofan Lin, Donghui Guo
System design and performance are presented for an experimental FM-DCSK radio system with a blind timing acquisition scheme. The transmitter and receiver architecture is proposed, and a novel two-stage blind bit synchronization algorithm for a fast and efficient timing acquisition process is introduced. This synchronization scheme exploits the waveform repetition pattern which naturally present in the DCSK transmitted reference signal structure. The BER performance of such systems is evaluated under AWGN and multi-path channel, the value is fairly close to that of perfect synchronization, which is 0.2dB difference at SNR 10–15dB. Key building blocks of circuit implementation are also presented.
{"title":"The experimental blind timing acquisition scheme for FM-DCSK communication system","authors":"Xiaochao Li, Xiaofan Lin, Donghui Guo","doi":"10.1109/ICASID.2010.5551521","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551521","url":null,"abstract":"System design and performance are presented for an experimental FM-DCSK radio system with a blind timing acquisition scheme. The transmitter and receiver architecture is proposed, and a novel two-stage blind bit synchronization algorithm for a fast and efficient timing acquisition process is introduced. This synchronization scheme exploits the waveform repetition pattern which naturally present in the DCSK transmitted reference signal structure. The BER performance of such systems is evaluated under AWGN and multi-path channel, the value is fairly close to that of perfect synchronization, which is 0.2dB difference at SNR 10–15dB. Key building blocks of circuit implementation are also presented.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"33 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116717984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551515
Yongfu Yan, Jianyang Zhou, Chunfang Zheng
In this paper, we design and implement 3D scan conversion algorithm using Handel-C language. Primarily we introduce the 3D graphics rendering process and analyze the principle of improved scan conversion algorithm. Then we design and implement the improved scan conversion algorithm. Finally we translate the Handel-C code into Verilog-HDL code and verify the design in ModelSim. Parallel optimization schemes are introduced in Handel-C porting. The performance increases more than 12 times after optimization. The design experience shows that the hardware implementation of complex algorithm based on Handel-C is feasible and efficient.
{"title":"Design and implementation of 3D scan conversion algorithm based on Handel-C","authors":"Yongfu Yan, Jianyang Zhou, Chunfang Zheng","doi":"10.1109/ICASID.2010.5551515","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551515","url":null,"abstract":"In this paper, we design and implement 3D scan conversion algorithm using Handel-C language. Primarily we introduce the 3D graphics rendering process and analyze the principle of improved scan conversion algorithm. Then we design and implement the improved scan conversion algorithm. Finally we translate the Handel-C code into Verilog-HDL code and verify the design in ModelSim. Parallel optimization schemes are introduced in Handel-C porting. The performance increases more than 12 times after optimization. The design experience shows that the hardware implementation of complex algorithm based on Handel-C is feasible and efficient.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116761526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551344
Hongli Tang, Xiaoyao Xie, Xiangdong Yang, Chen Yang, J. Xiao
The realization of communication between PC and PLC is the basic constituent part in rescue robot control system. It has direct impact to the function of entire system. This paper introduces a method in detail which can make the communication between the rescue robot upper computer and lower PLC come true. It also analyses how to implement communication between S7-200 programmable logic controller and personal computer in the mode of free port, and given the programming instance. Practice indicates the idea of the scheme is succinct and also very effective.
{"title":"The implementation of communication between the upper computer and lower PLC of rescue robot","authors":"Hongli Tang, Xiaoyao Xie, Xiangdong Yang, Chen Yang, J. Xiao","doi":"10.1109/ICASID.2010.5551344","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551344","url":null,"abstract":"The realization of communication between PC and PLC is the basic constituent part in rescue robot control system. It has direct impact to the function of entire system. This paper introduces a method in detail which can make the communication between the rescue robot upper computer and lower PLC come true. It also analyses how to implement communication between S7-200 programmable logic controller and personal computer in the mode of free port, and given the programming instance. Practice indicates the idea of the scheme is succinct and also very effective.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115694125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551337
Huiqing Liu, Yinghao Liao, Tao Yang, Cheng Chen
In this paper, a new image interpolation algorithm is proposed due to the inspiration of knowledge-based learning and dynamical control strategy which are based on computational verb theory. This algorithm takes gray level profiles and contour shapes as two processing factors. Experiments show that, with respect to the performance near edges of digital images, our algorithm is better than nearest neighbor interpolation algorithm; with respect to the performance in regions of images, our method is better than bilinear interpolation and bicubic interpolation.
{"title":"Image interpolation algorithm based on computational verb theory","authors":"Huiqing Liu, Yinghao Liao, Tao Yang, Cheng Chen","doi":"10.1109/ICASID.2010.5551337","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551337","url":null,"abstract":"In this paper, a new image interpolation algorithm is proposed due to the inspiration of knowledge-based learning and dynamical control strategy which are based on computational verb theory. This algorithm takes gray level profiles and contour shapes as two processing factors. Experiments show that, with respect to the performance near edges of digital images, our algorithm is better than nearest neighbor interpolation algorithm; with respect to the performance in regions of images, our method is better than bilinear interpolation and bicubic interpolation.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127194824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551512
Xiaopeng Lin, Yiyang Li, H. Dai, Donghui Guo
Cloud computing is usually defined to deliver infrastructure, platform and software as services, which is available as a pay-as-you-go model for users. A paradigm of Cloud computing for EDA service is presented in this paper, and a hierarchical architecture of Web-EDA system implemented with Cloud computing is described in detail. Based on this proposed system structure, we developed a prototype of the Web-EDA system for sharing EDA Tools and project management of IC design. It shows that Cloud computing for EDA service is possible to be implemented distributedly and brings maximum benefit to both users and vendors.
{"title":"Architecture of Web-EDA system based on Cloud computing and application for project management of IC design","authors":"Xiaopeng Lin, Yiyang Li, H. Dai, Donghui Guo","doi":"10.1109/ICASID.2010.5551512","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551512","url":null,"abstract":"Cloud computing is usually defined to deliver infrastructure, platform and software as services, which is available as a pay-as-you-go model for users. A paradigm of Cloud computing for EDA service is presented in this paper, and a hierarchical architecture of Web-EDA system implemented with Cloud computing is described in detail. Based on this proposed system structure, we developed a prototype of the Web-EDA system for sharing EDA Tools and project management of IC design. It shows that Cloud computing for EDA service is possible to be implemented distributedly and brings maximum benefit to both users and vendors.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123468391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551832
Zhichao Liu, Yunfeng Wang, Tianxiang Liu
In this paper, the implementation and reconfigurable feature of RSA and AES cryptographic algorithm are analyzed. On the basis of the Reconfigurable design of this two algorithms, Reconfigurable RSA and AES hardware architecture is designed to fit four different key length of 256bit, 512bit, 1024bit, 2048bit for RSA, and three different key length of 128bit, 192bit, and 256bit for AES. The reconfigurable design and testing are carried out on FPGA, the results showed that it is able to meet the high-performance information security systems encryption algorithm on the speed requirement.
{"title":"Research on the implementation of trusted platform module based on reconfigurable computing","authors":"Zhichao Liu, Yunfeng Wang, Tianxiang Liu","doi":"10.1109/ICASID.2010.5551832","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551832","url":null,"abstract":"In this paper, the implementation and reconfigurable feature of RSA and AES cryptographic algorithm are analyzed. On the basis of the Reconfigurable design of this two algorithms, Reconfigurable RSA and AES hardware architecture is designed to fit four different key length of 256bit, 512bit, 1024bit, 2048bit for RSA, and three different key length of 128bit, 192bit, and 256bit for AES. The reconfigurable design and testing are carried out on FPGA, the results showed that it is able to meet the high-performance information security systems encryption algorithm on the speed requirement.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121622060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-18DOI: 10.1109/ICASID.2010.5551516
Shuming Yang, Yongsheng Yin, Honghui Deng
A new type of voltage reference which can be controlled in the outer-chip by the external pins and can generate an arbitrary reference voltage was introduced in this paper. There is a resistor serial in the reference voltage circuit that can generate 4 different reference voltages by the internal control logic circuit to adapt to fit different situations demand. The core circuit employs the improved Brokaw architecture. The entire circuit is in 0.18um CMOS process and the power supply voltage is 1.8V. Simulation results using Hspice tools show that different reference voltages can be achieved by corresponding configurations of external pins; or can output 4 fixed reference voltages controlled by the internal logic signals. When the temperature ranges from −40 to 120°C, the reference voltage circuit can reach to a low temperature coefficient (8.5ppm/°C) and a high power supply rejection ratio that is −110.2dB.1
{"title":"Design of an outer-chip controllable and inner-chip adjustable voltage reference","authors":"Shuming Yang, Yongsheng Yin, Honghui Deng","doi":"10.1109/ICASID.2010.5551516","DOIUrl":"https://doi.org/10.1109/ICASID.2010.5551516","url":null,"abstract":"A new type of voltage reference which can be controlled in the outer-chip by the external pins and can generate an arbitrary reference voltage was introduced in this paper. There is a resistor serial in the reference voltage circuit that can generate 4 different reference voltages by the internal control logic circuit to adapt to fit different situations demand. The core circuit employs the improved Brokaw architecture. The entire circuit is in 0.18um CMOS process and the power supply voltage is 1.8V. Simulation results using Hspice tools show that different reference voltages can be achieved by corresponding configurations of external pins; or can output 4 fixed reference voltages controlled by the internal logic signals. When the temperature ranges from −40 to 120°C, the reference voltage circuit can reach to a low temperature coefficient (8.5ppm/°C) and a high power supply rejection ratio that is −110.2dB.1","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121622239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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