Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658391
T. Kurashige, J. Shiokawa, H. Chiba, N. Yamamoto, T. Kitade, H. Tarumizu, H. Kami, T. Imai
We have developed a handy digital camera to record MPEG-1 video and JPEG still photo. The newly developed camera signal processing LSI and real-time MPEG-1 codec LSI compress and decompress images, and a RISC MPU, SH-3, does MPEG-1 audio compression and decompression. We adopt PC card type HDD to record compressed image and audio instead of tape media for easy file handling and high adaptability with PC. Users are able to arrange, retrieve and playback files on the camera easily using the 1.8" TFT-LCD and "Media Navigation System", the built-in file handling function.
{"title":"Development of MPEG camera","authors":"T. Kurashige, J. Shiokawa, H. Chiba, N. Yamamoto, T. Kitade, H. Tarumizu, H. Kami, T. Imai","doi":"10.1109/ISCE.1997.658391","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658391","url":null,"abstract":"We have developed a handy digital camera to record MPEG-1 video and JPEG still photo. The newly developed camera signal processing LSI and real-time MPEG-1 codec LSI compress and decompress images, and a RISC MPU, SH-3, does MPEG-1 audio compression and decompression. We adopt PC card type HDD to record compressed image and audio instead of tape media for easy file handling and high adaptability with PC. Users are able to arrange, retrieve and playback files on the camera easily using the 1.8\" TFT-LCD and \"Media Navigation System\", the built-in file handling function.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126183180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658409
B. Frankston
The Internet is the new infrastructure. It requires that we rethink the nature of devices. They no longer need be isolated. The cost of tapping into the global network is very low and the new capabilities are compelling. The designs need not be limited by what the device can do alone. We need to learn how to create such devices. What capabilities should be available locally and which can be shifted to a more sophisticated device such as a personal computer. How does a device maintain a relationship to the manufacturer? In order to take advantage of these opportunities we need simple and robust protocols. Unlike an isolated device where one manufacturer can take full responsibility for the devices' function, the new device can be affected by the misbehavior of other devices and must be resilient even when other devices fail. A device that cannot cooperate with other devices will be like the typewriter-a story for one's grandchildren. Like the days we used to multiply numbers by using a slide rule.
{"title":"The Internet and consumer electronics","authors":"B. Frankston","doi":"10.1109/ISCE.1997.658409","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658409","url":null,"abstract":"The Internet is the new infrastructure. It requires that we rethink the nature of devices. They no longer need be isolated. The cost of tapping into the global network is very low and the new capabilities are compelling. The designs need not be limited by what the device can do alone. We need to learn how to create such devices. What capabilities should be available locally and which can be shifted to a more sophisticated device such as a personal computer. How does a device maintain a relationship to the manufacturer? In order to take advantage of these opportunities we need simple and robust protocols. Unlike an isolated device where one manufacturer can take full responsibility for the devices' function, the new device can be affected by the misbehavior of other devices and must be resilient even when other devices fail. A device that cannot cooperate with other devices will be like the typewriter-a story for one's grandchildren. Like the days we used to multiply numbers by using a slide rule.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127584545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658377
Chichyang Chen, Te-Lung Lin
We proposed a new video coding method that results in a lower bit-rate than the MPEG-1 method. Instead of dividing the image frames into 8/spl times/8 blocks, the frames are triangulated according to a set of control points. The control points and the edges of the triangular blocks are located at the edge features in the image. These control points in the sequence are tracked and their motion is encoded and sent to the decoder. The prediction error is computed as the difference between the original image and the estimated image that is reconstructed by warping the corresponding triangular blocks in the previous frame. The prediction error is encoded using vector quantization (VQ). Experimental results show that the bit-rate needed to encode the Susie sequence is about one-fourth the bit-rate needed in the MPEG-1 method. By properly selecting the number and position of the control points, it is expected that very low bit-rate video coding can be achieved.
{"title":"Low bit-rate video coding using image triangulation and warping","authors":"Chichyang Chen, Te-Lung Lin","doi":"10.1109/ISCE.1997.658377","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658377","url":null,"abstract":"We proposed a new video coding method that results in a lower bit-rate than the MPEG-1 method. Instead of dividing the image frames into 8/spl times/8 blocks, the frames are triangulated according to a set of control points. The control points and the edges of the triangular blocks are located at the edge features in the image. These control points in the sequence are tracked and their motion is encoded and sent to the decoder. The prediction error is computed as the difference between the original image and the estimated image that is reconstructed by warping the corresponding triangular blocks in the previous frame. The prediction error is encoded using vector quantization (VQ). Experimental results show that the bit-rate needed to encode the Susie sequence is about one-fourth the bit-rate needed in the MPEG-1 method. By properly selecting the number and position of the control points, it is expected that very low bit-rate video coding can be achieved.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123208421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658370
S. Mozar
Medium to high end colour TVs that are designed for an international market must operate over a wide mains voltage range, which typically images from 90 V/sub AC/ to 276 V/sub AC/. To achieve operation over this wide mains voltage range, at the power levels that these sets require, a voltage doubler circuit is required at the front end. The doubler circuit consists of two electrolytic capacitors, which are rated at 100 V in order to comply with IEC65 requirements. This paper proposes an "electrolytic capacitor protection circuit" which enables the voltage rating of the electrolytics to be reduced to 250 V. This patented circuit results in cost savings of more than 50% in the price of the electrolytic filter capacitors. This represents substantial savings, especially for mass produced items like TV sets. Therefore, what may at first appear to be an unnecessary circuit, may from a financial point of view be very desirable.
{"title":"Voltage doubler protection circuit results in large cost savings","authors":"S. Mozar","doi":"10.1109/ISCE.1997.658370","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658370","url":null,"abstract":"Medium to high end colour TVs that are designed for an international market must operate over a wide mains voltage range, which typically images from 90 V/sub AC/ to 276 V/sub AC/. To achieve operation over this wide mains voltage range, at the power levels that these sets require, a voltage doubler circuit is required at the front end. The doubler circuit consists of two electrolytic capacitors, which are rated at 100 V in order to comply with IEC65 requirements. This paper proposes an \"electrolytic capacitor protection circuit\" which enables the voltage rating of the electrolytics to be reduced to 250 V. This patented circuit results in cost savings of more than 50% in the price of the electrolytic filter capacitors. This represents substantial savings, especially for mass produced items like TV sets. Therefore, what may at first appear to be an unnecessary circuit, may from a financial point of view be very desirable.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128197697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658345
L.J. Luo, J.S. Chang, Y. Tong
In this paper, we present the design and IC implementation of a 3V micropower programmable transconductance-C (g/sub m/-C) filter set for hearing aid applications. The filter set comprises 3 biquads, including a proposed high pass biquad which features the simplest structure to date. The filter set features a novel architecture in that it may be configured as a single 3-channel device or a single or cascade of two or three biquads. This filter set was implemented in IC with an area of 2.4/spl times/2.6 mm/sup 2/ using a 1.2 /spl mu/m CMOS process. The measurement results show that the prototype ICs dissipated a maximum of 250 /spl mu/W.
{"title":"A 3V micropower programmable g/sub m/-C filter set for hearing aids","authors":"L.J. Luo, J.S. Chang, Y. Tong","doi":"10.1109/ISCE.1997.658345","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658345","url":null,"abstract":"In this paper, we present the design and IC implementation of a 3V micropower programmable transconductance-C (g/sub m/-C) filter set for hearing aid applications. The filter set comprises 3 biquads, including a proposed high pass biquad which features the simplest structure to date. The filter set features a novel architecture in that it may be configured as a single 3-channel device or a single or cascade of two or three biquads. This filter set was implemented in IC with an area of 2.4/spl times/2.6 mm/sup 2/ using a 1.2 /spl mu/m CMOS process. The measurement results show that the prototype ICs dissipated a maximum of 250 /spl mu/W.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123534945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658385
Wanshi Chen, M. A. Do
A novel adaptive two-stage multiuser detector is proposed for synchronous DS-CDMA communication systems. This new multiuser detector employs the first-order approximate decorrelating detector as the first stage followed by an adaptive canceller. The steepest descent algorithm is used to control the weights of the adaptive canceller. Through analysis and numerical results, we show that the proposed detector results in a better error probability than that of the conventional detector and the decorrelating detector, especially when the multiple access interference (MAI) is high.
{"title":"A novel adaptive two-stage detector for synchronous DS-CDMA communication systems","authors":"Wanshi Chen, M. A. Do","doi":"10.1109/ISCE.1997.658385","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658385","url":null,"abstract":"A novel adaptive two-stage multiuser detector is proposed for synchronous DS-CDMA communication systems. This new multiuser detector employs the first-order approximate decorrelating detector as the first stage followed by an adaptive canceller. The steepest descent algorithm is used to control the weights of the adaptive canceller. Through analysis and numerical results, we show that the proposed detector results in a better error probability than that of the conventional detector and the decorrelating detector, especially when the multiple access interference (MAI) is high.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127922539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658376
Chinchen Chang, Lin-Li Chen, Tung-Shou Chen
Block matching can reduce temporal redundancies. It is an important scheme in video compression. So far, there have been many methods proposed for this scheme, such as fixed-sized block matching (FSBM), top-down variable-sized block matching (TDVSBM), and bottom-up variable-sized block matching (BUVSBM). In these methods, the blocks in each frame of a video must be square, and that is why some objects in the frame cannot be described correctly. To remedy this problem, we propose a new block matching method. In this new method, the blocks in each frame of a video do not need to be square. Moreover, all kinds of combinations of small blocks are taken into consideration. Because our block shapes are dynamic, all objects in the frame can be described clearly, and, under the same number of blocks in each frame, our new method can generate better image quality than FSBM, TDVSBM, and BUVSBM. This phenomenon is proven in our experimental results.
{"title":"An improvement of bottom-up variable-sized block matching technique for video compression","authors":"Chinchen Chang, Lin-Li Chen, Tung-Shou Chen","doi":"10.1109/ISCE.1997.658376","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658376","url":null,"abstract":"Block matching can reduce temporal redundancies. It is an important scheme in video compression. So far, there have been many methods proposed for this scheme, such as fixed-sized block matching (FSBM), top-down variable-sized block matching (TDVSBM), and bottom-up variable-sized block matching (BUVSBM). In these methods, the blocks in each frame of a video must be square, and that is why some objects in the frame cannot be described correctly. To remedy this problem, we propose a new block matching method. In this new method, the blocks in each frame of a video do not need to be square. Moreover, all kinds of combinations of small blocks are taken into consideration. Because our block shapes are dynamic, all objects in the frame can be described clearly, and, under the same number of blocks in each frame, our new method can generate better image quality than FSBM, TDVSBM, and BUVSBM. This phenomenon is proven in our experimental results.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126893610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658380
H. Ohtsubo, T. Fujihira, K. Asada, T. Imaide
We have developed a low power MPEG1/JPEG encode/decode single chip LSI (codec). On the development of the codec, we have developed a new compact motion estimation (ME) process which reduced the number of gates and the power consumption to about a quarter and 1/8 of those of the conventional ME process respectively, while keeping good quality of picture. With the new ME process and power management function all over the codec chip, we realized the low power consumption of the codec. Total power consumption of the codec is only 500 mW. With this chip, we have also realized the first digital camera with an MPEG1 stream in the world.
{"title":"1 chip low power MPEG1 codec with compact motion estimation","authors":"H. Ohtsubo, T. Fujihira, K. Asada, T. Imaide","doi":"10.1109/ISCE.1997.658380","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658380","url":null,"abstract":"We have developed a low power MPEG1/JPEG encode/decode single chip LSI (codec). On the development of the codec, we have developed a new compact motion estimation (ME) process which reduced the number of gates and the power consumption to about a quarter and 1/8 of those of the conventional ME process respectively, while keeping good quality of picture. With the new ME process and power management function all over the codec chip, we realized the low power consumption of the codec. Total power consumption of the codec is only 500 mW. With this chip, we have also realized the first digital camera with an MPEG1 stream in the world.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128443552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658375
G. Ashraf, M. Chong
Video compression algorithms continue to forge video applications to increasingly lower bandwidths. The onus at present is to enable real time video transmission on the telephone lines and the wireless network. H.263 is one of the latest video coding standards that proposes several enhancements to the H.261 video coding algorithm. This paper presents a comparison of these two standard video codecs, namely H.261 and H.263. The parameters of comparison are the degree of compression and peak signal to noise ratio (PSNR) achieved by these codecs. The paper also evaluates the behaviour of H.263 at different bit rates with various optional modes active. From the results obtained, it is concluded that H.263 performs best at very low bit rates (28.8 kHz and below), and existing codecs could perform much better if certain features of the H.263 guidelines are incorporated into them.
{"title":"Performance analysis of H.261 and H.263 video coding algorithms","authors":"G. Ashraf, M. Chong","doi":"10.1109/ISCE.1997.658375","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658375","url":null,"abstract":"Video compression algorithms continue to forge video applications to increasingly lower bandwidths. The onus at present is to enable real time video transmission on the telephone lines and the wireless network. H.263 is one of the latest video coding standards that proposes several enhancements to the H.261 video coding algorithm. This paper presents a comparison of these two standard video codecs, namely H.261 and H.263. The parameters of comparison are the degree of compression and peak signal to noise ratio (PSNR) achieved by these codecs. The paper also evaluates the behaviour of H.263 at different bit rates with various optional modes active. From the results obtained, it is concluded that H.263 performs best at very low bit rates (28.8 kHz and below), and existing codecs could perform much better if certain features of the H.263 guidelines are incorporated into them.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127294684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-12-02DOI: 10.1109/ISCE.1997.658349
C.L. Lee
A parallel motion compensation architecture is proposed for an HDTV video decoder. It is based on block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solutions for a parallel HDTV video decoder.
{"title":"Parallel implementation of motion-compensation for HDTV video decoder","authors":"C.L. Lee","doi":"10.1109/ISCE.1997.658349","DOIUrl":"https://doi.org/10.1109/ISCE.1997.658349","url":null,"abstract":"A parallel motion compensation architecture is proposed for an HDTV video decoder. It is based on block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solutions for a parallel HDTV video decoder.","PeriodicalId":393861,"journal":{"name":"ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132049481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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