In recent years, the increase of energy demand and the problems of fossil-fuel sources due to their environmental pollution and future shortages, have led to the development of technologies need to use non-polluting alternative energy sources such as solar and wind sources. Growing demand, advancements in semiconductor technology and magnetic materials such as high frequency inductor cores, has a significant impact on PV inverter topologies and their efficiencies, on the improvement of the control circuits on the potential of costs reduction. The user naturally wants to operate the Photovoltaic (PV) array at its highest energy conversion output by continuously utilizing the maximum available solar power of the array. The electrical system PV modules are powered by solar arrays requires special design considerations due to varying nature of the solar power generated resulting from unpredictable and sudden changes in weather conditions which change the solar irradiation level as well as the cell operating temperature. This work proposes on Evolutionary computing Based Multilevel H-Bridge Cascaded Inverter for Photovoltaic System with simple PWM Technique, to have the advantages of low frequency switching and reduced total harmonic distortion (THD).
{"title":"Evolutionary Computing Based Multilevel H-bridge Cascaded Inverter with Photovoltaic System","authors":"J. Kumari, C. Babu, D. Lenine","doi":"10.1109/ARTCOM.2010.17","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.17","url":null,"abstract":"In recent years, the increase of energy demand and the problems of fossil-fuel sources due to their environmental pollution and future shortages, have led to the development of technologies need to use non-polluting alternative energy sources such as solar and wind sources. Growing demand, advancements in semiconductor technology and magnetic materials such as high frequency inductor cores, has a significant impact on PV inverter topologies and their efficiencies, on the improvement of the control circuits on the potential of costs reduction. The user naturally wants to operate the Photovoltaic (PV) array at its highest energy conversion output by continuously utilizing the maximum available solar power of the array. The electrical system PV modules are powered by solar arrays requires special design considerations due to varying nature of the solar power generated resulting from unpredictable and sudden changes in weather conditions which change the solar irradiation level as well as the cell operating temperature. This work proposes on Evolutionary computing Based Multilevel H-Bridge Cascaded Inverter for Photovoltaic System with simple PWM Technique, to have the advantages of low frequency switching and reduced total harmonic distortion (THD).","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128586125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new non-recursive algorithm for reconstructing a binary tree from its traversals. Binary tree traversal refers to the process of visiting each node in a specified order. Given the in order traversal of a binary tree, along with one of its preorder or post order traversals, the original binary tree can be uniquely identified. This algorithm is efficient and requires O(n) time and O(n) space. The implementation of this algorithm was done in C and the complete algorithm was tested. The new algorithm was found to be faster than other non-recursive algorithms.
{"title":"A New Non-recursive Algorithm for Reconstructing a Binary Tree from its Traversals","authors":"V. V. Das","doi":"10.1109/ARTCOM.2010.88","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.88","url":null,"abstract":"This paper presents a new non-recursive algorithm for reconstructing a binary tree from its traversals. Binary tree traversal refers to the process of visiting each node in a specified order. Given the in order traversal of a binary tree, along with one of its preorder or post order traversals, the original binary tree can be uniquely identified. This algorithm is efficient and requires O(n) time and O(n) space. The implementation of this algorithm was done in C and the complete algorithm was tested. The new algorithm was found to be faster than other non-recursive algorithms.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125480409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital video technology is burgeoning new standards broadening the gamut of prerequisites such as high definition video quality and more resolution substantially at lower bit rates than previous standards. Among the latest video compression algorithms, the newly established H.264 standard has become increasingly popular. However, the high coding efficiency of it comes at the cost of increase in computational complexity which makes the real-time implementation a great challenge. Previous works in video compression implement a dual core DSP processor executing this composite H.264 algorithm in parts, but has certain bottlenecks like timing, reliability and efficiency with a small overhead of synchronization. With higher interprocessor bus speeds, streamlined memory and a highly programmable FPGA multi-core architecture the limitations of current platforms based on DSPs and ASICs can be overwhelmed. This paper presents an FPGA based multicore processor implementation to optimize the H.264 encoder performance between the cores providing scalability, attaining load balance among the cores and parallel execution reducing the dependability of resources. This enables a more effectual use of processing power of the cores.
{"title":"FPGA Based Symmetric Multi-core Processors for Optimized Performance of H.264 Encoder","authors":"E. MuraliKrishnan, E. Gangadharan, P. Nirmalkumar","doi":"10.1109/ARTCOM.2010.106","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.106","url":null,"abstract":"Digital video technology is burgeoning new standards broadening the gamut of prerequisites such as high definition video quality and more resolution substantially at lower bit rates than previous standards. Among the latest video compression algorithms, the newly established H.264 standard has become increasingly popular. However, the high coding efficiency of it comes at the cost of increase in computational complexity which makes the real-time implementation a great challenge. Previous works in video compression implement a dual core DSP processor executing this composite H.264 algorithm in parts, but has certain bottlenecks like timing, reliability and efficiency with a small overhead of synchronization. With higher interprocessor bus speeds, streamlined memory and a highly programmable FPGA multi-core architecture the limitations of current platforms based on DSPs and ASICs can be overwhelmed. This paper presents an FPGA based multicore processor implementation to optimize the H.264 encoder performance between the cores providing scalability, attaining load balance among the cores and parallel execution reducing the dependability of resources. This enables a more effectual use of processing power of the cores.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127313341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Detection and localization of face in colour images with skin tone regions involves many challenges. This paper proposes an algorithm that uses a combination of wavelets, edge detection techniques to improve the efficiency during segmentation and feature extraction stage. Experimental results using the proposed algorithm presented here show improved false acceptance and false rejection rates.
{"title":"Face Detection and Localization in Skin Toned Color Images Using Wavelet and Edge Detection Techniques","authors":"H. Lakshmi, S. Patilkulkarni","doi":"10.1109/ARTCOM.2010.34","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.34","url":null,"abstract":"Detection and localization of face in colour images with skin tone regions involves many challenges. This paper proposes an algorithm that uses a combination of wavelets, edge detection techniques to improve the efficiency during segmentation and feature extraction stage. Experimental results using the proposed algorithm presented here show improved false acceptance and false rejection rates.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116822811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Chanda, S. Naha, S. Manna, A. Dandapat, H. Rahaman
The paper presents the implementation of ultra low power 8 bit carry look ahead adder circuit operated by single-phase adiabatic dynamic logic (SPADL) which, unlike any other existing adiabatic logic family, uses single sinusoidal supply-clock. This not only ensures higher energy efficiency, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. Static logic resembled characteristics of SPADL logic substantially decreases circuit complexity with improved driving ability and circuit robustness. in TSMC 0.18μm CMOS technology. CADENCE simulations show that SPADL saves 65% to 50% and 30% to 40% of total energy compared to Conventional CMOS and other existing single phase adiabatic logic based CLA for a frequency of 1MHz to 100MHz.
{"title":"Implementation of Ultra Low-Power 8 Bit CLA Using Single Phase Adiabatic Dynamic Logic","authors":"M. Chanda, S. Naha, S. Manna, A. Dandapat, H. Rahaman","doi":"10.1109/ARTCOM.2010.82","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.82","url":null,"abstract":"The paper presents the implementation of ultra low power 8 bit carry look ahead adder circuit operated by single-phase adiabatic dynamic logic (SPADL) which, unlike any other existing adiabatic logic family, uses single sinusoidal supply-clock. This not only ensures higher energy efficiency, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. Static logic resembled characteristics of SPADL logic substantially decreases circuit complexity with improved driving ability and circuit robustness. in TSMC 0.18μm CMOS technology. CADENCE simulations show that SPADL saves 65% to 50% and 30% to 40% of total energy compared to Conventional CMOS and other existing single phase adiabatic logic based CLA for a frequency of 1MHz to 100MHz.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A Multi-bit output Linear Feedback Shift Register (MBO LFSR) based kernel (computational object) is proposed. This paper describes the results of a study on the required hardware components in the MBO LFSR kernel. The kernel provides an advantage of required programmability in computing hardware of a Software Defined Radio (SDR) along with the low power implementation in processing of digital wireless standards and protocols. The proposed kernel uses shared memory-block architecture. It significantly reduces the energy dissipation in the memory accesses (Paccess). There is dominating effect and energy cost in modulus operation. The kernel replaces modulus operation by an equivalent operation, which drastically reduces the number of machine cycles and thus execution time. The kernel has the characteristics of reduced switching activity. Proper use of LFSR polynomial and a systematic optimization approach at all levels of the design enabled a low power design of the kernel. The MBO LFSR kernel is shown to be applicable in the link encryption of Bluetooth wireless 802.15.1 and OFDM based protocols WLAN 802.11a and WiMAX 802.16 standards. The paper also gives the results for computations for the dynamic power consumption (Pdynamic) in the different kernel components and total Pdynamic for the kernel. The paper also gives the results when using a gated clock for obtaining the lower Pdynamic in the MBO LFSR components. The results of simulating the kernel will be taken up in future to verify the results of the computations.
{"title":"Multi-bit Output LFSR Kernel Architecture for a Low Power Design for the Link Encryption in Bluetooth and WiMAX Protocols in Software Defined Radios","authors":"C. Khairnar, R. Kamal, S. Tokekar","doi":"10.1109/ARTCOM.2010.81","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.81","url":null,"abstract":"A Multi-bit output Linear Feedback Shift Register (MBO LFSR) based kernel (computational object) is proposed. This paper describes the results of a study on the required hardware components in the MBO LFSR kernel. The kernel provides an advantage of required programmability in computing hardware of a Software Defined Radio (SDR) along with the low power implementation in processing of digital wireless standards and protocols. The proposed kernel uses shared memory-block architecture. It significantly reduces the energy dissipation in the memory accesses (Paccess). There is dominating effect and energy cost in modulus operation. The kernel replaces modulus operation by an equivalent operation, which drastically reduces the number of machine cycles and thus execution time. The kernel has the characteristics of reduced switching activity. Proper use of LFSR polynomial and a systematic optimization approach at all levels of the design enabled a low power design of the kernel. The MBO LFSR kernel is shown to be applicable in the link encryption of Bluetooth wireless 802.15.1 and OFDM based protocols WLAN 802.11a and WiMAX 802.16 standards. The paper also gives the results for computations for the dynamic power consumption (Pdynamic) in the different kernel components and total Pdynamic for the kernel. The paper also gives the results when using a gated clock for obtaining the lower Pdynamic in the MBO LFSR components. The results of simulating the kernel will be taken up in future to verify the results of the computations.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116893656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Moushmi Kar, K. Thakur, A. Zadgaonkar, Bikesh Kr. Singh
This study discusses the difficulties of short term analysis of speech signals and shows that appropriate windowing is very crucial for obtaining reliable spectra. Once windowing is performed properly, it reveals clearly Formant information. In this paper we dealt with the effect of windowing in extraction of speech parameter. Choosing a appropriate window consists of selecting the type, length and placement of window. Ideally, the window spectrum would have a narrow main lobe and small side lobes. We design band pass FIR filters for estimation of speech parameters using window methods & compare several standard windows in terms of the parameters that reflect the effect of resolution degradation due to the mainlobe, leakage due to the near side lobe. In this paper attempt was carried out mainly to deal with the effect of side lobe attenuation and optimal side lobe attenuation for standard window function used in short term analysis has been proposed.
{"title":"Appropriate Windowing in Speech Parameter Extraction","authors":"Moushmi Kar, K. Thakur, A. Zadgaonkar, Bikesh Kr. Singh","doi":"10.1109/ARTCOM.2010.12","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.12","url":null,"abstract":"This study discusses the difficulties of short term analysis of speech signals and shows that appropriate windowing is very crucial for obtaining reliable spectra. Once windowing is performed properly, it reveals clearly Formant information. In this paper we dealt with the effect of windowing in extraction of speech parameter. Choosing a appropriate window consists of selecting the type, length and placement of window. Ideally, the window spectrum would have a narrow main lobe and small side lobes. We design band pass FIR filters for estimation of speech parameters using window methods & compare several standard windows in terms of the parameters that reflect the effect of resolution degradation due to the mainlobe, leakage due to the near side lobe. In this paper attempt was carried out mainly to deal with the effect of side lobe attenuation and optimal side lobe attenuation for standard window function used in short term analysis has been proposed.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117065402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Orthogonal Frequency Division Multiplexing (OFDM) has been currently under intense research for broadband wireless transmission due to its robustness against multipath fading. However OFDM signals have a problem with high Peak-to-Average power ratio (PAPR) and thus, a power amplifier must be carefully manufactured to have a linear input-output characteristic or to have a large input power back-off. In this paper, some of the important PAPR reduction techniques have been compared based on computational complexity, bandwidth expansion, spectral spillage and performance.
{"title":"Performance Analysis of Peak-to-Average Power Ratio Reduction Techniques for Wireless Communication Using OFDM Signals","authors":"P. Sharma, A. Basu","doi":"10.1109/ARTCOM.2010.83","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.83","url":null,"abstract":"Orthogonal Frequency Division Multiplexing (OFDM) has been currently under intense research for broadband wireless transmission due to its robustness against multipath fading. However OFDM signals have a problem with high Peak-to-Average power ratio (PAPR) and thus, a power amplifier must be carefully manufactured to have a linear input-output characteristic or to have a large input power back-off. In this paper, some of the important PAPR reduction techniques have been compared based on computational complexity, bandwidth expansion, spectral spillage and performance.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117209179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A vital role of static task scheduling is to obtain high performance in distributed computing environment. Several algorithms have been proposed for homogeneous and heterogeneous distributed computing systems. In this paper we propose a static list Path based Heuristic Task Scheduling (PHTS) algorithm to efficiently schedule tasks on the heterogeneous distributed computing systems. The algorithm is mainly focused on reducing the makespan. It consists of three phases: A path prioritizing phase, selecting all possible paths from the given graph and sorting them by descending order. Secondly, a task selection phase, selecting the tasks from the sorted paths and finally, a processor selection phase, assigning the tasks to processors which minimizes the completion time. From the theoretical analysis of the PHTS algorithm with HEFT for a DAG graph, the better schedule length is observed.
{"title":"Path-Based Heuristic Task Scheduling Algorithm for Heterogeneous Distributed Computing Systems","authors":"R. Eswari, S. Nickolas","doi":"10.1109/ARTCOM.2010.19","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.19","url":null,"abstract":"A vital role of static task scheduling is to obtain high performance in distributed computing environment. Several algorithms have been proposed for homogeneous and heterogeneous distributed computing systems. In this paper we propose a static list Path based Heuristic Task Scheduling (PHTS) algorithm to efficiently schedule tasks on the heterogeneous distributed computing systems. The algorithm is mainly focused on reducing the makespan. It consists of three phases: A path prioritizing phase, selecting all possible paths from the given graph and sorting them by descending order. Secondly, a task selection phase, selecting the tasks from the sorted paths and finally, a processor selection phase, assigning the tasks to processors which minimizes the completion time. From the theoretical analysis of the PHTS algorithm with HEFT for a DAG graph, the better schedule length is observed.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115655787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Harmonic contamination and low power factor in power systems caused by power converters have been a great concern. The effect of harmonics in current due to lagging power factor are the increase in current flow in the capacitors which results in additional heating of the capacitors and reduce its life, increased magnitudes of neutral currents in three phase systems, over-heating in transformers and induction motors. To overcome these problems several converter topologies and control schemes have been proposed in recent years. This work is proposed to identify the power converters with low cost/small size/high efficiency for single phase systems and also to study the control techniques for such converters to improve the Power Factor (PF) and reduce total harmonic distortion (THD) in the input current with output voltage regulation. This work has very high potential for UPS, motor drives and other industrial applications. A predictive control strategy for power factor correction of AC - DC converter is to maintain the unity power factor. Its basic idea is that all of the duty cycles required to achieve unity power factor in a half line period are generated in advance by using a predictive control topologies. It can be based on the average output voltage in the previous half line period, the duty cycles in the current half line period can be calculated by the predictive control topologies. The operation, analysis and design of control technique for high performance rectifier are investigated and verified through simulation.
{"title":"A Static Improvement of Predictive Control for Single Phase Voltage Fed Power Factor Correction Converters","authors":"D. Lenine, C. Babu, J. Kumari","doi":"10.1109/ARTCOM.2010.16","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.16","url":null,"abstract":"Harmonic contamination and low power factor in power systems caused by power converters have been a great concern. The effect of harmonics in current due to lagging power factor are the increase in current flow in the capacitors which results in additional heating of the capacitors and reduce its life, increased magnitudes of neutral currents in three phase systems, over-heating in transformers and induction motors. To overcome these problems several converter topologies and control schemes have been proposed in recent years. This work is proposed to identify the power converters with low cost/small size/high efficiency for single phase systems and also to study the control techniques for such converters to improve the Power Factor (PF) and reduce total harmonic distortion (THD) in the input current with output voltage regulation. This work has very high potential for UPS, motor drives and other industrial applications. A predictive control strategy for power factor correction of AC - DC converter is to maintain the unity power factor. Its basic idea is that all of the duty cycles required to achieve unity power factor in a half line period are generated in advance by using a predictive control topologies. It can be based on the average output voltage in the previous half line period, the duty cycles in the current half line period can be calculated by the predictive control topologies. The operation, analysis and design of control technique for high performance rectifier are investigated and verified through simulation.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"26 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114117193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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