Dominance of on-chip power densities has become a critical design constraint in high-performance VLSI design. This is primarily due to increased technology scaling, number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entail the stacking of multiple active (device) layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the thermal placement of standard cells and gate arrays (modules) taking total wire-length as well as TSVs (through silicon via) into consideration. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of the active layers are not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer, (iv) the estimated total interconnect lengths connecting the modules of the different layers are also improved, and (v) the total number of interlayer vias is quite reasonable. Experimental results on randomly generated and standard benchmark instances are encouraging.
{"title":"Thermal Aware Placement in 3D ICs","authors":"P. Ghosal, H. Rahaman, P. Dasgupta","doi":"10.1109/ARTCOM.2010.55","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.55","url":null,"abstract":"Dominance of on-chip power densities has become a critical design constraint in high-performance VLSI design. This is primarily due to increased technology scaling, number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entail the stacking of multiple active (device) layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the thermal placement of standard cells and gate arrays (modules) taking total wire-length as well as TSVs (through silicon via) into consideration. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of the active layers are not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer, (iv) the estimated total interconnect lengths connecting the modules of the different layers are also improved, and (v) the total number of interlayer vias is quite reasonable. Experimental results on randomly generated and standard benchmark instances are encouraging.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125404063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7% and 39.9% in terms of power dissipation, power delay product and total transistor width respectively. At scaled voltages, the power consumption of the proposed design reduces by 34% and hence the design is suitable for low power, low voltage and high density applications.
{"title":"A Low Power High Density Double Edge Triggered Flip Flop for Low Voltage Systems","authors":"S. Tiwari, Kunwar Singh, Maneesha Gupta","doi":"10.1109/ARTCOM.2010.64","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.64","url":null,"abstract":"The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7% and 39.9% in terms of power dissipation, power delay product and total transistor width respectively. At scaled voltages, the power consumption of the proposed design reduces by 34% and hence the design is suitable for low power, low voltage and high density applications.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125428265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An Electrocardiogram (ECG) is a bioelectric signal which detects and records the heart’s electrical activity versus time. It is important diagnostic tool for assessing heart functions. The aim of this project is to develop a system for real time analysis of the cardiac oscillations by a three electrode ECG circuit. The ECG wave is filtered out of noise and amplified to a valuable to be read by an analog to digital converter. The data is fetched by data acquisition system and send to the PC, where ECG and its features are continuously monitored. The ECG features supplies evidence for the diagnoses of cardiac diseases.
{"title":"PC Based ECG Monitoring System","authors":"Gaytri Gupta","doi":"10.1109/ARTCOM.2010.32","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.32","url":null,"abstract":"An Electrocardiogram (ECG) is a bioelectric signal which detects and records the heart’s electrical activity versus time. It is important diagnostic tool for assessing heart functions. The aim of this project is to develop a system for real time analysis of the cardiac oscillations by a three electrode ECG circuit. The ECG wave is filtered out of noise and amplified to a valuable to be read by an analog to digital converter. The data is fetched by data acquisition system and send to the PC, where ECG and its features are continuously monitored. The ECG features supplies evidence for the diagnoses of cardiac diseases.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"388 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122846762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Circuit partitioning plays an important role in physical design automation of very large scale integration (VLSI) chips. The interest in finding an optimal partitioning especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. To enhance, other criterion like power, delay and area in addition to minimum cut is included. Memetic Algorithm (MA) is an evolutionary algorithm that includes one or more local search phases within its evolutionary cycle. MA applies some sort of local search for optimization of VLSI partitioning. The algorithm combines a hierarchical design technique, Genetic algorithm and constructive techniques like Simulated Annealing for local search to solve VLSI partitioning problem. MA quickly produces optimal solution for the entire popular benchmark problem. The result will be compared with the previous work result
{"title":"A Novel Approach to Find the Best Fit for VLSI Partitioning - Physical Design","authors":"I. Shanavas, R. K. Gnanamurthy, T. Thangaraj","doi":"10.1109/ARTCOM.2010.93","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.93","url":null,"abstract":"Circuit partitioning plays an important role in physical design automation of very large scale integration (VLSI) chips. The interest in finding an optimal partitioning especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. To enhance, other criterion like power, delay and area in addition to minimum cut is included. Memetic Algorithm (MA) is an evolutionary algorithm that includes one or more local search phases within its evolutionary cycle. MA applies some sort of local search for optimization of VLSI partitioning. The algorithm combines a hierarchical design technique, Genetic algorithm and constructive techniques like Simulated Annealing for local search to solve VLSI partitioning problem. MA quickly produces optimal solution for the entire popular benchmark problem. The result will be compared with the previous work result","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130611343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present DAC for multiple valued system by utilizing pseudo floating gate (PFG) transistor. It has an advantage to operate the gate in continuous mode The avoidance of recharging floating gate is shown and simulation result is provided.
{"title":"Multiple-Input Multiple-Valued Pseudo-floating Gate DAC","authors":"M. V. Mankar, S. Hajare","doi":"10.1109/ARTCOM.2010.100","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.100","url":null,"abstract":"In this paper we present DAC for multiple valued system by utilizing pseudo floating gate (PFG) transistor. It has an advantage to operate the gate in continuous mode The avoidance of recharging floating gate is shown and simulation result is provided.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125305414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A wireless network consisting of a large number of small sensors with low-power transceivers can be an effective tool for gathering data in a variety of environments. The data collected by each sensor is communicated through the network to a single processing centre that uses all reported data to determine characteristics of the environment or detect an event. The communication or message passing process must be designed to conserve the limited energy resources of the sensors. The sensors communicate information only to cluster heads and then the cluster heads communicate the aggregated information to the processing centre, may save energy. This paper proposed genetic algorithm for wireless sensor network for random behaviour of the node. The algorithm is implemented in java eclipse environment. This paper considered variable byte size and the variable distance. The simulation results showed that the proposed Genetic algorithm extend the network lifetime for random network deployment environments.
{"title":"Efficient Energy Consumption in Two Tiered Sensor Networks Using Genetic Algorithm","authors":"P. Vidyasagar, S. Sawarkar, A. Gawande","doi":"10.1109/ARTCOM.2010.89","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.89","url":null,"abstract":"A wireless network consisting of a large number of small sensors with low-power transceivers can be an effective tool for gathering data in a variety of environments. The data collected by each sensor is communicated through the network to a single processing centre that uses all reported data to determine characteristics of the environment or detect an event. The communication or message passing process must be designed to conserve the limited energy resources of the sensors. The sensors communicate information only to cluster heads and then the cluster heads communicate the aggregated information to the processing centre, may save energy. This paper proposed genetic algorithm for wireless sensor network for random behaviour of the node. The algorithm is implemented in java eclipse environment. This paper considered variable byte size and the variable distance. The simulation results showed that the proposed Genetic algorithm extend the network lifetime for random network deployment environments.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122965549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Transmission Control Protocol (TCP) was designed to provide reliable end-to-end delivery of data over unreliable networks. In practice, most TCP deployments have been carefully designed in the context of wired networks. Ignoring the properties of wireless Ad Hoc Networks can lead to TCP implementations with poor performance. In this paper, an overview of this issue and a detailed discussion of the major factors involved have been presented. In particular, it has been shown how TCP can be affected by mobility and lower layers protocols. To make routing protocols aware of lost data packets and ACKs and help reduce TCP timeouts for mobility induced losses, there are two mechanisms: early packet loss notification (EPLN) and best effort ACK delivery (BEAD). EPLN seeks to notify TCP senders about lost data packets. A new technique for improving TCP performance in an ad hoc network that uses a table driven type of routing protocol paying attention to short-duration link failure has been described. The effect of the collision of a data packet and an ACK packet is suppressed by Delayed ACK and resending the ACK packet preferentially has also been evaluated. Through simulation, it has been shown that the combination of these improvements can increase TCP throughput about 20%. TCP performance over a mobile wireless link in different realistic scenarios has been explored in the paper. A simple method to combine a physical layer modeling and a network simulation using the network simulator ns-2 is being used. The results of the propagation channel simulation and the results of the corresponding network simulation using TCP protocol have been presented. The proposed approach demonstrates that in order to improve TCP performance over wireless links, one need not only to tune the parameters of TCP but also to modify the TCP semantics.
{"title":"A Modified Approach for Measuring TCP Performance in Wireless Adhoc Network","authors":"N. Sengottaiyan, R. Somasundaram, S. Arumugam","doi":"10.1109/ARTCOM.2010.96","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.96","url":null,"abstract":"The Transmission Control Protocol (TCP) was designed to provide reliable end-to-end delivery of data over unreliable networks. In practice, most TCP deployments have been carefully designed in the context of wired networks. Ignoring the properties of wireless Ad Hoc Networks can lead to TCP implementations with poor performance. In this paper, an overview of this issue and a detailed discussion of the major factors involved have been presented. In particular, it has been shown how TCP can be affected by mobility and lower layers protocols. To make routing protocols aware of lost data packets and ACKs and help reduce TCP timeouts for mobility induced losses, there are two mechanisms: early packet loss notification (EPLN) and best effort ACK delivery (BEAD). EPLN seeks to notify TCP senders about lost data packets. A new technique for improving TCP performance in an ad hoc network that uses a table driven type of routing protocol paying attention to short-duration link failure has been described. The effect of the collision of a data packet and an ACK packet is suppressed by Delayed ACK and resending the ACK packet preferentially has also been evaluated. Through simulation, it has been shown that the combination of these improvements can increase TCP throughput about 20%. TCP performance over a mobile wireless link in different realistic scenarios has been explored in the paper. A simple method to combine a physical layer modeling and a network simulation using the network simulator ns-2 is being used. The results of the propagation channel simulation and the results of the corresponding network simulation using TCP protocol have been presented. The proposed approach demonstrates that in order to improve TCP performance over wireless links, one need not only to tune the parameters of TCP but also to modify the TCP semantics.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123951822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In today's fast-changing, competitive environment, a complaint frequently heard by data warehouse users is that access to time-critical data is too slow. Shrinking batch windows and data volume that increases exponentially are placing increasing demands on data warehouses to deliver instantly-available information. Additionally, data warehouses must be able to consistently generate accurate results. But achieving accuracy and speed with large, diverse sets of data can be challenging. Various operations can be used to optimize data manipulation and thus accelerate data warehouse processes. In this paper we have introduced two such operations: 1. Join and 2. Aggregation – which will play an integral role during preprocessing as well in manipulating and consolidating data in a data warehouse. Our approach demonstrate how we can save hours or even days, when processing large amounts of data for ETL, data warehousing, business intelligence (BI) and other mission critical applications.
{"title":"Speeding ETL Processing in Data Warehouses Using High-Performance Joins for Changed Data Capture (CDC)","authors":"D. Tank, A. Ganatra, Y. Kosta, C. Bhensdadia","doi":"10.1109/ARTCOM.2010.63","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.63","url":null,"abstract":"In today's fast-changing, competitive environment, a complaint frequently heard by data warehouse users is that access to time-critical data is too slow. Shrinking batch windows and data volume that increases exponentially are placing increasing demands on data warehouses to deliver instantly-available information. Additionally, data warehouses must be able to consistently generate accurate results. But achieving accuracy and speed with large, diverse sets of data can be challenging. Various operations can be used to optimize data manipulation and thus accelerate data warehouse processes. In this paper we have introduced two such operations: 1. Join and 2. Aggregation – which will play an integral role during preprocessing as well in manipulating and consolidating data in a data warehouse. Our approach demonstrate how we can save hours or even days, when processing large amounts of data for ETL, data warehousing, business intelligence (BI) and other mission critical applications.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124305983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jithin P. Thomas, K. Kumar, Vamsidhar Addanki, Anu Gupta, N. Chaturvedi
The present day software approaches for fingerprint identification systems, are very slow and computationally complex, and hence the user has to wait for a long time before being granted access. The hardware version of the same system is much faster and reliable. We proceed by exploring a new tool in MATLAB in order to describe this system. Three blocks in the fingerprint system flow have been designed and synthesized for use in real time applications.
{"title":"Hardware Implementation of a Biometric Fingerprint Identification System with Embedded Matlab","authors":"Jithin P. Thomas, K. Kumar, Vamsidhar Addanki, Anu Gupta, N. Chaturvedi","doi":"10.1109/ARTCOM.2010.79","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.79","url":null,"abstract":"The present day software approaches for fingerprint identification systems, are very slow and computationally complex, and hence the user has to wait for a long time before being granted access. The hardware version of the same system is much faster and reliable. We proceed by exploring a new tool in MATLAB in order to describe this system. Three blocks in the fingerprint system flow have been designed and synthesized for use in real time applications.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121612999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Divya Mishra, Shailendra Mishra, Dinesh Chandra, B. Kaushik
The paper aims to analyze the effect of crosstalk in dual aggressor environment. The extent of crosstalk noise with the increment in the interconnect length is observed. It also observes the effect on delay with the gradual increment in the interconnect length and extent of reduction in crosstalk voltage on repeater insertion. A three wire multiline model is considered.
{"title":"Crosstalk Estimation in Dual Aggressor Environment","authors":"Divya Mishra, Shailendra Mishra, Dinesh Chandra, B. Kaushik","doi":"10.1109/ARTCOM.2010.92","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.92","url":null,"abstract":"The paper aims to analyze the effect of crosstalk in dual aggressor environment. The extent of crosstalk noise with the increment in the interconnect length is observed. It also observes the effect on delay with the gradual increment in the interconnect length and extent of reduction in crosstalk voltage on repeater insertion. A three wire multiline model is considered.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117173733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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