Face recognition has received an increased attention from several years in the field of image analysis, pattern recognition, and computer vision. In this paper we propose a method to the problem of face recognition. The proposed method consists of two stages. In the first stage regularized linear discriminant analysis is used to extract the most significant and discriminant features and then in the second stage, these features are used by probabilistic reasoning model for classification of unknown face images. Here two databases, the ORL database and the UMIST database are used for experiments and to show the performance of the proposed method.
{"title":"Face Recognition by Regularized-LDA Using PRM","authors":"Lingraj Dora Elect, Telecomm. Engg","doi":"10.1109/ARTCOM.2010.50","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.50","url":null,"abstract":"Face recognition has received an increased attention from several years in the field of image analysis, pattern recognition, and computer vision. In this paper we propose a method to the problem of face recognition. The proposed method consists of two stages. In the first stage regularized linear discriminant analysis is used to extract the most significant and discriminant features and then in the second stage, these features are used by probabilistic reasoning model for classification of unknown face images. Here two databases, the ORL database and the UMIST database are used for experiments and to show the performance of the proposed method.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115400865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A flipped current mirror and a flipped voltage follower suited to low-voltage and low power operation is applied to the design of current conveyors (CCII). A new topology (class-A )is proposed operating at 1.5v and featuring simplicity, compactness, low power consumption and bandwidths up to 100 MHz for a 0.5μm CMOS technology.
{"title":"A Compact Second Generation Current Conveyor(CCII)","authors":"A. Naik, N. Devashrayee","doi":"10.1109/ARTCOM.2010.108","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.108","url":null,"abstract":"A flipped current mirror and a flipped voltage follower suited to low-voltage and low power operation is applied to the design of current conveyors (CCII). A new topology (class-A )is proposed operating at 1.5v and featuring simplicity, compactness, low power consumption and bandwidths up to 100 MHz for a 0.5μm CMOS technology.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122999400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Software maintenance is a complex and life long process due to unstructured code, team morale, poor visibility of the project, lack of communication techniques and lack of proper test suite. On the other hand extreme programming is an existing process of software development with its challenges practices. In this paper, we propose an iterative maintenance life cycle using extreme programming practices. It would be able to resolve software maintenance issues in the smooth manner. The proposed approach speedsup maintenance process with less effort and produces a more maintainable code for future maintenance and evolution.
{"title":"Iterative Maintenance Life Cycle Using eXtreme Programming","authors":"J. Choudhari, U. Suman","doi":"10.1109/ARTCOM.2010.52","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.52","url":null,"abstract":"Software maintenance is a complex and life long process due to unstructured code, team morale, poor visibility of the project, lack of communication techniques and lack of proper test suite. On the other hand extreme programming is an existing process of software development with its challenges practices. In this paper, we propose an iterative maintenance life cycle using extreme programming practices. It would be able to resolve software maintenance issues in the smooth manner. The proposed approach speedsup maintenance process with less effort and produces a more maintainable code for future maintenance and evolution.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115540755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Ravishankar, K. R. U. Rani, M. Bharathi, H. Mahesh
The possibility of DSL over power lines has received considerable attention recently to cater to broadband distribution within the premises of a home and in the local area served by a substation. The power line has a very different gauge and topology compared to traditional twisted pair copper used for telephone lines. This paper addresses the dual issues of modelling typical power line channels and analyzes the resultant channel for Multicarrier Transmission. The basic approach to analyze the channel employs ABCD parameters for the individual sections. A bit loading analysis for power line channels over the considered DSL bandwidth of 30 MHz has been presented assuming the Transmit power spectral densities as for ADSL and VDSL2 used in telephone lines. An analysis points to the fact that lower Transmit PSDs would suffice to match the traditional rates achievable over traditional twisted pair copper.
{"title":"Analysis of Power Line Networks for Broadband Transmission","authors":"S. Ravishankar, K. R. U. Rani, M. Bharathi, H. Mahesh","doi":"10.1109/ARTCOM.2010.95","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.95","url":null,"abstract":"The possibility of DSL over power lines has received considerable attention recently to cater to broadband distribution within the premises of a home and in the local area served by a substation. The power line has a very different gauge and topology compared to traditional twisted pair copper used for telephone lines. This paper addresses the dual issues of modelling typical power line channels and analyzes the resultant channel for Multicarrier Transmission. The basic approach to analyze the channel employs ABCD parameters for the individual sections. A bit loading analysis for power line channels over the considered DSL bandwidth of 30 MHz has been presented assuming the Transmit power spectral densities as for ADSL and VDSL2 used in telephone lines. An analysis points to the fact that lower Transmit PSDs would suffice to match the traditional rates achievable over traditional twisted pair copper.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128667620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anika Saxena, Praveen Kumar, Kavita Sharma, B. Kaushik
A method is proposed here for development of a new tool which provides fast and efficient way for fault diagnoses in analog CMOS circuits arises due to glitches. The tool follows SBT (simulation before testing) based approach for tests the CMOS analog circuits against faults arises due to glitches. SBT system for fault diagnosis requires some form of a fault dictionary to which the test data is compared. The designed tool generates a fault dictionary which is used in SBT method with distinct pretest and post-test analysis stages. Pretest analysis generates a fault directory. For this the circuit is simulated circuit under all fault combinations, as well as the fault-free case. We can then compute observable variables (voltages or currents), of them, for each combination and store them in an entry of the fault directory.
{"title":"Algorithm Design for Generation of Fault Dictionary in Analog VLSI Circuits","authors":"Anika Saxena, Praveen Kumar, Kavita Sharma, B. Kaushik","doi":"10.1109/ARTCOM.2010.107","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.107","url":null,"abstract":"A method is proposed here for development of a new tool which provides fast and efficient way for fault diagnoses in analog CMOS circuits arises due to glitches. The tool follows SBT (simulation before testing) based approach for tests the CMOS analog circuits against faults arises due to glitches. SBT system for fault diagnosis requires some form of a fault dictionary to which the test data is compared. The designed tool generates a fault dictionary which is used in SBT method with distinct pretest and post-test analysis stages. Pretest analysis generates a fault directory. For this the circuit is simulated circuit under all fault combinations, as well as the fault-free case. We can then compute observable variables (voltages or currents), of them, for each combination and store them in an entry of the fault directory.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129884765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Optimization of power and speed is a very important issue in low-voltage and low-power applications. In this paper, a 1-bit full adder cell has been successfully analyzed by assigning high-threshold voltage to some transistors and low-threshold voltage to others. Moreover, a robust full adder circuit using dual threshold voltage MOSFETs (DT-MOS) has been proposed. The proposed design features lower power dissipation (by 0.11%), higher computing speed (by 4.23%) and lower energy (power delay product) (by 4.33%). The proposed design also offers 4.2% improvement in delay variability and 3.7% improvement in PDP variability at the expense of 2.5% reduction in power variability against process, voltage, and temperature (PVT) variation. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).
在低压低功耗应用中，功率和速度的优化是一个非常重要的问题。本文成功地分析了一个1位全加法器单元，方法是给一些晶体管分配高阈值电压，给另一些晶体管分配低阈值电压。此外，还提出了一种采用双阈值电压mosfet (DT-MOS)的鲁棒全加法器电路。该设计具有低功耗(0.11%)，高计算速度(4.23%)和低能量(功率延迟积)(4.33%)的特点。提出的设计还提供了4.2%的延迟可变性改进和3.7%的PDP可变性改进，其代价是过程、电压和温度(PVT)变化的功率可变性降低2.5%。在HSPICE电路模拟器上进行了大量的仿真，对其功率、速度和能量进行了评估。仿真结果基于32nm Berkeley Predictive Technology Model (BPTM)。
{"title":"Design and Analysis of Robust Dual Threshold CMOS Full Adder Circuit in 32nm Technology","authors":"A. Islam, M. W. Akram, S. Pable, M. Hasan","doi":"10.1109/ARTCOM.2010.20","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.20","url":null,"abstract":"Optimization of power and speed is a very important issue in low-voltage and low-power applications. In this paper, a 1-bit full adder cell has been successfully analyzed by assigning high-threshold voltage to some transistors and low-threshold voltage to others. Moreover, a robust full adder circuit using dual threshold voltage MOSFETs (DT-MOS) has been proposed. The proposed design features lower power dissipation (by 0.11%), higher computing speed (by 4.23%) and lower energy (power delay product) (by 4.33%). The proposed design also offers 4.2% improvement in delay variability and 3.7% improvement in PDP variability at the expense of 2.5% reduction in power variability against process, voltage, and temperature (PVT) variation. The power, speed and energy evaluation has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 32nm Berkeley Predictive Technology Model (BPTM).","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125273862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Chanda, P. Sil, R. Mitra, A. Dandapat, H. Rahaman
In recent years, a plethora of adiabatic logic styles have been published in literature for ultra low power application, but only very few investigate and compare the performances of these adiabatic logic styles. This paper compares and analyzes the performance of transistor based imperative adiabatic logic styles, using 4-2 compressor circuit as a reference. Significant differences in area occupation, energy consumption, operating frequencies are found among the various logic styles. All the simulations are carried out by CADENCE spice spectra in 0.18μm CMOS technology.
{"title":"Comparative Analysis of Adiabatic Compressor Circuits for Ultra-low Power DSP Application","authors":"M. Chanda, P. Sil, R. Mitra, A. Dandapat, H. Rahaman","doi":"10.1109/ARTCOM.2010.78","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.78","url":null,"abstract":"In recent years, a plethora of adiabatic logic styles have been published in literature for ultra low power application, but only very few investigate and compare the performances of these adiabatic logic styles. This paper compares and analyzes the performance of transistor based imperative adiabatic logic styles, using 4-2 compressor circuit as a reference. Significant differences in area occupation, energy consumption, operating frequencies are found among the various logic styles. All the simulations are carried out by CADENCE spice spectra in 0.18μm CMOS technology.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128356947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In a vehicle license plate identification system, locating the license plate in the image or video of a vehicle is an important step before final recognition. In the proposed method care has been taken up to extract license plate of motorcycle (size of plate is small and double row plate), car (single as well as double row type), transport vehicle such as bus, truck, dirty plates as well as multiple license plates present in an image frame under consideration. This paper presents a multiple license plate detection algorithm based on mathematical morphology and component filtering. The proposed algorithm consists of three main stages. The three stages involve pre-processing followed by morphological operations and connected component analysis. The algorithm is able to detect single as well as multiple license plates accurately. The algorithm is tested on set of 750 samples containing the vehicle images from India as well as other countries. The success rate is 98.8% for single license plate extraction and 95% for multiple extraction case.
{"title":"Multiple License Plate Extraction Based on Mathematical Morphology and Component Filtering in Indian Traffic Conditions","authors":"C. Paunwala, S. Patnaik, Manoj D. Chaudhary","doi":"10.1109/ARTCOM.2010.30","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.30","url":null,"abstract":"In a vehicle license plate identification system, locating the license plate in the image or video of a vehicle is an important step before final recognition. In the proposed method care has been taken up to extract license plate of motorcycle (size of plate is small and double row plate), car (single as well as double row type), transport vehicle such as bus, truck, dirty plates as well as multiple license plates present in an image frame under consideration. This paper presents a multiple license plate detection algorithm based on mathematical morphology and component filtering. The proposed algorithm consists of three main stages. The three stages involve pre-processing followed by morphological operations and connected component analysis. The algorithm is able to detect single as well as multiple license plates accurately. The algorithm is tested on set of 750 samples containing the vehicle images from India as well as other countries. The success rate is 98.8% for single license plate extraction and 95% for multiple extraction case.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128380448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
COordinate Rotation DIgital Computer (CORDIC) algorithm has become widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. In this paper, we have represented the design of pipelined architecture for the computation of Sine and Cosine values based on application specific CORDIC processor. The design of CORDIC in the circular rotation mode gives a high system throughput due to its pipelined architecture by reducing latency in each individual pipelined stage. Saving area on silicon substrate is essential to the design of pipelined CORDIC and that can be achieved through the optimization in the number of micro rotations. The computed quantization error is also minimized using required number of iterations. The pipelined architecture can be easily integrated in VLSI technology due to its regularity and modularity.
{"title":"VLSI Architecture Design and Implementation for Application Specific CORDIC Processor","authors":"A. Mandal, K. Tyagi, B. Kaushik","doi":"10.1109/ARTCOM.2010.94","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.94","url":null,"abstract":"COordinate Rotation DIgital Computer (CORDIC) algorithm has become widely researched topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. In this paper, we have represented the design of pipelined architecture for the computation of Sine and Cosine values based on application specific CORDIC processor. The design of CORDIC in the circular rotation mode gives a high system throughput due to its pipelined architecture by reducing latency in each individual pipelined stage. Saving area on silicon substrate is essential to the design of pipelined CORDIC and that can be achieved through the optimization in the number of micro rotations. The computed quantization error is also minimized using required number of iterations. The pipelined architecture can be easily integrated in VLSI technology due to its regularity and modularity.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116211457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Amudhavel, T. Vengattaraman, M. S. Basha, P. Dhavachelvan
Recent distributed computing technologies are primarily oriented towards availability and reliability in the versatile environments. For data availability, replication is widely used in distributed environments to reduce the access cost and improve the overall performance. This paper addresses the one of the main issues in maintaining consistency in replica management particularly; effective local consistency management using optimized Distributed Spanning Tree models. The proposed approach leads to maintain the effective local consistency in the Ad Hoc Networks. This paper evaluates the efficiency of existing techniques along with the proposed approach in the view of promoting the proposed model and the promising results support the same.
{"title":"Effective Maintenance of Replica in Distributed Network Environment Using DST","authors":"J. Amudhavel, T. Vengattaraman, M. S. Basha, P. Dhavachelvan","doi":"10.1109/ARTCOM.2010.97","DOIUrl":"https://doi.org/10.1109/ARTCOM.2010.97","url":null,"abstract":"Recent distributed computing technologies are primarily oriented towards availability and reliability in the versatile environments. For data availability, replication is widely used in distributed environments to reduce the access cost and improve the overall performance. This paper addresses the one of the main issues in maintaining consistency in replica management particularly; effective local consistency management using optimized Distributed Spanning Tree models. The proposed approach leads to maintain the effective local consistency in the Ad Hoc Networks. This paper evaluates the efficiency of existing techniques along with the proposed approach in the view of promoting the proposed model and the promising results support the same.","PeriodicalId":398854,"journal":{"name":"2010 International Conference on Advances in Recent Technologies in Communication and Computing","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126782225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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