Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651743
H. E. Badawi, F. Azaïs, S. Bernard, M. Comte, V. Kerzérho, F. Lefèvre
This paper deals with the general domain of IC reliability and targets more specifically RF circuit. It investigates the feasibility of implementing on-line RF performance monitoring based on the indirect test strategy. The principle of the proposed solution is introduced and the essential requirements needed to adapt the indirect test strategy are discussed. The proposed solution is then applied to a wireless microcontroller with the objective to monitor the power level delivered by the RF transmitter. Hardware measurement results are presented, which demonstrate the potential of this approach and establish a proof-of-concept.
{"title":"Exploring on-line RF performance monitoring based on the indirect test strategy","authors":"H. E. Badawi, F. Azaïs, S. Bernard, M. Comte, V. Kerzérho, F. Lefèvre","doi":"10.1109/LATS53581.2021.9651743","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651743","url":null,"abstract":"This paper deals with the general domain of IC reliability and targets more specifically RF circuit. It investigates the feasibility of implementing on-line RF performance monitoring based on the indirect test strategy. The principle of the proposed solution is introduced and the essential requirements needed to adapt the indirect test strategy are discussed. The proposed solution is then applied to a wireless microcontroller with the objective to monitor the power level delivered by the RF transmitter. Hardware measurement results are presented, which demonstrate the potential of this approach and establish a proof-of-concept.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114604445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651877
I. Kabin, Z. Dyka, D. Klann, P. Langendoerfer
In this work we discuss the resistance of our hardware accelerator for Elliptic Curve Cryptography against simple side-channel analysis (SCA) attacks. We implemented an elliptic curve point multiplication $kP$ corresponding to the atomicity principle that is a well-known countermeasure against simple SCA attacks. We evaluated the resistance of our design by analysing a single simulated power trace of a $kP$ execution. 552 out of 32700 extracted key candidates were identical to the scalar $k$ used in the $kP$ execution, i.e. we were able to reveal the scalar $k$ completely. The reason of the success of our attack is the key-dependent addressing of blocks/registers in the implemented $kP$ algorithm. This means that applying of atomic patterns as effective countermeasures against simple SCA has to be revised, at least for hardware implementations.
{"title":"EC Scalar Multiplication: Successful Simple Address-Bit SCA Attack against Atomic Patterns","authors":"I. Kabin, Z. Dyka, D. Klann, P. Langendoerfer","doi":"10.1109/LATS53581.2021.9651877","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651877","url":null,"abstract":"In this work we discuss the resistance of our hardware accelerator for Elliptic Curve Cryptography against simple side-channel analysis (SCA) attacks. We implemented an elliptic curve point multiplication $kP$ corresponding to the atomicity principle that is a well-known countermeasure against simple SCA attacks. We evaluated the resistance of our design by analysing a single simulated power trace of a $kP$ execution. 552 out of 32700 extracted key candidates were identical to the scalar $k$ used in the $kP$ execution, i.e. we were able to reveal the scalar $k$ completely. The reason of the success of our attack is the key-dependent addressing of blocks/registers in the implemented $kP$ algorithm. This means that applying of atomic patterns as effective countermeasures against simple SCA has to be revised, at least for hardware implementations.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128334948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651736
T. Balen, Carlos J. González, Ingrid F. V. Oliveira, R. Schvittz, N. Added, E. Macchione, V. Aguiar, M. Guazzelli, Nilberto H. Medina, P. Butzen
This work presents a study on the reliability of voters for approximate fault tolerant systems in the context of single event effects. A first case study analyses different topologies of single-bit majority voters for logic circuits by means of fault injection by simulation. In these simulations a previous analysis is performed identifying the critical diffusion areas of the physical implementation according to the voter input vector. Additionally, as second case study, practical heavy ion experiments on different architectures of software-based approximate voters for mixed-signal applications are also presented, and the cross section of each voter is evaluated. The system comprising the voter was irradiated in two distinct experiments with an 16O ion beam, producing an effective $LET$ at the active region of 5.5 MeV/mg/cm2. Results of both case-studies allow identifying the most tolerant voter architectures (among the studied ones) for approximate computing applications under single event effects.
{"title":"Reliability Evaluation of Voters for Fault Tolerant Approximate Systems","authors":"T. Balen, Carlos J. González, Ingrid F. V. Oliveira, R. Schvittz, N. Added, E. Macchione, V. Aguiar, M. Guazzelli, Nilberto H. Medina, P. Butzen","doi":"10.1109/LATS53581.2021.9651736","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651736","url":null,"abstract":"This work presents a study on the reliability of voters for approximate fault tolerant systems in the context of single event effects. A first case study analyses different topologies of single-bit majority voters for logic circuits by means of fault injection by simulation. In these simulations a previous analysis is performed identifying the critical diffusion areas of the physical implementation according to the voter input vector. Additionally, as second case study, practical heavy ion experiments on different architectures of software-based approximate voters for mixed-signal applications are also presented, and the cross section of each voter is evaluated. The system comprising the voter was irradiated in two distinct experiments with an 16O ion beam, producing an effective $LET$ at the active region of 5.5 MeV/mg/cm2. Results of both case-studies allow identifying the most tolerant voter architectures (among the studied ones) for approximate computing applications under single event effects.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125143960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651813
G. Rodrigues, F. Kastensmidt, A. Bosio
This work presents an overview of approximate computing and how it can be applied to safety-critical systems. Approximation has emerged as a strategy to provide execution performance and save computational resources at the cost of precision reduction. When applied to safety-critical applications, it can also improve their robustness, but it conflicts with their requirements (such as high precision and predictability). We discuss those issues and possibilities and how to handle them.
{"title":"Approximate Computing for Safety-Critical Applications","authors":"G. Rodrigues, F. Kastensmidt, A. Bosio","doi":"10.1109/LATS53581.2021.9651813","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651813","url":null,"abstract":"This work presents an overview of approximate computing and how it can be applied to safety-critical systems. Approximation has emerged as a strategy to provide execution performance and save computational resources at the cost of precision reduction. When applied to safety-critical applications, it can also improve their robustness, but it conflicts with their requirements (such as high precision and predictability). We discuss those issues and possibilities and how to handle them.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651798
Bernardo Borges Sandoval, L. H. Brendler, A. Zimpeck, F. Kastensmidt, Ricardo Reis, C. Meinhardt
Radiation effects still present a challenge even with the increased robustness of the multigate devices. The higher density of devices in a small area and the reduction on the node capacitance of the trend technologies keep the radiation robustness evaluation a key parameter on the circuit design, mainly targeting aerospace applications. These applications may also demand power-efficient design. Thus, it is relevant to consider the circuit behavior at different voltage levels of operation. This work provides an analysis of radiation effects on variations of a circuit-level benchmark in 7 nm FinFET device technology, intending to evaluate how the gate mapping affects the circuit susceptibility to radiation faults. Five different circuits were analyzed on supply voltages ranging from 0.7 V to 0.4 V. The LETth for all five circuits and their radiation robustness ranking were determined. The operation of the circuits below 0.5V introduces over 75% more sensitivity on the evaluated circuits. The results show that exploring gate mapping can be adopted to improve robustness. Adopting the NAND2 gate instead of NOR2 gate in the output improves the output robustness by about 38.6%. Moreover, exploring the transistor sizing only in the most sensitive gates can improve the robustness over to 69%.
{"title":"Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study","authors":"Bernardo Borges Sandoval, L. H. Brendler, A. Zimpeck, F. Kastensmidt, Ricardo Reis, C. Meinhardt","doi":"10.1109/LATS53581.2021.9651798","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651798","url":null,"abstract":"Radiation effects still present a challenge even with the increased robustness of the multigate devices. The higher density of devices in a small area and the reduction on the node capacitance of the trend technologies keep the radiation robustness evaluation a key parameter on the circuit design, mainly targeting aerospace applications. These applications may also demand power-efficient design. Thus, it is relevant to consider the circuit behavior at different voltage levels of operation. This work provides an analysis of radiation effects on variations of a circuit-level benchmark in 7 nm FinFET device technology, intending to evaluate how the gate mapping affects the circuit susceptibility to radiation faults. Five different circuits were analyzed on supply voltages ranging from 0.7 V to 0.4 V. The LETth for all five circuits and their radiation robustness ranking were determined. The operation of the circuits below 0.5V introduces over 75% more sensitivity on the evaluated circuits. The results show that exploring gate mapping can be adopted to improve robustness. Adopting the NAND2 gate instead of NOR2 gate in the output improves the output robustness by about 38.6%. Moreover, exploring the transistor sizing only in the most sensitive gates can improve the robustness over to 69%.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124123352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651874
Alexander Aponte-Moreno, Felipe Restrepo-Calle, C. Pedraza
Fault injection tools are commonly used in the early evaluation of microprocessor-based systems. These tools are based on introducing faults into a system to evaluate its behavior, making them of great interest to academia and industry. They are widely used to validate the reliability of mission-critical systems and the effectiveness of fault tolerance techniques. In this paper, we present UN-FIT, an open-source fault injection tool adaptable to different architectures. UN-FIT simulates the target architecture using QEMU, which allows code debugging via GDB. In this way, we can modify the content of registers by simulating bit-flips. We validated the functionality and applicability of this tool by carrying out fault injection campaigns for ARM and RISC-V microprocessors using four test programs. The main contribution of this work is the introduction of an open-source fault injection tool, UN-FIT, for ARM and RISC-V processor architectures, which can be adapted to other architectures or customized according to the user's needs.
{"title":"Reliability Evaluation of RISC-V and ARM Microprocessors Through a New Fault Injection Tool","authors":"Alexander Aponte-Moreno, Felipe Restrepo-Calle, C. Pedraza","doi":"10.1109/LATS53581.2021.9651874","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651874","url":null,"abstract":"Fault injection tools are commonly used in the early evaluation of microprocessor-based systems. These tools are based on introducing faults into a system to evaluate its behavior, making them of great interest to academia and industry. They are widely used to validate the reliability of mission-critical systems and the effectiveness of fault tolerance techniques. In this paper, we present UN-FIT, an open-source fault injection tool adaptable to different architectures. UN-FIT simulates the target architecture using QEMU, which allows code debugging via GDB. In this way, we can modify the content of registers by simulating bit-flips. We validated the functionality and applicability of this tool by carrying out fault injection campaigns for ARM and RISC-V microprocessors using four test programs. The main contribution of this work is the introduction of an open-source fault injection tool, UN-FIT, for ARM and RISC-V processor architectures, which can be adapted to other architectures or customized according to the user's needs.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130974396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651839
S. Carbonetto, Luciano Genovese, L. S. Salomone, M. G. Inza, E. Redin, A. Faigón
The design and characterization of an ionizing radiation sensor for radiotherapy applications based on floating gate structures are presented. The devices were fabricated in a commercial CMOS process, and the floating gate was extended over field oxide in order to improve the radiation sensitivity. Such devices are a useful tool for studying the total dose effects on floating gate structures. The sensor is provided with an injection electrode in order to manipulate the charge stored in the floating gate, allowing not only to set different charge conditions for a complete characterization, but also to restore the floating gate to a desired state after the charge was neutralized by radiation. The devices response to ionizing radiation was studied, showing that sensitivity increases as more charge is stored in the floating gate. The experimental results help to improve the modeling of total ionizing dose effects on floating gate structures and predict their degradation. Preliminary results show that the charge manipulation was successful in several samples, and also experimental results show good agreement with the expected theoretical sensitivity.
{"title":"Total Ionizing Dose Effects on Floating Gate Structures. Preliminary Results.","authors":"S. Carbonetto, Luciano Genovese, L. S. Salomone, M. G. Inza, E. Redin, A. Faigón","doi":"10.1109/LATS53581.2021.9651839","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651839","url":null,"abstract":"The design and characterization of an ionizing radiation sensor for radiotherapy applications based on floating gate structures are presented. The devices were fabricated in a commercial CMOS process, and the floating gate was extended over field oxide in order to improve the radiation sensitivity. Such devices are a useful tool for studying the total dose effects on floating gate structures. The sensor is provided with an injection electrode in order to manipulate the charge stored in the floating gate, allowing not only to set different charge conditions for a complete characterization, but also to restore the floating gate to a desired state after the charge was neutralized by radiation. The devices response to ionizing radiation was studied, showing that sensitivity increases as more charge is stored in the floating gate. The experimental results help to improve the modeling of total ionizing dose effects on floating gate structures and predict their degradation. Preliminary results show that the charge manipulation was successful in several samples, and also experimental results show good agreement with the expected theoretical sensitivity.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125283334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651770
Jakub Lojda, R. Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Z. Kotásek
The growing chip-level integration results in a higher susceptibility to faults of today components. This also relates to commonly used storage memories. A charged particle causes bit flip and a program stored in such memory starts to behave differently from it was supposed to. Even worse, such bit flips can be induced also on purpose to tamper with a device. While the so-called smart devices are becoming still more popular these days, such failure or even tampering of them is very undesired. A smart electronic lock can serve as an example. This is why in this paper, we evaluate the consequences of such program corruption. We target smart lock operation on several computer architectures and show the results on our case study observing the change of the lock behavior. We present our Evaluation Environment that is able to connect with single-board computers and evaluation kits to test the SW behavior on them, which is done under the presence of faults in the tested SW. Our results indicate that the most sensitive part of a program is generally the loading of shared libraries. Problem in this process results in inability to load the program. Segmentation Fault and early termination of the program (e.g. problem in the logic of motor cycle counting) is also serious. The least problematic, according to our observations, is the syntactic error in the output data. In such cases, the motor driver ignores corrupted commands and the motor move is not smooth. Certain findings from the experimental part of this paper, can be generalized to other devices as well.
{"title":"Testing Embedded Software Through Fault Injection: Case Study on Smart Lock","authors":"Jakub Lojda, R. Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Z. Kotásek","doi":"10.1109/LATS53581.2021.9651770","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651770","url":null,"abstract":"The growing chip-level integration results in a higher susceptibility to faults of today components. This also relates to commonly used storage memories. A charged particle causes bit flip and a program stored in such memory starts to behave differently from it was supposed to. Even worse, such bit flips can be induced also on purpose to tamper with a device. While the so-called smart devices are becoming still more popular these days, such failure or even tampering of them is very undesired. A smart electronic lock can serve as an example. This is why in this paper, we evaluate the consequences of such program corruption. We target smart lock operation on several computer architectures and show the results on our case study observing the change of the lock behavior. We present our Evaluation Environment that is able to connect with single-board computers and evaluation kits to test the SW behavior on them, which is done under the presence of faults in the tested SW. Our results indicate that the most sensitive part of a program is generally the loading of shared libraries. Problem in this process results in inability to load the program. Segmentation Fault and early termination of the program (e.g. problem in the logic of motor cycle counting) is also serious. The least problematic, according to our observations, is the syntactic error in the output data. In such cases, the motor driver ignores corrupted commands and the motor move is not smooth. Certain findings from the experimental part of this paper, can be generalized to other devices as well.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121720878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651868
T. Melis, E. Simeu, E. Auvray, L. Saury
Good testability and robust fault diagnosis solutions are extremely important factors for an electronic circuit. However, these goals are difficult to achieve in analog circuits. It is even a more complex problem when such circuits are used in safety domains like automotive. In this work, an active exploitation of the light emission from silicon devices is proposed. This constitutes a new fault diagnosis method. In particular, how to characterize the light emission from the basic principles and mechanisms is presented. Then the description of how it is used as a parameter in automatic fault simulators is given. The results of this paper prove the benefits of such methods in fault diagnosis and testability of the analog circuits.
{"title":"Improved Fault Diagnosis of Analog Circuits using Light Emission Measures","authors":"T. Melis, E. Simeu, E. Auvray, L. Saury","doi":"10.1109/LATS53581.2021.9651868","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651868","url":null,"abstract":"Good testability and robust fault diagnosis solutions are extremely important factors for an electronic circuit. However, these goals are difficult to achieve in analog circuits. It is even a more complex problem when such circuits are used in safety domains like automotive. In this work, an active exploitation of the light emission from silicon devices is proposed. This constitutes a new fault diagnosis method. In particular, how to characterize the light emission from the basic principles and mechanisms is presented. Then the description of how it is used as a parameter in automatic fault simulators is given. The results of this paper prove the benefits of such methods in fault diagnosis and testability of the analog circuits.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115717585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651819
Tobias Faller, P. Scholl, Tobias Paxian, B. Becker
The increasing amount and diversity of System-On-a-Chip (SoC) devices with short development times pose numerous challenges. The RISC-V initiative targets this market with a free and open ISA that supports custom instruction set extensions and accelerators to adapt to application specific scenarios and meet varying constraints w.r.t. efficiency, security, safety and computational power. In this context we target an appropriate test strategy to find manufacturing defects during production, and moreover, to detect degradation in the field. An essential part of this strategy will be so-called Software-Based Self-Tests (SBST). Manually developing SBST programs is a tedious and time-consuming task that requires the expertise of a skilled engineer with detailed knowledge about the specific architecture of the processor at hand. In contrast we present a staggered SBST approach for the automatic creation of SBST programs for RISC-V architectures with the help of SAT-based test pattern generation. First experimental results to demonstrate the feasibility of our approach are provided by test generation results for two exemplary RISC-V processor, each in two variants.
{"title":"Towards SAT-Based SBST Generation for RISC-V Cores","authors":"Tobias Faller, P. Scholl, Tobias Paxian, B. Becker","doi":"10.1109/LATS53581.2021.9651819","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651819","url":null,"abstract":"The increasing amount and diversity of System-On-a-Chip (SoC) devices with short development times pose numerous challenges. The RISC-V initiative targets this market with a free and open ISA that supports custom instruction set extensions and accelerators to adapt to application specific scenarios and meet varying constraints w.r.t. efficiency, security, safety and computational power. In this context we target an appropriate test strategy to find manufacturing defects during production, and moreover, to detect degradation in the field. An essential part of this strategy will be so-called Software-Based Self-Tests (SBST). Manually developing SBST programs is a tedious and time-consuming task that requires the expertise of a skilled engineer with detailed knowledge about the specific architecture of the processor at hand. In contrast we present a staggered SBST approach for the automatic creation of SBST programs for RISC-V architectures with the help of SAT-based test pattern generation. First experimental results to demonstrate the feasibility of our approach are provided by test generation results for two exemplary RISC-V processor, each in two variants.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115853230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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