Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651879
J. Fabero, Golnaz Korkian, F. J. Franco, H. Mecha, M. Letiche, J. A. Clemente
This paper presents an experimental study of the SEU susceptibility against thermal neutron radiation of a 28-nm bulk Commercial-Off-The-Shelf (COTS) SRAM-based FPGA. Experimental results showing Single Event Upsets (SEUs) on configuration RAM (CRAM) cells, Flip-Flops (FFs), and Block RAMs (BRAMs) are provided and discussed. Shapes of multiple events (of various multiplicities) are also analyzed, as well as their dependency with the incident angle of the particle beam against the device's surface.
{"title":"Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles","authors":"J. Fabero, Golnaz Korkian, F. J. Franco, H. Mecha, M. Letiche, J. A. Clemente","doi":"10.1109/LATS53581.2021.9651879","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651879","url":null,"abstract":"This paper presents an experimental study of the SEU susceptibility against thermal neutron radiation of a 28-nm bulk Commercial-Off-The-Shelf (COTS) SRAM-based FPGA. Experimental results showing Single Event Upsets (SEUs) on configuration RAM (CRAM) cells, Flip-Flops (FFs), and Block RAMs (BRAMs) are provided and discussed. Shapes of multiple events (of various multiplicities) are also analyzed, as well as their dependency with the incident angle of the particle beam against the device's surface.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121565618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651857
Zahra Paria Najafi-Haghi, H. Wunderlich
Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield.
{"title":"Resistive Open Defect Classification of Embedded Cells under Variations","authors":"Zahra Paria Najafi-Haghi, H. Wunderlich","doi":"10.1109/LATS53581.2021.9651857","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651857","url":null,"abstract":"Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125666807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651773
F. Pancher, Vanessa Vargas, P. Ramos, R. P. Bastos, David César Ardiles Saravia, R. Velazco
Software fault tolerance techniques can be applied to multi or many-core processors benefitting of the multiplicity of cores. The MPPA Coolidge many-core processor developed by KALRAY (Grenoble, France) was selected in the frame of OVNIPROM1 project as a target for the implementation of the N-Modular Redundancy and M-Partitions (NMR-MPar) fault tolerance technique developed at TIMA. This paper describes the implementation of this technique applied to the MPPA processor for its use as the heart of a nanosatellite On-Board Computer (OBC) to deal with errors produced by radiation effects.
{"title":"Nanosatellite On-Board Computer including a Many-Core Processor","authors":"F. Pancher, Vanessa Vargas, P. Ramos, R. P. Bastos, David César Ardiles Saravia, R. Velazco","doi":"10.1109/LATS53581.2021.9651773","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651773","url":null,"abstract":"Software fault tolerance techniques can be applied to multi or many-core processors benefitting of the multiplicity of cores. The MPPA Coolidge many-core processor developed by KALRAY (Grenoble, France) was selected in the frame of OVNIPROM1 project as a target for the implementation of the N-Modular Redundancy and M-Partitions (NMR-MPar) fault tolerance technique developed at TIMA. This paper describes the implementation of this technique applied to the MPPA processor for its use as the heart of a nanosatellite On-Board Computer (OBC) to deal with errors produced by radiation effects.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115508441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651859
Carlos Bernal, M. Jiménèz, fabio. andrade
This paper proposes an automated setup to reliably characterize the soft switching behavior of commercial GaN HEMTs under pulsed measurements, based on the Transmission Line Pulse (TLP) generator principle. The proposed setup allows for high voltage - high current measurements while keeping the device under test within safe thermal conditions. Additionally, the setup follows the guidelines outlined on the JEDEC JEP173 standard, Dynamic ON-Resistance Test Method Guidelines for GaN HEMT based Power Conversion Devices, guaranteeing reliability and repeatability for a wide range of test conditions. This setup is suitable for characterizing several commercially available GaN HEMT structures such as enhancement and depletion mode devices in cascode or planar p-GaN gate structures. Results showed a non-monotonic behavior on the current collapse phenomenon, for tested planar p-GaN gate HEMT, as drain to source voltage increased. Also, the device ON resistance went significantly down as drain voltage approached to the rated limit.
{"title":"TLP Generator Setup for Reliable Switching Characterization of Commercial GaN HEMTs","authors":"Carlos Bernal, M. Jiménèz, fabio. andrade","doi":"10.1109/LATS53581.2021.9651859","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651859","url":null,"abstract":"This paper proposes an automated setup to reliably characterize the soft switching behavior of commercial GaN HEMTs under pulsed measurements, based on the Transmission Line Pulse (TLP) generator principle. The proposed setup allows for high voltage - high current measurements while keeping the device under test within safe thermal conditions. Additionally, the setup follows the guidelines outlined on the JEDEC JEP173 standard, Dynamic ON-Resistance Test Method Guidelines for GaN HEMT based Power Conversion Devices, guaranteeing reliability and repeatability for a wide range of test conditions. This setup is suitable for characterizing several commercially available GaN HEMT structures such as enhancement and depletion mode devices in cascode or planar p-GaN gate structures. Results showed a non-monotonic behavior on the current collapse phenomenon, for tested planar p-GaN gate HEMT, as drain to source voltage increased. Also, the device ON resistance went significantly down as drain voltage approached to the rated limit.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133306813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-27DOI: 10.1109/LATS53581.2021.9651760
Nunzio Mirabella, M. Grosso, G. Franchino, S. Rinaudo, I. Deretzis, A. Magna, M. Reorda
Low-power SRAM architectures are especially sensitive to many types of defects that may occur during manufacturing. Among these, resistive defects can appear. This paper analyzes some types of such defects that may impair the device functionalities in subtle ways, depending on the defect characteristics, and that may not be directly or easily detectable by traditional test methods, such as March algorithms. We analyze different methods to test such defects and discuss them in terms of complexity and test time.
{"title":"Comparing different solutions for testing resistive defects in low-power SRAMs","authors":"Nunzio Mirabella, M. Grosso, G. Franchino, S. Rinaudo, I. Deretzis, A. Magna, M. Reorda","doi":"10.1109/LATS53581.2021.9651760","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651760","url":null,"abstract":"Low-power SRAM architectures are especially sensitive to many types of defects that may occur during manufacturing. Among these, resistive defects can appear. This paper analyzes some types of such defects that may impair the device functionalities in subtle ways, depending on the defect characteristics, and that may not be directly or easily detectable by traditional test methods, such as March algorithms. We analyze different methods to test such defects and discuss them in terms of complexity and test time.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122293028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-19DOI: 10.1109/LATS53581.2021.9651741
S. Pagliarini
The recent advances in the area of design obfuscation are encouraging, but may present themselves as hard to read for a non-specialist audience. This tutorial uncovers these advances in a clear language, contrasting the approaches that can be implemented at layout level, in the netlist of a circuit, or even at chip level. This tutorial also highlights the available support, both from the tooling side and the logistics of fabricating an obfuscated integrated circuit.
{"title":"A Tutorial on Design Obfuscation: from Transistors to Systems","authors":"S. Pagliarini","doi":"10.1109/LATS53581.2021.9651741","DOIUrl":"https://doi.org/10.1109/LATS53581.2021.9651741","url":null,"abstract":"The recent advances in the area of design obfuscation are encouraging, but may present themselves as hard to read for a non-specialist audience. This tutorial uncovers these advances in a clear language, contrasting the approaches that can be implemented at layout level, in the netlist of a circuit, or even at chip level. This tutorial also highlights the available support, both from the tooling side and the logistics of fabricating an obfuscated integrated circuit.","PeriodicalId":404536,"journal":{"name":"2021 IEEE 22nd Latin American Test Symposium (LATS)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121902748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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