Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896495
Mengmeng Yao, Yao Wang, Zhaolei Wu, J. Liou
A low power trimming-free relaxation oscillator with process and temperature compensation is presented. It adopts a current reference based on transistors working in strong-inversion region and another subthreshold MOSFET current reference to generate the reference voltages for the comparator stage and the charging/discharging current for the oscillator core, respectively. The instability of the time constant RC induced by process and temperature variations are compensated by this scheme. The circuit is designed using TSMC 0.18$mu$m standard CMOS process and simulated with Spectre. Simulations results show that the worst-case variation of the oscillation frequency is ± 4.5% from -20 to 80°C in five different process corners. The power for the proposed oscillator is only 253 nW at 27° C.
{"title":"A low power trimming-free relaxation oscillator with process and temperature compensation","authors":"Mengmeng Yao, Yao Wang, Zhaolei Wu, J. Liou","doi":"10.1109/ISNE.2019.8896495","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896495","url":null,"abstract":"A low power trimming-free relaxation oscillator with process and temperature compensation is presented. It adopts a current reference based on transistors working in strong-inversion region and another subthreshold MOSFET current reference to generate the reference voltages for the comparator stage and the charging/discharging current for the oscillator core, respectively. The instability of the time constant RC induced by process and temperature variations are compensated by this scheme. The circuit is designed using TSMC 0.18$mu$m standard CMOS process and simulated with Spectre. Simulations results show that the worst-case variation of the oscillation frequency is ± 4.5% from -20 to 80°C in five different process corners. The power for the proposed oscillator is only 253 nW at 27° C.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122126937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896617
K. Pey, A. Ranjan, N. Raghavan, S. O’Shea
Hexagonal boron nitride (h-BN) has emerged as one of the promising dielectric materials for the practical realization of graphene nanoelectronics. Although numerous stacks of outperforming 2D material-based transistors have already been demonstrated, very limited insights are available on the reliability aspects of h-BN as a gate dielectric for 2D nanoelectronics. In this work, we review the key similarities and differences in the degradation and breakdown of conventional (SiO2, HfO2) and emerging 2D (h-BN) dielectrics. Some of the key emerging potential applications of h-BN are also highlighted.
{"title":"New Physics of Breakdown in 2D Hexagonal Boron Nitride Dielectrics and Its Potential Applications","authors":"K. Pey, A. Ranjan, N. Raghavan, S. O’Shea","doi":"10.1109/ISNE.2019.8896617","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896617","url":null,"abstract":"Hexagonal boron nitride (h-BN) has emerged as one of the promising dielectric materials for the practical realization of graphene nanoelectronics. Although numerous stacks of outperforming 2D material-based transistors have already been demonstrated, very limited insights are available on the reliability aspects of h-BN as a gate dielectric for 2D nanoelectronics. In this work, we review the key similarities and differences in the degradation and breakdown of conventional (SiO2, HfO2) and emerging 2D (h-BN) dielectrics. Some of the key emerging potential applications of h-BN are also highlighted.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122876061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896462
L. Xu, Baoge Zhang, Donghao Wang
In practical engineering applications, capacitor voltage sorting of Modular Multilevel Converter (MMC) in Power Electronic Transformer (PET) input stage is a huge engineering difficulty. To solve the problems of traditional voltage balancing sorting algorithm, such as high switching frequency, large amount of computation and large switching loss, an optimizing voltage balancing method is proposed to reduce time complexity and switching frequency. Firstly, Merge sort is used to select the appropriate elements as reference values of the randomized-select algorithm, and then the randomized-select algorithm is used for quick sorting. On this basis, the reordering factor is introduced. When the difference of capacitance voltage between sub-modules (SMs) is small, it avoids reordering and keeps trigger pulse unchanged; otherwise, it quickly reorders. Selective sorting of MMC controllers not only further reduces the computational complexity of the controllers, but also effectively reduces switching losses. Finally, the feasibility and validity of the proposed optimization method are verified with MATLAB simulation.
{"title":"Optimizing Voltage Balancing Method of Power Electronic Transformer Based on MMC","authors":"L. Xu, Baoge Zhang, Donghao Wang","doi":"10.1109/ISNE.2019.8896462","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896462","url":null,"abstract":"In practical engineering applications, capacitor voltage sorting of Modular Multilevel Converter (MMC) in Power Electronic Transformer (PET) input stage is a huge engineering difficulty. To solve the problems of traditional voltage balancing sorting algorithm, such as high switching frequency, large amount of computation and large switching loss, an optimizing voltage balancing method is proposed to reduce time complexity and switching frequency. Firstly, Merge sort is used to select the appropriate elements as reference values of the randomized-select algorithm, and then the randomized-select algorithm is used for quick sorting. On this basis, the reordering factor is introduced. When the difference of capacitance voltage between sub-modules (SMs) is small, it avoids reordering and keeps trigger pulse unchanged; otherwise, it quickly reorders. Selective sorting of MMC controllers not only further reduces the computational complexity of the controllers, but also effectively reduces switching losses. Finally, the feasibility and validity of the proposed optimization method are verified with MATLAB simulation.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117109037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896409
YanChun Gu, Fang Wang, Yuhuai Liu
The full width at half maxima (FWHM) of the LDs is very narrow, with small threshold current and high luminous power. Through simulation, it can be seen that the radiation recombination rate and wave intensity of different lateral positions of LDs are different. The waveguide layer of the high Al composition has a lower refractive index and can reduce the divergence angle of light. In this paper, the device structure is optimized by gradually increasing the Al component toward the p-cladding layer and decreasing the Al component toward p-side. Compared with the original structure, the grading wave guide proves that it can have better electrical characteristics and the FWHM is smaller.
{"title":"Structural optimization of 273nm deep ultraviolet laser in wave guide","authors":"YanChun Gu, Fang Wang, Yuhuai Liu","doi":"10.1109/ISNE.2019.8896409","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896409","url":null,"abstract":"The full width at half maxima (FWHM) of the LDs is very narrow, with small threshold current and high luminous power. Through simulation, it can be seen that the radiation recombination rate and wave intensity of different lateral positions of LDs are different. The waveguide layer of the high Al composition has a lower refractive index and can reduce the divergence angle of light. In this paper, the device structure is optimized by gradually increasing the Al component toward the p-cladding layer and decreasing the Al component toward p-side. Compared with the original structure, the grading wave guide proves that it can have better electrical characteristics and the FWHM is smaller.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117142530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896513
Qingge Huo, M. I. Niass, Yuhuai Liu, Fang Wang
A method for improving the performance of deep ultraviolet laser devices by improving the electron blocking layer is proposed. It is applied to deep ultraviolet semiconductor laser diodes through the left tapered electron blocking layer (EBL). Comparison with the right tapered electron blocking layer or the non-tapered electron blocking layer, the laser of left tapered electron blocking layer device exhibits higher efficiency at the time of device, indicating a significant increase in electron transfer and holes, which improves the luminous efficiency of the device.
{"title":"Improve the performance of deep ultraviolet semiconductor lasers by optimizing the electron blocking layer","authors":"Qingge Huo, M. I. Niass, Yuhuai Liu, Fang Wang","doi":"10.1109/ISNE.2019.8896513","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896513","url":null,"abstract":"A method for improving the performance of deep ultraviolet laser devices by improving the electron blocking layer is proposed. It is applied to deep ultraviolet semiconductor laser diodes through the left tapered electron blocking layer (EBL). Comparison with the right tapered electron blocking layer or the non-tapered electron blocking layer, the laser of left tapered electron blocking layer device exhibits higher efficiency at the time of device, indicating a significant increase in electron transfer and holes, which improves the luminous efficiency of the device.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131672837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896496
Siyu Yu, L. Qi, Y. Tie
In order to solve the problem of accurate holographic projection of the point cloud collected by an external high-precision depth camera in HoloLens, we propose an augmented reality calibration algorithm for real-time scene perception. Firstly, we build a portable high-precision real-time sensing system, using external RealSense to collect point cloud data, and the portable host processes and returns the data to HoloLens via a local area network. Secondly, it calibrates the internal parameters of HoloLens' webcam and RealSense depth cameras, then fixed the two cameras for dual purpose calibration, so as to obtain the internal rotation and translation matrix. Finally, the calculated posture computed by the matrix transformation transforms of the virtual object from the RealSense coordinate system displayed in OSG (Open Scene Graph) to HoloLens unified. The Direct X coordinate system is then transformed into the HoloLens Webcam coordinate system, and then the HoloLens API is used to acquire the fixed coordinate system established during the acquisition. At the same time, the virtual object of the holographic projection is accurately merged with the real object, and the spatial anchor is fixed in the real scene, so that the system realizes an accurate and real-time aware augmented reality capability.
为了解决HoloLens中外部高精度深度相机采集的点云的精确全息投影问题，提出了一种用于实时场景感知的增强现实校准算法。首先，我们构建了一个便携式高精度实时传感系统，利用外部RealSense采集点云数据，便携式主机通过局域网处理并返回数据给HoloLens。其次，对HoloLens的网络摄像头和RealSense深度摄像头的内部参数进行标定，并将两个摄像头固定进行双重标定，从而得到内部旋转平移矩阵。最后，通过矩阵变换计算出的计算姿态将虚拟物体从OSG (Open Scene Graph)中显示的RealSense坐标系转换为统一的HoloLens坐标系。然后将Direct X坐标系转换为HoloLens Webcam坐标系，然后使用HoloLens API获取采集过程中建立的固定坐标系。同时，将全息投影的虚拟物体与真实物体精确融合，并将空间锚定在真实场景中，从而使系统实现了精确、实时的感知增强现实能力。
{"title":"A Calibration Algorithm for Real-time Scene-aware Portable Augmented Reality","authors":"Siyu Yu, L. Qi, Y. Tie","doi":"10.1109/ISNE.2019.8896496","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896496","url":null,"abstract":"In order to solve the problem of accurate holographic projection of the point cloud collected by an external high-precision depth camera in HoloLens, we propose an augmented reality calibration algorithm for real-time scene perception. Firstly, we build a portable high-precision real-time sensing system, using external RealSense to collect point cloud data, and the portable host processes and returns the data to HoloLens via a local area network. Secondly, it calibrates the internal parameters of HoloLens' webcam and RealSense depth cameras, then fixed the two cameras for dual purpose calibration, so as to obtain the internal rotation and translation matrix. Finally, the calculated posture computed by the matrix transformation transforms of the virtual object from the RealSense coordinate system displayed in OSG (Open Scene Graph) to HoloLens unified. The Direct X coordinate system is then transformed into the HoloLens Webcam coordinate system, and then the HoloLens API is used to acquire the fixed coordinate system established during the acquisition. At the same time, the virtual object of the holographic projection is accurately merged with the real object, and the spatial anchor is fixed in the real scene, so that the system realizes an accurate and real-time aware augmented reality capability.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133975623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896371
Wenda Zhao, Yanhui Lu, Shou-yi Yang
We propose an algorithm combining distributed recursive Gaussian process (drGP) regression with Message-Digest Algorithm 5 (MD5) Hash algorithm for indoor positioning (MD5-drGP), aiming to increase the rate of positioning process. The proposed algorithm processes the reference points database of positioning based on drGP by MD5, making the length of probability fingerprints becomes shorter and improving the matching rate of positioning. It realizes the optimization of the database. The simulation results show that the MD5-drGP algorithm greatly reduces the positioning time comparing to the conventional standard gaussian process and drGP, so that it develops the positioning efficiency. Meanwhile, the positioning accuracy is not affected.
{"title":"MD5-drGP for RSS Map Applied to Indoor Positioning","authors":"Wenda Zhao, Yanhui Lu, Shou-yi Yang","doi":"10.1109/ISNE.2019.8896371","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896371","url":null,"abstract":"We propose an algorithm combining distributed recursive Gaussian process (drGP) regression with Message-Digest Algorithm 5 (MD5) Hash algorithm for indoor positioning (MD5-drGP), aiming to increase the rate of positioning process. The proposed algorithm processes the reference points database of positioning based on drGP by MD5, making the length of probability fingerprints becomes shorter and improving the matching rate of positioning. It realizes the optimization of the database. The simulation results show that the MD5-drGP algorithm greatly reduces the positioning time comparing to the conventional standard gaussian process and drGP, so that it develops the positioning efficiency. Meanwhile, the positioning accuracy is not affected.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134052150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896420
Zhongqiu Xing, Fang Wang, Yuhuai Liu
The optimal thickness of the electron blocking layer for AlGaN-based deep ultraviolet laser diodes is reported. By comparing the performance of laser diodes with different thicknesses of electron blocking layer such as 4 nm, 5 nm, 6 nm, 10 nm, and 15 nm, it is found that the electron blocking ability is the strongest, when the thickness of the electron blocking layer set as 5 nm, the reason is that the electron concentration in the p-side is the lowest. Moreover, the laser has a threshold current of 20.62 mA, a threshold voltage of 4.54 V, a slope efficiency of 2.09 W/A.
{"title":"Optimization of thickness in electron blocking layer of AlGaN-based deep ultraviolet laser diodes","authors":"Zhongqiu Xing, Fang Wang, Yuhuai Liu","doi":"10.1109/ISNE.2019.8896420","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896420","url":null,"abstract":"The optimal thickness of the electron blocking layer for AlGaN-based deep ultraviolet laser diodes is reported. By comparing the performance of laser diodes with different thicknesses of electron blocking layer such as 4 nm, 5 nm, 6 nm, 10 nm, and 15 nm, it is found that the electron blocking ability is the strongest, when the thickness of the electron blocking layer set as 5 nm, the reason is that the electron concentration in the p-side is the lowest. Moreover, the laser has a threshold current of 20.62 mA, a threshold voltage of 4.54 V, a slope efficiency of 2.09 W/A.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132987670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896437
Chua-Chin Wang, S. Lu
A 2 × VDD output buffer equipped with SR (slew rate) self-adjustment mechanism driven by a PVT (process, voltage, temperature) detector is proposed in this investigation. Notably, the proposed buffer design is realized by 16-nm FinFET CMOS technology, where specical design constraints required by FinFET must be taken into consideration. In other words, design trade-off will be discussed and highlight. To enhance the output SR, awlays-on driving transistors in Output Stage must be realized with low Vth devices to boost the output current. For FinFET devices, The gate drives of these driving transistors must be stablized to prevent any possible noise interference. Nonoverlapping signaling control is directly realized in transistor level instead of conventional gate level designs such that the the speed is fastened. According to the all-PVT-corner simulations, the worst data rate is 2.5/2.5 GHz with 20 pF loading when the supply voltage is 0.8/1.6 V, respectively. The ∆ SR improvement is at least 10%, when the proposed SR self-adjustment mechanism is activated.
{"title":"2.5 GHz Data Rate 2 × VDD Digital Output Buffer Design Realized by 16-nm FinFET CMOS","authors":"Chua-Chin Wang, S. Lu","doi":"10.1109/ISNE.2019.8896437","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896437","url":null,"abstract":"A 2 × VDD output buffer equipped with SR (slew rate) self-adjustment mechanism driven by a PVT (process, voltage, temperature) detector is proposed in this investigation. Notably, the proposed buffer design is realized by 16-nm FinFET CMOS technology, where specical design constraints required by FinFET must be taken into consideration. In other words, design trade-off will be discussed and highlight. To enhance the output SR, awlays-on driving transistors in Output Stage must be realized with low Vth devices to boost the output current. For FinFET devices, The gate drives of these driving transistors must be stablized to prevent any possible noise interference. Nonoverlapping signaling control is directly realized in transistor level instead of conventional gate level designs such that the the speed is fastened. According to the all-PVT-corner simulations, the worst data rate is 2.5/2.5 GHz with 20 pF loading when the supply voltage is 0.8/1.6 V, respectively. The ∆ SR improvement is at least 10%, when the proposed SR self-adjustment mechanism is activated.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"390 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123958827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ISNE.2019.8896649
Xiaoda Liu, Ya Li, Jianning Yao, Bing Chen, Jiayou Song, Xiaonan Yang
Colorectal cancer (CRC) is the third leading cause of cancer-related death in China. It usually originates from the non-cancerous neoplasm polyps of the colon or rectal epithelium. Some polyps will evolve into precancerous lesions and eventually turn into colorectal cancer, Early screening and removal of adenomas can reduce the risk of colorectal cancer if screened. Unfortunately, more than 60% of colorectal cancer cases are attributed to missed polyps. Therefore, a deep learning network referred to as the faster_rcnn_inception_ resnet_v2 model was introduced for the localization and classification of precancerous lesions. It enables high-precision classification of polyps and adenomas under white light endoscopic images. The Mean Average Precision reached 90.645% when the Intersection over Union is set to 0.5. As an aid to clinicians, the model can improve the detection rate of adenomas and the diagnostic accuracy of early CRC.
结直肠癌(CRC)是中国癌症相关死亡的第三大原因。它通常起源于结肠或直肠上皮的非癌性肿瘤息肉。有些息肉会演变为癌前病变，最终演变为结直肠癌，及早筛查和切除腺瘤，如果筛查，可降低患结直肠癌的风险。不幸的是，超过60%的结直肠癌病例是由于漏诊的息肉。因此，我们引入了一种称为faster_rcnn_inception_ resnet_v2模型的深度学习网络，用于癌前病变的定位和分类。它可以在白光内镜图像下对息肉和腺瘤进行高精度分类。当Intersection over Union设置为0.5时，Mean Average Precision达到90.645%。该模型可以帮助临床医生提高腺瘤的检出率和早期结直肠癌的诊断准确率。
{"title":"Classification of Polyps and Adenomas Using Deep Learning Model in Screening Colonoscopy","authors":"Xiaoda Liu, Ya Li, Jianning Yao, Bing Chen, Jiayou Song, Xiaonan Yang","doi":"10.1109/ISNE.2019.8896649","DOIUrl":"https://doi.org/10.1109/ISNE.2019.8896649","url":null,"abstract":"Colorectal cancer (CRC) is the third leading cause of cancer-related death in China. It usually originates from the non-cancerous neoplasm polyps of the colon or rectal epithelium. Some polyps will evolve into precancerous lesions and eventually turn into colorectal cancer, Early screening and removal of adenomas can reduce the risk of colorectal cancer if screened. Unfortunately, more than 60% of colorectal cancer cases are attributed to missed polyps. Therefore, a deep learning network referred to as the faster_rcnn_inception_ resnet_v2 model was introduced for the localization and classification of precancerous lesions. It enables high-precision classification of polyps and adenomas under white light endoscopic images. The Mean Average Precision reached 90.645% when the Intersection over Union is set to 0.5. As an aid to clinicians, the model can improve the detection rate of adenomas and the diagnostic accuracy of early CRC.","PeriodicalId":405565,"journal":{"name":"2019 8th International Symposium on Next Generation Electronics (ISNE)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122749577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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