Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955044
V. Acharya, B. Banerjee
This paper describes a bandgap reference that doesn't use resistors or operational amplifiers. The circuit uses ratioed transistors in strong inversion with the inverse function technique to develop a voltage, proportional to the absolute temperature term of the reference. With the low-output impedance at the output, this reference voltage can drive resistive loads. Unlike its predecessor, this circuit's performance doesn't degrade with variations in supply voltage. The bandgap was designed on a 0.6μm process and the corresponding BSIM3 (V3.2) models are used.
{"title":"A supply insensitive resistor-less bandgap reference with buffered output","authors":"V. Acharya, B. Banerjee","doi":"10.1109/DCAS.2010.5955044","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955044","url":null,"abstract":"This paper describes a bandgap reference that doesn't use resistors or operational amplifiers. The circuit uses ratioed transistors in strong inversion with the inverse function technique to develop a voltage, proportional to the absolute temperature term of the reference. With the low-output impedance at the output, this reference voltage can drive resistive loads. Unlike its predecessor, this circuit's performance doesn't degrade with variations in supply voltage. The bandgap was designed on a 0.6μm process and the corresponding BSIM3 (V3.2) models are used.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117073166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955030
O. Eliezer, B. Staszewski, J. Mehta, F. Jabbar, I. Bashir
A programmable self-characterization technique is presented, whose purpose is to determine the extent of mismatches present in a variable-capacitor (varactor) array as part of an LC tank of a digitally controlled oscillator (DCO). The varactor array represents a digital-to-analog conversion function, such that mismatches in it cause distortion in the DCO's digital frequency tracking and modulation. The presented technique, relying exclusively on internal resources in the system-on-chip (SoC) and on dedicated software, is implemented in a 65nm CMOS Digital RF Processor (DRP) based transceiver, and demonstrates sufficient accuracy to allow relatively quick measurements of mismatches of a few percent.
{"title":"Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator","authors":"O. Eliezer, B. Staszewski, J. Mehta, F. Jabbar, I. Bashir","doi":"10.1109/DCAS.2010.5955030","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955030","url":null,"abstract":"A programmable self-characterization technique is presented, whose purpose is to determine the extent of mismatches present in a variable-capacitor (varactor) array as part of an LC tank of a digitally controlled oscillator (DCO). The varactor array represents a digital-to-analog conversion function, such that mismatches in it cause distortion in the DCO's digital frequency tracking and modulation. The presented technique, relying exclusively on internal resources in the system-on-chip (SoC) and on dedicated software, is implemented in a 65nm CMOS Digital RF Processor (DRP) based transceiver, and demonstrates sufficient accuracy to allow relatively quick measurements of mismatches of a few percent.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122310222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955045
S. Modi, S. Askari, S. Manohar, P. Balsara, M. Nourani
The increasing complexity of analog design for SoCs has become a bottleneck due to the lack of established design automation flows. Consequently, reuse of analog design IP (intellectual property) is becoming increasingly prevalent in the semiconductor industry. Traditional design reuse approaches still require a considerable amount of a designer's time for a new set of specifications or migration to new technology nodes. This paper describes an accelerated design reuse strategy for analog circuit design using design automation techniques. As a case study, we developed an automated GmC filter design flow using a combination of heuristic and stochastic optimization methods. The resultant IP is capable of generating SPICE netlists for wide sets of specifications and different technology nodes with minimal designer effort.
{"title":"Automated GmC filter design: A case study in accelerated reuse of analog circuit design","authors":"S. Modi, S. Askari, S. Manohar, P. Balsara, M. Nourani","doi":"10.1109/DCAS.2010.5955045","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955045","url":null,"abstract":"The increasing complexity of analog design for SoCs has become a bottleneck due to the lack of established design automation flows. Consequently, reuse of analog design IP (intellectual property) is becoming increasingly prevalent in the semiconductor industry. Traditional design reuse approaches still require a considerable amount of a designer's time for a new set of specifications or migration to new technology nodes. This paper describes an accelerated design reuse strategy for analog circuit design using design automation techniques. As a case study, we developed an automated GmC filter design flow using a combination of heuristic and stochastic optimization methods. The resultant IP is capable of generating SPICE netlists for wide sets of specifications and different technology nodes with minimal designer effort.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128979438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955038
S. T. Block, Yiran Li, Yi Yang, Changzhi Li
An All-CMOS temperature sensor front-end is designed to work with a supply voltage range of 0.6 to 2.0 volts, and temperature range from 0 to 120°C. The flexibility of 0.6 to 2.0 volt operation was made possible by the use of a bulk-driven op amp. Using all CMOS allows for low voltage and smaller chip area. UMC 0.13μm technology was used for this design. This sensor produces three outputs, two voltages proportional to absolute temperature (PTAT), and one voltage independent of absolute temperature (IOAT). The temperature sensor front-end produces an approximate average reference voltage of 249mV with variation of ±0.7mV, a temperature coefficient of 18.2ppm/°C at VDD = 0.6V to 19.2ppm/°C at VDD = 2.0V, and a voltage coefficient of 290ppm/V at 0°C to 657ppm/V at 120°C. The design produces two linear PTAT voltages with approximate temperature sensitivity of 0.28mV/°C and 0.84mV/°C (Vtemp0 and Vtemp1 respectively) and voltage coefficients of 113.6ppm/V at 0°C, 450ppm/V at 120°C for Vtemp0 and 501.4ppm/V at 0°C, 1904ppm/V at 120°C for Vtemp1. The design has a simulated PSRR of −54dB at 100Hz and 0°C with a supply voltage of 0.6V.
{"title":"0.6–2.0 V, All-CMOS temperature sensor front-end using bulk-driven technology","authors":"S. T. Block, Yiran Li, Yi Yang, Changzhi Li","doi":"10.1109/DCAS.2010.5955038","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955038","url":null,"abstract":"An All-CMOS temperature sensor front-end is designed to work with a supply voltage range of 0.6 to 2.0 volts, and temperature range from 0 to 120°C. The flexibility of 0.6 to 2.0 volt operation was made possible by the use of a bulk-driven op amp. Using all CMOS allows for low voltage and smaller chip area. UMC 0.13μm technology was used for this design. This sensor produces three outputs, two voltages proportional to absolute temperature (PTAT), and one voltage independent of absolute temperature (IOAT). The temperature sensor front-end produces an approximate average reference voltage of 249mV with variation of ±0.7mV, a temperature coefficient of 18.2ppm/°C at VDD = 0.6V to 19.2ppm/°C at VDD = 2.0V, and a voltage coefficient of 290ppm/V at 0°C to 657ppm/V at 120°C. The design produces two linear PTAT voltages with approximate temperature sensitivity of 0.28mV/°C and 0.84mV/°C (V<inf>temp0</inf> and V<inf>temp1</inf> respectively) and voltage coefficients of 113.6ppm/V at 0°C, 450ppm/V at 120°C for V<inf>temp0</inf> and 501.4ppm/V at 0°C, 1904ppm/V at 120°C for V<inf>temp1</inf>. The design has a simulated PSRR of −54dB at 100Hz and 0°C with a supply voltage of 0.6V.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130547274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955043
P. Srinivasan, A. Marshall
Circuit characterization for low frequency noise of a bandgap reference circuit in a 45nm CMOS process is performed here. It is determined that the noise at lower frequencies follow 1/fγ spectra where 1<γ<2. This flattens off as thermal noise for frequencies greater than 1 KHz. Substantial variation in bandgap noise is observed which is demonstrated to be largely uncorrelated to bandgap trim voltage. Possible noise generating components within the bandgap circuit are identified. The dominant contributor for the observed 1/fγ nature of the bandgap noise is identified as the noise generated within the operational amplifier circuit block.
{"title":"Circuit characterization of low frequency noise in 45nm technology bandgap","authors":"P. Srinivasan, A. Marshall","doi":"10.1109/DCAS.2010.5955043","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955043","url":null,"abstract":"Circuit characterization for low frequency noise of a bandgap reference circuit in a 45nm CMOS process is performed here. It is determined that the noise at lower frequencies follow 1/fγ spectra where 1<γ<2. This flattens off as thermal noise for frequencies greater than 1 KHz. Substantial variation in bandgap noise is observed which is demonstrated to be largely uncorrelated to bandgap trim voltage. Possible noise generating components within the bandgap circuit are identified. The dominant contributor for the observed 1/fγ nature of the bandgap noise is identified as the noise generated within the operational amplifier circuit block.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122988602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955037
R. Oberhuber, R. Prakash
An ultra-small, low power, low dropout (LDO) voltage regulator is presented which tracks the output voltage with threshold voltages of the underlying process technology. The topology of the regulator is extremely simple because it does not use an error amplifier. Instead a common-gate stage feedback loop is used, reducing the number of active transistors to only 10. This results in extremely small chip area as well as very low power consumption. This regulator is suitable for various applications where high precision of the output voltage is not required, such as controlling the interfaces of the various sub-circuits in highly complex system-on chip designs. Moreover, in many applications, the voltage overshoot from the output of the LDO can cause violations of breakdown voltage limitations on transistor terminals in subsequent stages, and thus damages those transistors. Therefore in the second part of this paper, an improved ultra-small regulator circuit will be discussed with reduced output voltage overshoot for sharp input voltage ramps. It also comprises a simple, new level detector circuit which indicates if the regulator is in regulation mode or passive mode.
{"title":"Low overshoot, low dropout voltage regulator with level detector","authors":"R. Oberhuber, R. Prakash","doi":"10.1109/DCAS.2010.5955037","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955037","url":null,"abstract":"An ultra-small, low power, low dropout (LDO) voltage regulator is presented which tracks the output voltage with threshold voltages of the underlying process technology. The topology of the regulator is extremely simple because it does not use an error amplifier. Instead a common-gate stage feedback loop is used, reducing the number of active transistors to only 10. This results in extremely small chip area as well as very low power consumption. This regulator is suitable for various applications where high precision of the output voltage is not required, such as controlling the interfaces of the various sub-circuits in highly complex system-on chip designs. Moreover, in many applications, the voltage overshoot from the output of the LDO can cause violations of breakdown voltage limitations on transistor terminals in subsequent stages, and thus damages those transistors. Therefore in the second part of this paper, an improved ultra-small regulator circuit will be discussed with reduced output voltage overshoot for sharp input voltage ramps. It also comprises a simple, new level detector circuit which indicates if the regulator is in regulation mode or passive mode.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122373370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955039
Liuxi Qian, Dian Zhou, Sheng-Guo Wang, Xuan Zeng
In today's VLSI technology, the process variations are unavoidable. This paper proposes an efficient analysis approach for exploring the worst case performance for VLSI circuits with severe parameter value variations due to nano-scale process. Inspired by Kharitonov's theorem, the described method dramatically reduces the computational burden to only evaluate several critical Kharitonov-type interval transfer functions. The computational efficiency of the method is demonstrated by two practical VLSI circuits.
{"title":"Performance robustness analysis of VLSI circuits with process variations based on Kharitonov's theorem","authors":"Liuxi Qian, Dian Zhou, Sheng-Guo Wang, Xuan Zeng","doi":"10.1109/DCAS.2010.5955039","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955039","url":null,"abstract":"In today's VLSI technology, the process variations are unavoidable. This paper proposes an efficient analysis approach for exploring the worst case performance for VLSI circuits with severe parameter value variations due to nano-scale process. Inspired by Kharitonov's theorem, the described method dramatically reduces the computational burden to only evaluate several critical Kharitonov-type interval transfer functions. The computational efficiency of the method is demonstrated by two practical VLSI circuits.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123258880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/DCAS.2010.5955031
H. Edwards, T. Chatterjee, M. Kassem, G. Gómez, F. Hou, Xiaoju Wu
We report a device physics theory and compact model that predicts the threshold voltage mismatch for CMOS transistors using the halo implant. This model is able to fit CMOS VT mismatch across temperature and device geometry, validating the underlying physical argument. Layout and biasing methods are presented and shown to recover part of the matching degradation due to the halo implant.
{"title":"Device physics origin and solutions to threshold voltage fluctuations in sub 130 nm CMOS incorporating halo implant","authors":"H. Edwards, T. Chatterjee, M. Kassem, G. Gómez, F. Hou, Xiaoju Wu","doi":"10.1109/DCAS.2010.5955031","DOIUrl":"https://doi.org/10.1109/DCAS.2010.5955031","url":null,"abstract":"We report a device physics theory and compact model that predicts the threshold voltage mismatch for CMOS transistors using the halo implant. This model is able to fit CMOS VT mismatch across temperature and device geometry, validating the underlying physical argument. Layout and biasing methods are presented and shown to recover part of the matching degradation due to the halo implant.","PeriodicalId":405694,"journal":{"name":"2010 IEEE Dallas Circuits and Systems Workshop","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129063300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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