Relying on a recently developed gate-level information assurance scheme, we formally analyze the security of design-for-test (DFT) scan chains, the industrial standard testing methods for fabricated chips and, for the first time, formally prove that a circuit with scan chain inserted can violate security properties. The same security assessment method is then applied to a built-in-self-test (BIST) structure where it is shown that even BIST structures can cause security vulnerabilities. To balance trustworthiness and testability, a new design-for-security (DFS) methodology is proposed which, through the modification of scan chain structure, can achieve high security without compromising the testability of the inserted scan structure. To support the task of secure scan chain insertion, a method of scan chain reshuffling is introduced. Using an AES encryption core as the testing platform, we elaborated the security assessment procedure as well as the DFS technique in balancing security and testability of cryptographic circuits.
{"title":"Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits","authors":"Yier Jin","doi":"10.1109/ISVLSI.2014.54","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.54","url":null,"abstract":"Relying on a recently developed gate-level information assurance scheme, we formally analyze the security of design-for-test (DFT) scan chains, the industrial standard testing methods for fabricated chips and, for the first time, formally prove that a circuit with scan chain inserted can violate security properties. The same security assessment method is then applied to a built-in-self-test (BIST) structure where it is shown that even BIST structures can cause security vulnerabilities. To balance trustworthiness and testability, a new design-for-security (DFS) methodology is proposed which, through the modification of scan chain structure, can achieve high security without compromising the testability of the inserted scan structure. To support the task of secure scan chain insertion, a method of scan chain reshuffling is introduced. Using an AES encryption core as the testing platform, we elaborated the security assessment procedure as well as the DFS technique in balancing security and testability of cryptographic circuits.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133821903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hélène Leroux, Karen Godary-Dejean, Guillaume Coppey, D. Andreu
Several solutions for implementing Petri net models on FPGA thanks to a transformation in a VHDL code have been proposed in literature. But none deals with the management of transition conflicts in the specific case of synchronous implementation of interpreted Petri nets. This article presents an automatic method to deal with conflicts from their detection to their implementation on FPGA. One solution for binary Petri nets is proposed. For the generalized case, two solutions are proposed and experimentally compared. Thus a solution is provided for the implementation of interpreted generalized time Petri nets.
{"title":"Automatic Handling of Conflicts in Synchronous Interpreted Time Petri Nets Implementation","authors":"Hélène Leroux, Karen Godary-Dejean, Guillaume Coppey, D. Andreu","doi":"10.1109/ISVLSI.2014.44","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.44","url":null,"abstract":"Several solutions for implementing Petri net models on FPGA thanks to a transformation in a VHDL code have been proposed in literature. But none deals with the management of transition conflicts in the specific case of synchronous implementation of interpreted Petri nets. This article presents an automatic method to deal with conflicts from their detection to their implementation on FPGA. One solution for binary Petri nets is proposed. For the generalized case, two solutions are proposed and experimentally compared. Thus a solution is provided for the implementation of interpreted generalized time Petri nets.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"08 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130638314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents FinCACTI, a cache modeling tool based on CACTI which also supports deeply-scaled FinFET devices as well as more robust SRAM cells. In particular, FinFET devices optimized using advanced device simulators for 7nm process serve as the case study of the paper. Based on this 7nm FinFET process, characteristics of 6T and 8T SRAMs are calculated, and comparison results show that under the same stability requirements the 8T cell has smaller area and leakage power. SRAM and technological parameters of the 7nm FinFET are then incorporated into FinCACTI. According to architecture-level simulations, the 8T SRAM is suggested as the choice of memory cell for 7nm FinFET. Moreover, a 4MB cache in 7nm FinFET compared with 22nm (32nm) CMOS under same access latencies achieves 5x (9x) and 11x (24x) reduction in read energy and area, respectively.
{"title":"FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET Devices","authors":"A. Shafaei, Yanzhi Wang, X. Lin, Massoud Pedram","doi":"10.1109/ISVLSI.2014.94","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.94","url":null,"abstract":"This paper presents FinCACTI, a cache modeling tool based on CACTI which also supports deeply-scaled FinFET devices as well as more robust SRAM cells. In particular, FinFET devices optimized using advanced device simulators for 7nm process serve as the case study of the paper. Based on this 7nm FinFET process, characteristics of 6T and 8T SRAMs are calculated, and comparison results show that under the same stability requirements the 8T cell has smaller area and leakage power. SRAM and technological parameters of the 7nm FinFET are then incorporated into FinCACTI. According to architecture-level simulations, the 8T SRAM is suggested as the choice of memory cell for 7nm FinFET. Moreover, a 4MB cache in 7nm FinFET compared with 22nm (32nm) CMOS under same access latencies achieves 5x (9x) and 11x (24x) reduction in read energy and area, respectively.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132871929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a transistor sizing tool to optimize performance taking into account area and power consumption in MOSFET and FinFET devices. The sizing tool is based on Geometric Programming (GP). This tool is modeled to deal with the discrete behavior of FinFET transistor sizing due to the width quantization of these devices. ISCAS'85 benchmark circuits were mapped to a typical standard cell library in 45nm bulk CMOS technology. The size characteristics of this library were adapted to build a predictive 14nm FinFET cell library. Considering transistor sizes generally used in a standard cell library, our transistor sizing improves the delay of MOSFET circuits in 52.5%, on average, keeping almost the same area and power than the sizing provided by the standard-cell library. Good results are achieved considering two simple techniques to adjust continuous to discrete sizing for FinFET circuits: rounding and truncation. These simple sizing strategies produce FinFET circuits 77% faster, on average, keeping the same area and power. Further, results show that the performance can be significantly improved if is considered a Performance Dedicated Cell Library with more cells sizes than the adopted in traditional cell libraries.
{"title":"Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices","authors":"G. Posser, Jozeanne Belomo, C. Meinhardt, R. Reis","doi":"10.1109/ISVLSI.2014.13","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.13","url":null,"abstract":"This work presents a transistor sizing tool to optimize performance taking into account area and power consumption in MOSFET and FinFET devices. The sizing tool is based on Geometric Programming (GP). This tool is modeled to deal with the discrete behavior of FinFET transistor sizing due to the width quantization of these devices. ISCAS'85 benchmark circuits were mapped to a typical standard cell library in 45nm bulk CMOS technology. The size characteristics of this library were adapted to build a predictive 14nm FinFET cell library. Considering transistor sizes generally used in a standard cell library, our transistor sizing improves the delay of MOSFET circuits in 52.5%, on average, keeping almost the same area and power than the sizing provided by the standard-cell library. Good results are achieved considering two simple techniques to adjust continuous to discrete sizing for FinFET circuits: rounding and truncation. These simple sizing strategies produce FinFET circuits 77% faster, on average, keeping the same area and power. Further, results show that the performance can be significantly improved if is considered a Performance Dedicated Cell Library with more cells sizes than the adopted in traditional cell libraries.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132895522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of multicore processors the emphasis incomputation is moving from sequential to parallel processing. Still, applications that require strong sequential performance do not achieve their highest performance/power when executing on current multicoresystems. As the computational needs vary significantly across different applications and with time, there is a need to dynamically allocate appropriate computational resources on demand to suit the applications' current needs, in order to minimize the energy consumption. The Energy per Instruction (EPI) could be further decreased by dynamically adapting the voltage and frequency to better fit the changing characteristics of the workload. Not only can a core be forced to a low power mode when its activity level is low, but the power saved by doing so could be opportunistically re-budgeted to other cores to boost the overall system throughput. To this end, we propose a holistic solution to energy efficiency improvement by seamlessly combining heterogeneity, Dynamic ResourceAllocation (DRA) and Dynamic Voltage and Frequency Adaptation (DVFA) capabilities to adapt the core resources to the changing demands of applications. Our results show that the proposed scheme provides anEPI reduction of about 17.9% when compared to the baseline heterogeneous multicore, 14% when compared to the baseline heterogeneous multicore with DVFA only and about 16.5% when compared to the baseline heterogeneous multicore with DRA only.
{"title":"Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores","authors":"A. Annamalai, Rance Rodrigues, I. Koren, S. Kundu","doi":"10.1109/ISVLSI.2014.110","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.110","url":null,"abstract":"With the advent of multicore processors the emphasis incomputation is moving from sequential to parallel processing. Still, applications that require strong sequential performance do not achieve their highest performance/power when executing on current multicoresystems. As the computational needs vary significantly across different applications and with time, there is a need to dynamically allocate appropriate computational resources on demand to suit the applications' current needs, in order to minimize the energy consumption. The Energy per Instruction (EPI) could be further decreased by dynamically adapting the voltage and frequency to better fit the changing characteristics of the workload. Not only can a core be forced to a low power mode when its activity level is low, but the power saved by doing so could be opportunistically re-budgeted to other cores to boost the overall system throughput. To this end, we propose a holistic solution to energy efficiency improvement by seamlessly combining heterogeneity, Dynamic ResourceAllocation (DRA) and Dynamic Voltage and Frequency Adaptation (DVFA) capabilities to adapt the core resources to the changing demands of applications. Our results show that the proposed scheme provides anEPI reduction of about 17.9% when compared to the baseline heterogeneous multicore, 14% when compared to the baseline heterogeneous multicore with DVFA only and about 16.5% when compared to the baseline heterogeneous multicore with DRA only.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132697399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhe Wang, Weichen Liu, Jiang Xu, Bin Li, R. Iyer, R. Illikkal, Xiaowen Wu, W. Mow, W. Ye
Network-on-chip (NoC) based multiprocessor system-on-chips (MPSoCs) have been proposed as promising architectures to meet modern applications' ever-increasing demands for computing capability under limited power budget. Understanding the behaviors of MPSoC applications is the key to design MPSoCs under tight power and performance constraints. In this case study, we systematically examine the computation and communication behaviors of four real applications on MPSoCs based on three popular NoC topologies. We formally model real multiprocessor applications as task communication graphs (TCG) to accurately capture their computation and communication requirements. We publicly release a multiprocessor benchmark suite called COSMIC online, which includes the TCG models. In this work, we analyze the spatial distributions of workloads and traffics for each application, and evaluate their performance and energy efficiency on various MPSoC architectures. Our study shows that fat tree based MPSoCs are good choices for applications requiring high network throughput.
{"title":"A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs","authors":"Zhe Wang, Weichen Liu, Jiang Xu, Bin Li, R. Iyer, R. Illikkal, Xiaowen Wu, W. Mow, W. Ye","doi":"10.1109/ISVLSI.2014.36","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.36","url":null,"abstract":"Network-on-chip (NoC) based multiprocessor system-on-chips (MPSoCs) have been proposed as promising architectures to meet modern applications' ever-increasing demands for computing capability under limited power budget. Understanding the behaviors of MPSoC applications is the key to design MPSoCs under tight power and performance constraints. In this case study, we systematically examine the computation and communication behaviors of four real applications on MPSoCs based on three popular NoC topologies. We formally model real multiprocessor applications as task communication graphs (TCG) to accurately capture their computation and communication requirements. We publicly release a multiprocessor benchmark suite called COSMIC online, which includes the TCG models. In this work, we analyze the spatial distributions of workloads and traffics for each application, and evaluate their performance and energy efficiency on various MPSoC architectures. Our study shows that fat tree based MPSoCs are good choices for applications requiring high network throughput.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133338635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Dhal, Piyali Datta, A. Chakrabarty, Goutam Saha, R. Pal
Digital Microfluidic Biochips (DMFB) is revolutionizing many areas of Microelectronics, Biochemistry, and Biomedical sciences. It is also known as 'Lab-on-a-Chip' for its popularity as an alternative for laboratory experiments. Pin count reduction and cross contamination avoidance are some of the core design issues for practical applications. Nowadays, due to emergency and cost effectiveness, more than one assay operations are required to be performed simultaneously. So, parallelism is a necessity in DMFB. Having an area of a given chip as a constraint, how efficiently we can use a restricted sized biochip and how much parallelism can be incorporated are the objectives of this paper. The paper presents a design automation flow that augments parallelism in applications considering cross contamination problem as well.
{"title":"An Algorithm for Parallel Assay Operations in a Restricted Sized Chip in Digital Microfluidics","authors":"D. Dhal, Piyali Datta, A. Chakrabarty, Goutam Saha, R. Pal","doi":"10.1109/ISVLSI.2014.46","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.46","url":null,"abstract":"Digital Microfluidic Biochips (DMFB) is revolutionizing many areas of Microelectronics, Biochemistry, and Biomedical sciences. It is also known as 'Lab-on-a-Chip' for its popularity as an alternative for laboratory experiments. Pin count reduction and cross contamination avoidance are some of the core design issues for practical applications. Nowadays, due to emergency and cost effectiveness, more than one assay operations are required to be performed simultaneously. So, parallelism is a necessity in DMFB. Having an area of a given chip as a constraint, how efficiently we can use a restricted sized biochip and how much parallelism can be incorporated are the objectives of this paper. The paper presents a design automation flow that augments parallelism in applications considering cross contamination problem as well.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115446719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Rehman, Adrien Blanchardon, Arwa Ben Dhia, M. Benabdenbi, R. Chotin-Avot, L. Naviner, L. Anghel, H. Mehrez, Emna Amouri, Z. Marrakchi
Nowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and the overallrobustness of a given FPGA. This paper addresses a thoroughanalysis of the cluster size impact on area and routability ofthe cluster as well as on its testability and inherent robustness. Benchmark circuits are synthesized in a range of cluster sizes(number of logic blocks per cluster) 4, 6, 8, 10 and 12 to identifythe optimum one in terms of area and routability. Then, theoverall cluster testability and its respective cost is examinedusing BIST algorithm developed for this purpose. To completethe analysis, cluster size impact on the robustness of the clusterlogic and the intra-cluster interconnect is assessed by logicalmasking ability. Results show that the cluster of size 12 offers abetter routability at relatively less test cost along with a better robustness.
{"title":"Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA","authors":"S. Rehman, Adrien Blanchardon, Arwa Ben Dhia, M. Benabdenbi, R. Chotin-Avot, L. Naviner, L. Anghel, H. Mehrez, Emna Amouri, Z. Marrakchi","doi":"10.1109/ISVLSI.2014.66","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.66","url":null,"abstract":"Nowadays, modern FPGA architectures are mainlyorganized in clusters of configurable logic resources connected togetherby depopulated interconnect. However, cluster architectureorganization and size versus inter and intra-cluster interconnectarchitectures is an ongoing optimization process, as it severelyimpacts the routability, area saving, testability and the overallrobustness of a given FPGA. This paper addresses a thoroughanalysis of the cluster size impact on area and routability ofthe cluster as well as on its testability and inherent robustness. Benchmark circuits are synthesized in a range of cluster sizes(number of logic blocks per cluster) 4, 6, 8, 10 and 12 to identifythe optimum one in terms of area and routability. Then, theoverall cluster testability and its respective cost is examinedusing BIST algorithm developed for this purpose. To completethe analysis, cluster size impact on the robustness of the clusterlogic and the intra-cluster interconnect is assessed by logicalmasking ability. Results show that the cluster of size 12 offers abetter routability at relatively less test cost along with a better robustness.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114726575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The high integration density interconnects, closerproximity of modules, and the routing phase are pivotal during the layout of 3D ICs. Heuristic based approaches are typically used to handle such NP complete problems of global routing in 3D ICs. To overcome the inherent limitations of deterministic approaches a novel methodology for multi-objective global routing based on fuzzy logic has been proposed in this paper. The guiding information generated after the placement phase is used during routing with the help of a Fuzzy Expert System to achieve thermal efficient and congestion free routing. A complete global routing solution is designed based on the proposed algorithms and the results are compared with selected fully-established global routers viz. Labyrinth, FastRoute3.0, NTHU-R, BoxRouter 2.0, and FGR. Experiments are performed over ISPD benchmarks. The proposed router called FuzzRoute achieves balanced superiority in terms of routability, runtime, and wirelength over others. The improvements on routing time for Labyrinth, BoxRouter 2.0, and FGR are 91.81%, 86.87%, and 32.16%, respectively. It may be noted that though FastRoute3.0 achieves fastest runtime, it fails to generate congestion free solutions for all benchmarks, which is overcome by the proposed FuzzRoute of the current paper. FuzzRoute also shows wirelength improvements of 17.35%, 2.88%, 2.44%, 2.83%, and 2.10% respectively over others.
{"title":"FuzzRoute: A Method for Thermally Efficient Congestion Free Global Routing in 3D ICs","authors":"Debashri Roy, P. Ghosal, S. Mohanty","doi":"10.1109/ISVLSI.2014.52","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.52","url":null,"abstract":"The high integration density interconnects, closerproximity of modules, and the routing phase are pivotal during the layout of 3D ICs. Heuristic based approaches are typically used to handle such NP complete problems of global routing in 3D ICs. To overcome the inherent limitations of deterministic approaches a novel methodology for multi-objective global routing based on fuzzy logic has been proposed in this paper. The guiding information generated after the placement phase is used during routing with the help of a Fuzzy Expert System to achieve thermal efficient and congestion free routing. A complete global routing solution is designed based on the proposed algorithms and the results are compared with selected fully-established global routers viz. Labyrinth, FastRoute3.0, NTHU-R, BoxRouter 2.0, and FGR. Experiments are performed over ISPD benchmarks. The proposed router called FuzzRoute achieves balanced superiority in terms of routability, runtime, and wirelength over others. The improvements on routing time for Labyrinth, BoxRouter 2.0, and FGR are 91.81%, 86.87%, and 32.16%, respectively. It may be noted that though FastRoute3.0 achieves fastest runtime, it fails to generate congestion free solutions for all benchmarks, which is overcome by the proposed FuzzRoute of the current paper. FuzzRoute also shows wirelength improvements of 17.35%, 2.88%, 2.44%, 2.83%, and 2.10% respectively over others.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114769812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaolin Xu, Vikram B. Suresh, Raghavan Kumar, W. Burleson
Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are gaining significant importance in the field of hardware security. These crypto-graphic primitives harness randomness from IC fabrication process and on-chip noise respectively, necessitating unconventional post-Silicon (Si) validation techniques. In this work, we present a brief survey of post-Si validation techniques for PUFs and TRNGs, highlighting the importance of testing PUFs resilience against novel attacks and monitoring bias in TRNGs. We also propose novel techniques for monitoring PUFs reliability and measuring bias in TRNGs. The proposed techniques do not only facilitate on-chip calibration for hardware security systems, but can also be used as a countermeasure against fault-attacks.
{"title":"Post-Silicon Validation and Calibration of Hardware Security Primitives","authors":"Xiaolin Xu, Vikram B. Suresh, Raghavan Kumar, W. Burleson","doi":"10.1109/ISVLSI.2014.80","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.80","url":null,"abstract":"Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are gaining significant importance in the field of hardware security. These crypto-graphic primitives harness randomness from IC fabrication process and on-chip noise respectively, necessitating unconventional post-Silicon (Si) validation techniques. In this work, we present a brief survey of post-Si validation techniques for PUFs and TRNGs, highlighting the importance of testing PUFs resilience against novel attacks and monitoring bias in TRNGs. We also propose novel techniques for monitoring PUFs reliability and measuring bias in TRNGs. The proposed techniques do not only facilitate on-chip calibration for hardware security systems, but can also be used as a countermeasure against fault-attacks.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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