For more than four decades, Complementary Metal-Oxide-Semiconductor (CMOS) Field Effect Transistors (FETs) have been the baseline technology for implementing digital computation systems. CMOS transistors natively implement Not-AND (NAND)- and Not-OR (NOR)-based logic operators. Nowadays, we observe a trend towards devices with an increased set of logic capabilities, i.e., with the ability to realize in a compact way specific logic operators as compared to the standard CMOS. In particular, controllable-polarity devices enable a native and compact realization of eXclusive-OR (XOR)- and MAJority (MAJ)- logic functions, and open a large panel of opportunities for future high-performance computing systems. However, main current logic synthesis tools exploit algorithms using NAND/NOR representations that are not able to fully exploit the capabilities of novel XOR- and MAJ-oriented technologies. In this paper, we review some recent work that aims at providing novel logic synthesis techniques that natively assess the logic capabilities of XOR- and MAJ-operators.
{"title":"Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis","authors":"P. Gaillardon, L. Amarù, G. Micheli","doi":"10.1109/ISVLSI.2014.107","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.107","url":null,"abstract":"For more than four decades, Complementary Metal-Oxide-Semiconductor (CMOS) Field Effect Transistors (FETs) have been the baseline technology for implementing digital computation systems. CMOS transistors natively implement Not-AND (NAND)- and Not-OR (NOR)-based logic operators. Nowadays, we observe a trend towards devices with an increased set of logic capabilities, i.e., with the ability to realize in a compact way specific logic operators as compared to the standard CMOS. In particular, controllable-polarity devices enable a native and compact realization of eXclusive-OR (XOR)- and MAJority (MAJ)- logic functions, and open a large panel of opportunities for future high-performance computing systems. However, main current logic synthesis tools exploit algorithms using NAND/NOR representations that are not able to fully exploit the capabilities of novel XOR- and MAJ-oriented technologies. In this paper, we review some recent work that aims at providing novel logic synthesis techniques that natively assess the logic capabilities of XOR- and MAJ-operators.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130018498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li
The poor yield of current available processes for Through-Silicon Via (TSV) fabrication leads to serious influence on the robustness of the vertical communications in 3D NoCs. The fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of 2D NoCs. In this paper, we propose a high-performance reliable routing scheme HARS, which is deadlock-free by obeying a mid-node-searching method raised for 3D Mesh NoCs without requiring any Virtual Channels (VCs). In HARS, we adopt DyADM routing, extending the classical 2D routing algorithm DyAD to 3D scenario in presence of permanent faults on the vertical links. HARS is able to support both one-fault and multi-fault models. The experimental results show that HARS has better performance, improved reliability and lower overhead compared to the state-of-the-art reliable routing schemes.
{"title":"HARS: A High-Performance Reliable Routing Scheme for 3D NoCs","authors":"Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li","doi":"10.1109/ISVLSI.2014.56","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.56","url":null,"abstract":"The poor yield of current available processes for Through-Silicon Via (TSV) fabrication leads to serious influence on the robustness of the vertical communications in 3D NoCs. The fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of 2D NoCs. In this paper, we propose a high-performance reliable routing scheme HARS, which is deadlock-free by obeying a mid-node-searching method raised for 3D Mesh NoCs without requiring any Virtual Channels (VCs). In HARS, we adopt DyADM routing, extending the classical 2D routing algorithm DyAD to 3D scenario in presence of permanent faults on the vertical links. HARS is able to support both one-fault and multi-fault models. The experimental results show that HARS has better performance, improved reliability and lower overhead compared to the state-of-the-art reliable routing schemes.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131217859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Phase-based optimization specializes system configurations to runtime application requirements in order to achieve optimization goals. Due to potentially large design spaces in configurable systems, one major challenge of phase-based optimization is determining the best configuration for achieving optimization goals without incurring significant optimization overhead during design space exploration. This work proposes phase distance mapping, which uses the correlation between phases and the phases' characteristics to dynamically determine optimal or near-optimal configurations with minimal design space exploration, thereby minimizing optimization overhead.
{"title":"Dynamic Phase-Based Optimization of Embedded Systems","authors":"Tosiron Adegbija, A. Gordon-Ross","doi":"10.1109/ISVLSI.2014.17","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.17","url":null,"abstract":"Phase-based optimization specializes system configurations to runtime application requirements in order to achieve optimization goals. Due to potentially large design spaces in configurable systems, one major challenge of phase-based optimization is determining the best configuration for achieving optimization goals without incurring significant optimization overhead during design space exploration. This work proposes phase distance mapping, which uses the correlation between phases and the phases' characteristics to dynamically determine optimal or near-optimal configurations with minimal design space exploration, thereby minimizing optimization overhead.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129540096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The memristor is a novel non-volatile device having a large variable resistance range. Physical memristors can be laid out in a high density grid known as a crossbar. In this paper we propose a memristor crossbar based static routing switch design. We logically connect two wires within a crossbar by setting their corresponding cross-point memristor to a low resistance state. Conversely we logically disconnect the wires by setting the corresponding memristor to a high resistance state. Our evaluations show that the proposed static switch consumes extremely low power and has a high density compared to existing designs.
{"title":"Memristor Crossbar Based Programmable Interconnects","authors":"Raqibul Hasan, T. Taha","doi":"10.1109/ISVLSI.2014.100","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.100","url":null,"abstract":"The memristor is a novel non-volatile device having a large variable resistance range. Physical memristors can be laid out in a high density grid known as a crossbar. In this paper we propose a memristor crossbar based static routing switch design. We logically connect two wires within a crossbar by setting their corresponding cross-point memristor to a low resistance state. Conversely we logically disconnect the wires by setting the corresponding memristor to a high resistance state. Our evaluations show that the proposed static switch consumes extremely low power and has a high density compared to existing designs.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126732311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Networks-on-Chip (NoC) have emerged as communication backbones for enabling high degree of integration in future many-core chips. Despite their advantages, the communication is multi-hop and causes high latency and power dissipation, especially in larger systems. Wireless Network-on-Chip (WNoC) significantly improves the latency over traditional wired NoCs for multi-core systems. But on-chip wireless interfaces (WIs) have their own power and area overhead. In this paper we design and implement a Dynamic Voltage Frequency Scaling (DVFS) technique and extend it to provide power gating to the WIs. This approach effectively reduces the energy consumption in multi core systems. A centralized controller with dual-band wireless transceiver implements per-core DVFS. The scheme ensures balanced workload and energy consumption of the chip and efficient power gating for the WIs. It helps to alleviate the power consumption up to 33.085 % for on-chip communications infrastructure with little overheads.
{"title":"An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-Chip","authors":"H. Mondal, G. Harsha, Sujay Deb","doi":"10.1109/ISVLSI.2014.98","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.98","url":null,"abstract":"Networks-on-Chip (NoC) have emerged as communication backbones for enabling high degree of integration in future many-core chips. Despite their advantages, the communication is multi-hop and causes high latency and power dissipation, especially in larger systems. Wireless Network-on-Chip (WNoC) significantly improves the latency over traditional wired NoCs for multi-core systems. But on-chip wireless interfaces (WIs) have their own power and area overhead. In this paper we design and implement a Dynamic Voltage Frequency Scaling (DVFS) technique and extend it to provide power gating to the WIs. This approach effectively reduces the energy consumption in multi core systems. A centralized controller with dual-band wireless transceiver implements per-core DVFS. The scheme ensures balanced workload and energy consumption of the chip and efficient power gating for the WIs. It helps to alleviate the power consumption up to 33.085 % for on-chip communications infrastructure with little overheads.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129368000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is no secret that modern computer systems are vulnerable to threats such as side-channel attack or reverse engineering whereby sensitive data or code could be unintentionally leaked to an adversary. It is the premise of this work that the mitigation of such security threats can be achieved by leveraging the inherent complexity of emerging chaos-based computing (computer systems built from chaotic oscillators). More specifically, this paper considers a chaos-based arithmetic logic unit which consists of many unique implementations for each possible operation. Generalizing to a chaos-based computer, a large number of implementations per operation can enable the obfuscation of critical code or data. In such a system, any two functionally equivalent operations are unique in terms of control parameters, power profiles, and so on. Furthermore, many possible implementations for each operational code can be leveraged to compile a program that is uniquely defined in terms of what the user knows -- such knowledge which itself could be protected via encryption. The frequencies of the various operations are shown to approach that of a probabilistic system as the circuit is allowed to evolve in time. Further, the difficulty of a successful attack is assumed to be directly related to the number of unique op-code sets possible which is shown to grow exponentially with allowed evolution time for the proposed chaos-based arithmetic logic unit.
{"title":"A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation","authors":"G. Rose","doi":"10.1109/ISVLSI.2014.72","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.72","url":null,"abstract":"It is no secret that modern computer systems are vulnerable to threats such as side-channel attack or reverse engineering whereby sensitive data or code could be unintentionally leaked to an adversary. It is the premise of this work that the mitigation of such security threats can be achieved by leveraging the inherent complexity of emerging chaos-based computing (computer systems built from chaotic oscillators). More specifically, this paper considers a chaos-based arithmetic logic unit which consists of many unique implementations for each possible operation. Generalizing to a chaos-based computer, a large number of implementations per operation can enable the obfuscation of critical code or data. In such a system, any two functionally equivalent operations are unique in terms of control parameters, power profiles, and so on. Furthermore, many possible implementations for each operational code can be leveraged to compile a program that is uniquely defined in terms of what the user knows -- such knowledge which itself could be protected via encryption. The frequencies of the various operations are shown to approach that of a probabilistic system as the circuit is allowed to evolve in time. Further, the difficulty of a successful attack is assumed to be directly related to the number of unique op-code sets possible which is shown to grow exponentially with allowed evolution time for the proposed chaos-based arithmetic logic unit.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129379982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Use of non-volatile memory (NVM) devices such as resistive RAM (ReRAM) and spin transfer torque RAM (STT-RAM) for designing on-chip caches holds the promise of providing a high-density, low-leakage alternative to SRAM. However, low write endurance of NVMs, along with the write-variation introduced by existing cache management schemes significantly limits the lifetime of NVM caches. We present LastingNVCache, a technique for improving the cache lifetime by mitigating the intra-set write variation. LastingNVCache works on the key idea that by periodically flushing a frequently-written data-item, next time the block can be made to load into a cold block in the set. Through this, the future writes to that data-item can be redirected from a hot block to a cold block, which leads to improvement in the cache lifetime. Microarchitectural simulations have shown that LastingNVCache provides 6.36X, 9.79X, and 10.94X improvement in lifetime for single, dual and quad-core systems, respectively. Also, its implementation overhead is small and it outperforms a recently proposed technique for improving lifetime of NVM caches.
{"title":"LastingNVCache: A Technique for Improving the Lifetime of Non-volatile Caches","authors":"Sparsh Mittal, J. Vetter, Dong Li","doi":"10.1109/ISVLSI.2014.69","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.69","url":null,"abstract":"Use of non-volatile memory (NVM) devices such as resistive RAM (ReRAM) and spin transfer torque RAM (STT-RAM) for designing on-chip caches holds the promise of providing a high-density, low-leakage alternative to SRAM. However, low write endurance of NVMs, along with the write-variation introduced by existing cache management schemes significantly limits the lifetime of NVM caches. We present LastingNVCache, a technique for improving the cache lifetime by mitigating the intra-set write variation. LastingNVCache works on the key idea that by periodically flushing a frequently-written data-item, next time the block can be made to load into a cold block in the set. Through this, the future writes to that data-item can be redirected from a hot block to a cold block, which leads to improvement in the cache lifetime. Microarchitectural simulations have shown that LastingNVCache provides 6.36X, 9.79X, and 10.94X improvement in lifetime for single, dual and quad-core systems, respectively. Also, its implementation overhead is small and it outperforms a recently proposed technique for improving lifetime of NVM caches.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123963158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing complexity of modern electronic devices driven by consumer demand and technological advancements presents significant challenges for designers. The reduced feature size and increased capabilities lead to more complex designs as more sub-systems are packed into a single chip. Traditional synthesis and optimization methods which involve CAD tools for accurate simulation are computationally time expensive and even become infeasible especially in designs using nanoelectronic technology due to increased design factors and the exponentially increasing design space. The current objective is to explore techniques that produce optimal designs while reducing the design effort. Metamodeling techniques have been used in this respect to reduce the cost of manual iterative circuit sizing during synthesis. Existing metamodeling techniques however are unable to capture the effects of process variation which are dominant in deep nanometer regions. This work explores Kriging techniques for fast and accurate design optimization of nanoscale analog circuits.
{"title":"Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits","authors":"Oghenekarho Okobiah, S. Mohanty, E. Kougianos","doi":"10.1109/ISVLSI.2014.12","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.12","url":null,"abstract":"The increasing complexity of modern electronic devices driven by consumer demand and technological advancements presents significant challenges for designers. The reduced feature size and increased capabilities lead to more complex designs as more sub-systems are packed into a single chip. Traditional synthesis and optimization methods which involve CAD tools for accurate simulation are computationally time expensive and even become infeasible especially in designs using nanoelectronic technology due to increased design factors and the exponentially increasing design space. The current objective is to explore techniques that produce optimal designs while reducing the design effort. Metamodeling techniques have been used in this respect to reduce the cost of manual iterative circuit sizing during synthesis. Existing metamodeling techniques however are unable to capture the effects of process variation which are dominant in deep nanometer regions. This work explores Kriging techniques for fast and accurate design optimization of nanoscale analog circuits.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":" 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120825844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design of core based three dimensional (3D) system-on-chip (SOC) is gaining a remarkable attention in modern days' semiconductor industry. Testing of 3D SOC is considered as one of the important challenge and hence efficient test techniques are required. The objective of this paper is to design efficient test access mechanism (TAM) and test scheduling architecture of different cores of the SOC such that the overall test time of that SOC is minimized. In this work, we have proposed two session-based heuristic approaches. Experimental results are presented for several ITC'02 benchmark SOCs which show promising results for different TAM width allocation.
{"title":"Session Based Core Test Scheduling for 3D SOCs","authors":"S. Roy, Payel Ghosh, H. Rahaman, C. Giri","doi":"10.1109/ISVLSI.2014.61","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.61","url":null,"abstract":"Design of core based three dimensional (3D) system-on-chip (SOC) is gaining a remarkable attention in modern days' semiconductor industry. Testing of 3D SOC is considered as one of the important challenge and hence efficient test techniques are required. The objective of this paper is to design efficient test access mechanism (TAM) and test scheduling architecture of different cores of the SOC such that the overall test time of that SOC is minimized. In this work, we have proposed two session-based heuristic approaches. Experimental results are presented for several ITC'02 benchmark SOCs which show promising results for different TAM width allocation.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124137346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiaoyan Chen, C. Spagnol, S. Grandhi, E. Popovici, S. Cotofana, A. Amaricai
With the advent of deep submicron CMOS technology, process parameter statistical variations are increasing resulting in unpredictable device behaviour. The issue is even aggravated by low power requirements which are stretching transistor operation into near/sub threshold regime. Consequently, traditional delay models fail to accurately capture the circuit behaviour. In view of this we introduce an Inverse Gaussian Distribution (IGD) based delay model, which accurately captures the delay distribution under process variations at ultra low, near or below threshold, power supply values. We demonstrate that the IGD model captures the transistor delay distribution with a greater accuracy than the traditional Gaussian one. Moreover it exhibits linear compositionality such that the key model parameters can be straightforward propagated form device/gate level to circuit level. Our simulations indicate that, when compared with Monte Carlo SPICE simulation results, it provides high accuracy, e.g., an average error less than 0.8%, 1.2%, and 1.7% for Majority Voter, XOR gate, and 16-bit Ripple Carry Adder, respectively, while providing orders of magnitude simulation time reductions.
随着深亚微米CMOS技术的出现，工艺参数统计变化正在增加，导致不可预测的器件行为。低功耗要求将晶体管工作扩展到接近/亚阈值范围，这甚至加剧了这个问题。因此，传统的延迟模型不能准确地捕捉电路的行为。鉴于此，我们引入了一种基于逆高斯分布(IGD)的延迟模型，该模型可以准确捕获超低、接近或低于阈值的电源值下过程变化下的延迟分布。我们证明了IGD模型比传统的高斯模型更准确地捕获晶体管延迟分布。此外，它还表现出线性组合性，使得关键模型参数可以直接从器件/栅极级传播到电路级。我们的模拟表明，与Monte Carlo SPICE模拟结果相比，它提供了很高的准确性，例如，对于Majority Voter, XOR门和16位纹波进位加法器，它的平均误差分别小于0.8%，1.2%和1.7%，同时提供了数量级的模拟时间减少。
{"title":"Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits","authors":"Jiaoyan Chen, C. Spagnol, S. Grandhi, E. Popovici, S. Cotofana, A. Amaricai","doi":"10.1109/ISVLSI.2014.41","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.41","url":null,"abstract":"With the advent of deep submicron CMOS technology, process parameter statistical variations are increasing resulting in unpredictable device behaviour. The issue is even aggravated by low power requirements which are stretching transistor operation into near/sub threshold regime. Consequently, traditional delay models fail to accurately capture the circuit behaviour. In view of this we introduce an Inverse Gaussian Distribution (IGD) based delay model, which accurately captures the delay distribution under process variations at ultra low, near or below threshold, power supply values. We demonstrate that the IGD model captures the transistor delay distribution with a greater accuracy than the traditional Gaussian one. Moreover it exhibits linear compositionality such that the key model parameters can be straightforward propagated form device/gate level to circuit level. Our simulations indicate that, when compared with Monte Carlo SPICE simulation results, it provides high accuracy, e.g., an average error less than 0.8%, 1.2%, and 1.7% for Majority Voter, XOR gate, and 16-bit Ripple Carry Adder, respectively, while providing orders of magnitude simulation time reductions.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"24 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132830092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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