Post-silicon debug is widely acknowledged as a bottleneck in SoC design methodology. A major challenge during post-silicon debug is the limited observability of internal signals. Existing approaches try to select a small set of beneficial trace signals that can maximize observability. Unfortunately, these techniques do not consider design constraints such as routability of the selected signals or routing congestion. Therefore, in reality, it may not be possible to route the selected signals. We propose a layout-aware signal selection algorithm that takes into account both observability and routing congestion. Our experimental results demonstrate that our proposed approach can select routing friendly trace signals with negligible impact on observability.
{"title":"Layout-Aware Selection of Trace Signals for Post-Silicon Debug","authors":"Prateek Thakyal, P. Mishra","doi":"10.1109/ISVLSI.2014.19","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.19","url":null,"abstract":"Post-silicon debug is widely acknowledged as a bottleneck in SoC design methodology. A major challenge during post-silicon debug is the limited observability of internal signals. Existing approaches try to select a small set of beneficial trace signals that can maximize observability. Unfortunately, these techniques do not consider design constraints such as routability of the selected signals or routing congestion. Therefore, in reality, it may not be possible to route the selected signals. We propose a layout-aware signal selection algorithm that takes into account both observability and routing congestion. Our experimental results demonstrate that our proposed approach can select routing friendly trace signals with negligible impact on observability.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"592 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121981451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Higami, Hiroshi Takahashi, Shin-ya Kobayashi, K. Saluja
This paper presents a diagnosis method for gate delay faults in the presence of clock delay faults. The method deduces candidate faults using a single gate delay fault dictionary and a single clock delay fault dictionary, which contain the information of latest transition time of signals as well as output logic values. To reduce the diagnostic ambiguity we remove those faults from the candidate fault list which provide a contradiction between the circuit responses and responses stored in the dictionary. Since the dictionary is not generated by considering the simultaneous existence of a gate delay fault and a clock delay fault, some heuristic parameters are introduced in order to compensate the difference between the dictionaries and the responses in a circuit under diagnosis.
{"title":"Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults","authors":"Y. Higami, Hiroshi Takahashi, Shin-ya Kobayashi, K. Saluja","doi":"10.1109/ISVLSI.2014.60","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.60","url":null,"abstract":"This paper presents a diagnosis method for gate delay faults in the presence of clock delay faults. The method deduces candidate faults using a single gate delay fault dictionary and a single clock delay fault dictionary, which contain the information of latest transition time of signals as well as output logic values. To reduce the diagnostic ambiguity we remove those faults from the candidate fault list which provide a contradiction between the circuit responses and responses stored in the dictionary. Since the dictionary is not generated by considering the simultaneous existence of a gate delay fault and a clock delay fault, some heuristic parameters are introduced in order to compensate the difference between the dictionaries and the responses in a circuit under diagnosis.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126419316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a dynamic frequency scaling (DFS) technique, PIDDFS, targeting on real-time applications running on GPU platforms. PIDDFS technique applies a feedback controlling algorithm, Proportional-Integral-Derivative (PID), to scale the frequencies of core domain and DRAM domains based on memory access statistics. The major goal of PIDDFS is minimizing the energy consumption while the memory traffic is intensive or even causes the pipeline to stall. Performance can also be improved via increasing the frequency while the memory traffic is in a starving status. Based on the feedback, closed-loop controlling model with proper leading and lagging phases, PIDDFS can respond timely towards the variations during runtime and ignore the insignificant noise that causes unnecessary frequency adjustments. The proposed technique has been simulated on GPGPU-Sim, a cycle-level simulator of GPU architecture and power savings have been modeled by GPUWattch. According to the benchmark simulation result, a power saving of more than 23% with a performance improvement of 4% is achieved at the same time. Stalled cycles caused by saturation of memory request queues are reduced over 40%.
{"title":"A Feedback, Runtime Technique for Scaling the Frequency in GPU Architectures","authors":"Yue Wang, N. Ranganathan","doi":"10.1109/ISVLSI.2014.34","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.34","url":null,"abstract":"This paper presents a dynamic frequency scaling (DFS) technique, PIDDFS, targeting on real-time applications running on GPU platforms. PIDDFS technique applies a feedback controlling algorithm, Proportional-Integral-Derivative (PID), to scale the frequencies of core domain and DRAM domains based on memory access statistics. The major goal of PIDDFS is minimizing the energy consumption while the memory traffic is intensive or even causes the pipeline to stall. Performance can also be improved via increasing the frequency while the memory traffic is in a starving status. Based on the feedback, closed-loop controlling model with proper leading and lagging phases, PIDDFS can respond timely towards the variations during runtime and ignore the insignificant noise that causes unnecessary frequency adjustments. The proposed technique has been simulated on GPGPU-Sim, a cycle-level simulator of GPU architecture and power savings have been modeled by GPUWattch. According to the benchmark simulation result, a power saving of more than 23% with a performance improvement of 4% is achieved at the same time. Stalled cycles caused by saturation of memory request queues are reduced over 40%.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":" June","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120826396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With device dimensions reaching their physical limits, there has been a tremendous focus on development of post CMOS technologies. Carbon based transistors, including graphene and carbon nanotubes, are seen as potential candidates to replace traditional CMOS devices. In that, floating gate graphene field effect transistors (F-GFETs) are preferred over dual gate graphene field effect transistors (D-GFETs) due to their ability to provide variable threshold voltage using a single power supply. In this paper, we present a novel analytical model for the design of a complementary inverter using floating gate bilayer graphene field-effect transistors (F-GFETs). Our proposed model describes the i-v characteristics of the F-GFET for all the regions of operation considering both hole and electron conduction. The i-v characteristics obtained using our model are compared with that of D-GFETs. Based on our proposed model, we obtain the transfer characteristics of a complementary inverter using F-GFETs. Our proposed inverter gives better transfer characteristics when compared with previously reported inverters using either F-GFET or chemically doped D-GFETs.
{"title":"Analytical Model for Inverter Design Using Floating Gate Graphene Field Effect Transistors","authors":"A. Nishad, Aditya Dalakoti, Ashish Jindal, Rahul Kumar, Somesh Kumar, Rohit Sharma","doi":"10.1109/ISVLSI.2014.85","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.85","url":null,"abstract":"With device dimensions reaching their physical limits, there has been a tremendous focus on development of post CMOS technologies. Carbon based transistors, including graphene and carbon nanotubes, are seen as potential candidates to replace traditional CMOS devices. In that, floating gate graphene field effect transistors (F-GFETs) are preferred over dual gate graphene field effect transistors (D-GFETs) due to their ability to provide variable threshold voltage using a single power supply. In this paper, we present a novel analytical model for the design of a complementary inverter using floating gate bilayer graphene field-effect transistors (F-GFETs). Our proposed model describes the i-v characteristics of the F-GFET for all the regions of operation considering both hole and electron conduction. The i-v characteristics obtained using our model are compared with that of D-GFETs. Based on our proposed model, we obtain the transfer characteristics of a complementary inverter using F-GFETs. Our proposed inverter gives better transfer characteristics when compared with previously reported inverters using either F-GFET or chemically doped D-GFETs.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"360 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120939860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power consumption has become a major concern of integrated circuit (IC) design, especially for SRAM design. Reducing the supply voltage to the near-threshold region is one method to reduce the power consumption. However, operating in this region makes the circuit more sensitive to process variations. In this paper, the impact of process variations on a 32-nm 6T SRAM cell under near-threshold voltage is studied using Monte Carlo simulations to evaluate the potential for soft errors. The double-exponential current source is used to simulate the strike of an ionizing particle onto nodes of interest. The results show that threshold voltage variability is a more significant parameter affecting the critical charge distribution of the circuit under both near-threshold voltage and nominal supply voltage. Also under near-threshold voltage, the leakage power in standby mode is reduced compared to the nominal supply voltage, and the write delay time of the SRAM circuit is much larger than the nominal supply voltage.
{"title":"Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold Voltage","authors":"L. Kou, W. H. Robinson","doi":"10.1109/ISVLSI.2014.73","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.73","url":null,"abstract":"Power consumption has become a major concern of integrated circuit (IC) design, especially for SRAM design. Reducing the supply voltage to the near-threshold region is one method to reduce the power consumption. However, operating in this region makes the circuit more sensitive to process variations. In this paper, the impact of process variations on a 32-nm 6T SRAM cell under near-threshold voltage is studied using Monte Carlo simulations to evaluate the potential for soft errors. The double-exponential current source is used to simulate the strike of an ionizing particle onto nodes of interest. The results show that threshold voltage variability is a more significant parameter affecting the critical charge distribution of the circuit under both near-threshold voltage and nominal supply voltage. Also under near-threshold voltage, the leakage power in standby mode is reduced compared to the nominal supply voltage, and the write delay time of the SRAM circuit is much larger than the nominal supply voltage.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131575745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Network on Chip (NoC) is a sophisticated communication infrastructure that provides quality of service (QoS) guarantees for a complex Systems-on-Chip (SoC) application. Some applications demand guaranteed end-to-end latency. Mapping algorithms are used to map an application on an NoC to satisfy the bandwidth constraints and end-to-end latency requirements. The design of the mapping algorithms determines their capability in reaching a near optimal or optimal solution. Genetic algorithms (GA) based NoC mapping algorithms are increasingly used for mapping. They search the mapping space efficiently using a cost function to estimate a performance parameter that represents the "cost" associated with the solution, in this case latency. Generally analytical models are used to estimate cost, however, analytical models are not able to accurately estimate worst-case end-to-end latency. Motivated by this, we are proposing to use a formal NoC model to accurately estimate end-to-end latency, and incorporate it into GA cost function. The capability of the proposed method to find a near optimal or optimal solution is demonstrated with sample applications.
{"title":"Improving GA-Based NoC Mapping Algorithms Using a Formal Model","authors":"V. Palaniveloo, Jude Angelo Ambrose, A. Sowmya","doi":"10.1109/ISVLSI.2014.64","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.64","url":null,"abstract":"Network on Chip (NoC) is a sophisticated communication infrastructure that provides quality of service (QoS) guarantees for a complex Systems-on-Chip (SoC) application. Some applications demand guaranteed end-to-end latency. Mapping algorithms are used to map an application on an NoC to satisfy the bandwidth constraints and end-to-end latency requirements. The design of the mapping algorithms determines their capability in reaching a near optimal or optimal solution. Genetic algorithms (GA) based NoC mapping algorithms are increasingly used for mapping. They search the mapping space efficiently using a cost function to estimate a performance parameter that represents the \"cost\" associated with the solution, in this case latency. Generally analytical models are used to estimate cost, however, analytical models are not able to accurately estimate worst-case end-to-end latency. Motivated by this, we are proposing to use a formal NoC model to accurately estimate end-to-end latency, and incorporate it into GA cost function. The capability of the proposed method to find a near optimal or optimal solution is demonstrated with sample applications.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131078196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Continuous shrinking of device size has introduced reliability as a new design challenge for embedded processors. Error mitigation techniques trade off reliability for other design metrics such as performance and power consumption. State-of-the-art fault-tolerant designs involve cross-layer error management, which lead to an over-protected system. To address the overhead issue, asymmetric reliability utilizes unequal protection levels for different system components based on various criticality requirements. In this paper, We propose a versatile asymmetric error detection/correction framework based on instruction-level vulnerability analysis. Inspired from information-theoretic view of processor as a noisy network, asymmetric error correction coding schemes are designed and exploited to efficiently trade off reliability for other performance constraints. Multiple novel asymmetric fault-tolerant design techniques are proposed, which are evaluated through a range of experiments.
{"title":"Processor Design with Asymmetric Reliability","authors":"Z. Wang, G. Paul, A. Chattopadhyay","doi":"10.1109/ISVLSI.2014.63","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.63","url":null,"abstract":"Continuous shrinking of device size has introduced reliability as a new design challenge for embedded processors. Error mitigation techniques trade off reliability for other design metrics such as performance and power consumption. State-of-the-art fault-tolerant designs involve cross-layer error management, which lead to an over-protected system. To address the overhead issue, asymmetric reliability utilizes unequal protection levels for different system components based on various criticality requirements. In this paper, We propose a versatile asymmetric error detection/correction framework based on instruction-level vulnerability analysis. Inspired from information-theoretic view of processor as a noisy network, asymmetric error correction coding schemes are designed and exploited to efficiently trade off reliability for other performance constraints. Multiple novel asymmetric fault-tolerant design techniques are proposed, which are evaluated through a range of experiments.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115166890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advancement in deep submicron (DSM) technologies led to miniaturization. However, it also increased the vulnerability against some electrical and device non-idealities, including the soft errors. These errors are significant threat to the reliable functionality of digital circuits. Several techniques for the detection and deterrence of soft errors (to improve the reliability) have been proposed, both in synchronous and asynchronous domain. In this paper we propose a low power and soft error tolerant solution for synchronous systems that leverages the asynchronous pipeline within a synchronous framework. We named our technique as macro synchronous micro asynchronous (MSMA) pipeline. We provided a framework along with timing analysis of the MSMA technique. MSMA is implemented using a macro synchronous system and soft error tolerant and low power version of null convention logic (NCL) asynchronous circuit. It is found out that this solution can easily replace the intermediate stages of synchronous and asynchronous pipelines without changing its interface protocol. Such NCL asynchronous circuits can be used as a standard cell in the synchronous ASIC design flow. Power and performance analysis is done using electrical simulations, which shows that this techniques consumes at least 22% less power and 45% less energy delay product (EDP) compared to state-of-the-art solutions.
{"title":"Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline","authors":"F. Lodhi, S. R. Hasan, O. Hasan, F. Awwad","doi":"10.1109/ISVLSI.2014.59","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.59","url":null,"abstract":"Advancement in deep submicron (DSM) technologies led to miniaturization. However, it also increased the vulnerability against some electrical and device non-idealities, including the soft errors. These errors are significant threat to the reliable functionality of digital circuits. Several techniques for the detection and deterrence of soft errors (to improve the reliability) have been proposed, both in synchronous and asynchronous domain. In this paper we propose a low power and soft error tolerant solution for synchronous systems that leverages the asynchronous pipeline within a synchronous framework. We named our technique as macro synchronous micro asynchronous (MSMA) pipeline. We provided a framework along with timing analysis of the MSMA technique. MSMA is implemented using a macro synchronous system and soft error tolerant and low power version of null convention logic (NCL) asynchronous circuit. It is found out that this solution can easily replace the intermediate stages of synchronous and asynchronous pipelines without changing its interface protocol. Such NCL asynchronous circuits can be used as a standard cell in the synchronous ASIC design flow. Power and performance analysis is done using electrical simulations, which shows that this techniques consumes at least 22% less power and 45% less energy delay product (EDP) compared to state-of-the-art solutions.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125252603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The differential power analysis (DPA) attack is a well known major threat to cryptographic devices such as smart cards or other embedded systems. Quantification of resistance or robustness of a cryptographic device against the differential power analysis attack is lacking. We propose a DPA effectiveness (inverse of robustness) metric. We develop a logic graph based computational method for DPA effectiveness. Based on our insights with DPA effectiveness measures of an adder we develop a countermeasure. It enhances the proposed DPA resistance metric in normal 0-private circuits to the level of t-private circuits for t ≥ 1 at a smaller area and delay overhead. It deploys EXOR sum-of-products (ESOP) expressions to make the power consumption independent of input values or intermediate values. The logic synthesis system SIS was modified to incorporate both the proposed DPA effectiveness metric computation and the DPA-resistance transformation. The experiments show that the area and delay overhead of the proposed design method are 59.8% and 19.4%, respectively, compared to the original ESOP circuits averaged over MCNC benchmark suite. This, however, still takes 37.7% less area and 6.4% lower delay compared to 1-private implementation of the MCNC benchmark suite while maintaining the same DPA resistance.
{"title":"Towards Making Private Circuits Practical: DPA Resistant Private Circuits","authors":"Jungmin Park, A. Tyagi","doi":"10.1109/ISVLSI.2014.24","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.24","url":null,"abstract":"The differential power analysis (DPA) attack is a well known major threat to cryptographic devices such as smart cards or other embedded systems. Quantification of resistance or robustness of a cryptographic device against the differential power analysis attack is lacking. We propose a DPA effectiveness (inverse of robustness) metric. We develop a logic graph based computational method for DPA effectiveness. Based on our insights with DPA effectiveness measures of an adder we develop a countermeasure. It enhances the proposed DPA resistance metric in normal 0-private circuits to the level of t-private circuits for t ≥ 1 at a smaller area and delay overhead. It deploys EXOR sum-of-products (ESOP) expressions to make the power consumption independent of input values or intermediate values. The logic synthesis system SIS was modified to incorporate both the proposed DPA effectiveness metric computation and the DPA-resistance transformation. The experiments show that the area and delay overhead of the proposed design method are 59.8% and 19.4%, respectively, compared to the original ESOP circuits averaged over MCNC benchmark suite. This, however, still takes 37.7% less area and 6.4% lower delay compared to 1-private implementation of the MCNC benchmark suite while maintaining the same DPA resistance.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125512451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In practice, any integrated physical unclonable function (PUF) must be accessed through a logical interface. The interface may add additional functionalities such as access control, implement a (measurement) noise reduction layer, etc. In many PUF applications, the interface in fact hides the PUF itself: users only interact with the PUF's interface, and cannot "see" or verify what is behind the interface. This immediately gives rise to a security problem: how does the user know he is interacting with a properly behaving interface wrapped around a proper PUF? This question is not merely theoretical, but has strong relevance for PUF application security: It has been shown recently that a badly behaving interface could, e.g., log a history of PUF queries which an adversary can read out using some trapdoor, or may output "false" PUF responses that the adversary can predict or influence RvD-IEEESP13. This allows attacks on a considerable number of PUF protocols RvD-IEEESP13. Since we currently do not know how to authenticate proper interface behavior in practice, the security of many PUF applications implicitly rests on the mere assumption that an adversary cannot modify or enhance a PUF interface in a "bad" way. This is quite a strong hypothesis, which should be stated more explicitly in the literature. In this paper, we explicitly address this point, following and partly expanding earlier works RvD-IEEESP13. We add to the picture the need for rigorous security which is characterized by some security parameter λ (an adversary has "negl(λ) probability to successfully software clone/model a PUF"). First, this means that we need so-called Strong PUFs with a larger than poly(λ) input/challenge space. In order to have scalable PUF designs (which do not blow up in chip surface or volume for increasing λ), we need PUF designs which constitute of a "algebraic" composition of smaller basic building blocks/devices. In such compositions the security relies on a less well-established computational hardness assumption which states that machine learning and other modeling methods with poly(λ) runtime cannot reliably produce a software clone of the PUF. To provide rigorous security we argue that the PUF interface needs a one-way postprocessing of PUF responses such that the security can be reduced to the infeasibility of breaking the one-way property of the postprocessing. This leads to a set of interesting problems: how do we add noise reduction into this picture and how do we minimize or eliminate side channel leakage of computed intermediate values in the post processing?
{"title":"PUF Interfaces and their Security","authors":"Marten van Dijk, U. Rührmair","doi":"10.1109/ISVLSI.2014.90","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.90","url":null,"abstract":"In practice, any integrated physical unclonable function (PUF) must be accessed through a logical interface. The interface may add additional functionalities such as access control, implement a (measurement) noise reduction layer, etc. In many PUF applications, the interface in fact hides the PUF itself: users only interact with the PUF's interface, and cannot \"see\" or verify what is behind the interface. This immediately gives rise to a security problem: how does the user know he is interacting with a properly behaving interface wrapped around a proper PUF? This question is not merely theoretical, but has strong relevance for PUF application security: It has been shown recently that a badly behaving interface could, e.g., log a history of PUF queries which an adversary can read out using some trapdoor, or may output \"false\" PUF responses that the adversary can predict or influence RvD-IEEESP13. This allows attacks on a considerable number of PUF protocols RvD-IEEESP13. Since we currently do not know how to authenticate proper interface behavior in practice, the security of many PUF applications implicitly rests on the mere assumption that an adversary cannot modify or enhance a PUF interface in a \"bad\" way. This is quite a strong hypothesis, which should be stated more explicitly in the literature. In this paper, we explicitly address this point, following and partly expanding earlier works RvD-IEEESP13. We add to the picture the need for rigorous security which is characterized by some security parameter λ (an adversary has \"negl(λ) probability to successfully software clone/model a PUF\"). First, this means that we need so-called Strong PUFs with a larger than poly(λ) input/challenge space. In order to have scalable PUF designs (which do not blow up in chip surface or volume for increasing λ), we need PUF designs which constitute of a \"algebraic\" composition of smaller basic building blocks/devices. In such compositions the security relies on a less well-established computational hardness assumption which states that machine learning and other modeling methods with poly(λ) runtime cannot reliably produce a software clone of the PUF. To provide rigorous security we argue that the PUF interface needs a one-way postprocessing of PUF responses such that the security can be reduced to the infeasibility of breaking the one-way property of the postprocessing. This leads to a set of interesting problems: how do we add noise reduction into this picture and how do we minimize or eliminate side channel leakage of computed intermediate values in the post processing?","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127835088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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