Multi-mode and multi-standard connectivity has become a necessity for portable communication systems. A convenient architectural solution is to build flexible systems that can be reprogrammed to meet requirements of multiple standards. One of the major issues in this context is the resource overhead required by programmability. In particular, in the latest VLSI technology nodes, energy consumption has become a very severe problem, greatly impacting the reliability of the hardware. Therefore, any design aimed at the implementation of multi-mode multi-standard communication systems must be strictly targeted at the lowest power consumption without jeopardizing peak performance, while, at the same time, retaining a high degree of flexibility. This work presents the design and implementation of a (auto)correlator block for timing synchronization. The design is composed of a scalable computational unit, which allows to meet real-time requirements of different wireless communication standards (e.g. W-CDMA, IEEE 802.11a/g/n). Moreover, dynamic power management allows to dynamically trade-off energy consumption versus performance, adapting power dissipation to the specific requirements of each supported standard, as well as to follow dynamic variations of the computation load.
{"title":"Design of a Flexible, Energy Efficient (Auto)Correlator Block for Timing Synchronization","authors":"F. Campi, Roberto Airoldi, J. Nurmi","doi":"10.1109/ISVLSI.2014.27","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.27","url":null,"abstract":"Multi-mode and multi-standard connectivity has become a necessity for portable communication systems. A convenient architectural solution is to build flexible systems that can be reprogrammed to meet requirements of multiple standards. One of the major issues in this context is the resource overhead required by programmability. In particular, in the latest VLSI technology nodes, energy consumption has become a very severe problem, greatly impacting the reliability of the hardware. Therefore, any design aimed at the implementation of multi-mode multi-standard communication systems must be strictly targeted at the lowest power consumption without jeopardizing peak performance, while, at the same time, retaining a high degree of flexibility. This work presents the design and implementation of a (auto)correlator block for timing synchronization. The design is composed of a scalable computational unit, which allows to meet real-time requirements of different wireless communication standards (e.g. W-CDMA, IEEE 802.11a/g/n). Moreover, dynamic power management allows to dynamically trade-off energy consumption versus performance, adapting power dissipation to the specific requirements of each supported standard, as well as to follow dynamic variations of the computation load.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"455 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131856026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Asokan, A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel
Ongoing technology scaling has increased delay defects in integrated circuits. Some of the delay defects are due to crosstalk, supply noise, process variations, etc. They degrade the performance and field reliability of circuits. However, testing the circuits with path delay patterns under worst-case conditions helps to detect such defects. Estimation of patterns with worst-case path delay becomes difficult using the conventional techniques due to their unpredictable behavior. In this paper, we first describe the problem and then propose our approach in identifying a worst-case path delay pattern under the impact of process variations and supply noise. A delay probability metric ispresented in this work, for an efficient identification of worst-case path delay pattern, which is the basis of our ranking method. The simulation results of ITC'99 benchmark circuits show the feasibility of our delay probability metric.
{"title":"A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise","authors":"A. Asokan, A. Todri, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel","doi":"10.1109/ISVLSI.2014.42","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.42","url":null,"abstract":"Ongoing technology scaling has increased delay defects in integrated circuits. Some of the delay defects are due to crosstalk, supply noise, process variations, etc. They degrade the performance and field reliability of circuits. However, testing the circuits with path delay patterns under worst-case conditions helps to detect such defects. Estimation of patterns with worst-case path delay becomes difficult using the conventional techniques due to their unpredictable behavior. In this paper, we first describe the problem and then propose our approach in identifying a worst-case path delay pattern under the impact of process variations and supply noise. A delay probability metric ispresented in this work, for an efficient identification of worst-case path delay pattern, which is the basis of our ranking method. The simulation results of ITC'99 benchmark circuits show the feasibility of our delay probability metric.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123445666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes a method to derive a polynomial function computed by an arithmetic bit-level circuit. The circuit is modeled as a bit-level network composed of adders and logic gates and computation performed by the circuit is viewed as a flow of binary data through the network. The problem is cast as a Network Flow problem and solved using standard algebraic techniques. Extraction of the arithmetic function from the circuit is accomplished by transforming the expression at the primary outputs into an expression at the primary inputs. Experimental results show application of the method to certain classes of large arithmetic circuits.
{"title":"Function Extraction from Arithmetic Bit-Level Circuits","authors":"M. Ciesielski, W. Brown, Duo Liu, A. Rossi","doi":"10.1109/ISVLSI.2014.43","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.43","url":null,"abstract":"The paper describes a method to derive a polynomial function computed by an arithmetic bit-level circuit. The circuit is modeled as a bit-level network composed of adders and logic gates and computation performed by the circuit is viewed as a flow of binary data through the network. The problem is cast as a Network Flow problem and solved using standard algebraic techniques. Extraction of the arithmetic function from the circuit is accomplished by transforming the expression at the primary outputs into an expression at the primary inputs. Experimental results show application of the method to certain classes of large arithmetic circuits.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124040350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As silicon-based technology feature sizes continue to decrease and designs remain susceptible to novel attacks designers face competing goals when creating secure, low power, integrated circuits (ICs). Often, low power designs rely on heavy minimization and optimization procedures while many secure designs use low-level duplication mechanisms to thwart attacks. An area that requires special attention, and is crucial in both realms, is the power consumption profile of Finite State Machines (FSM). This work specifically addresses the key concern of creating secure, low-power, FSM encodings. This work details a flexible, secure, encoding strategy which, in conjunction with security-based structural modifications, can provide low-power security solutions against side channel attacks. The secure encoding strategy includes methods that modify the original constraints in order to provide varying levels of protection that approach traditional low power encoding methods. Specifically, this work uses the MCNC benchmark suite to compare the state space and encoding requirement for secure (70% increase) and relaxed encoding methods (53-67% increase) aimed at increasing overall device security while reducing state-state transition cost (Npeak = 2).
{"title":"Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements","authors":"M. Borowczak, R. Vemuri","doi":"10.1109/ISVLSI.2014.78","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.78","url":null,"abstract":"As silicon-based technology feature sizes continue to decrease and designs remain susceptible to novel attacks designers face competing goals when creating secure, low power, integrated circuits (ICs). Often, low power designs rely on heavy minimization and optimization procedures while many secure designs use low-level duplication mechanisms to thwart attacks. An area that requires special attention, and is crucial in both realms, is the power consumption profile of Finite State Machines (FSM). This work specifically addresses the key concern of creating secure, low-power, FSM encodings. This work details a flexible, secure, encoding strategy which, in conjunction with security-based structural modifications, can provide low-power security solutions against side channel attacks. The secure encoding strategy includes methods that modify the original constraints in order to provide varying levels of protection that approach traditional low power encoding methods. Specifically, this work uses the MCNC benchmark suite to compare the state space and encoding requirement for secure (70% increase) and relaxed encoding methods (53-67% increase) aimed at increasing overall device security while reducing state-state transition cost (Npeak = 2).","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127534418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a novel class of linear soft-input soft-output detectors with boosted communications performance. The detector showed an SNR gain of up to 2.4 dB compared to state-of-the-art linear detectors. We introduce a low-complexity algorithm tailored for VLSI implementation, and propose a suitable architecture. The developed ASIC demonstrates the feasibility and efficiency of the concept, achieving the IEEE 802.11n standard's peak data rate of 600 Mbit/s.
{"title":"A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture","authors":"Dominik Auras, R. Leupers, G. Ascheid","doi":"10.1109/ISVLSI.2014.16","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.16","url":null,"abstract":"This paper introduces a novel class of linear soft-input soft-output detectors with boosted communications performance. The detector showed an SNR gain of up to 2.4 dB compared to state-of-the-art linear detectors. We introduce a low-complexity algorithm tailored for VLSI implementation, and propose a suitable architecture. The developed ASIC demonstrates the feasibility and efficiency of the concept, achieving the IEEE 802.11n standard's peak data rate of 600 Mbit/s.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130598355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Process variation is a major limiting factor in designing high performance circuits in advanced CMOS technologies. Over optimizing data paths to provide adequate design margin is leading to increased area and power overhead. In this work, we present a variation aware design of Post-Silicon Tunable (PST) clock buffers to redistribute clock skew and mitigate impact of process variation on chip performance. Conventional PST buffers are designed for linear delay values. We estimate a set of non-linear delay intervals of PST buffer based on slack variation in each critical path. The configuration device sizes are mapped to the non-linear delay intervals using a set of equality conditions and solved using Linear Programming (LP). The variation aware device sizing provides many small delay intervals within one standard deviation of slack distribution and fewer large delay intervals to compensate for larger slack variations. This helps in optimal tuning of PST buffers to fix hold time, as well as better skew distribution to achieve maximum possible performance in a chip. The proposed PST buffer design technique was implemented for ISCAS'89 benchmark circuits. Non-linear delay PST buffers improve performance binning yield by more than 4%. They also provide optimum buffer circuits with an area reduction of 30% and leakage power reduction of 20%. The proposed technique can be implemented by designing dedicated buffers for each critical path or using a smaller set of pre-designed buffers with non-linear delay values.
{"title":"Variation Aware Design of Post-Silicon Tunable Clock Buffer","authors":"Vikram B. Suresh, W. Burleson","doi":"10.1109/ISVLSI.2014.95","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.95","url":null,"abstract":"Process variation is a major limiting factor in designing high performance circuits in advanced CMOS technologies. Over optimizing data paths to provide adequate design margin is leading to increased area and power overhead. In this work, we present a variation aware design of Post-Silicon Tunable (PST) clock buffers to redistribute clock skew and mitigate impact of process variation on chip performance. Conventional PST buffers are designed for linear delay values. We estimate a set of non-linear delay intervals of PST buffer based on slack variation in each critical path. The configuration device sizes are mapped to the non-linear delay intervals using a set of equality conditions and solved using Linear Programming (LP). The variation aware device sizing provides many small delay intervals within one standard deviation of slack distribution and fewer large delay intervals to compensate for larger slack variations. This helps in optimal tuning of PST buffers to fix hold time, as well as better skew distribution to achieve maximum possible performance in a chip. The proposed PST buffer design technique was implemented for ISCAS'89 benchmark circuits. Non-linear delay PST buffers improve performance binning yield by more than 4%. They also provide optimum buffer circuits with an area reduction of 30% and leakage power reduction of 20%. The proposed technique can be implemented by designing dedicated buffers for each critical path or using a smaller set of pre-designed buffers with non-linear delay values.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132896849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A subclass of efficient simulation-based sequential test generation procedures are guided by information about primary input values that effective test subsequences should use. This information is represented by a primary input cube c. In all the earlier procedures that are based on this concept, the computation of c is fault-independent. This paper introduces an approach for a fault-dependent computation of c. This allows the test generation procedure to generate test subsequences that match the detection conditions of specific faults, thus increasing the fault coverage that it can achieve. The computation of the primary input cube c for a fault f is based on a process that unspecifies a primary input subsequence, which does not detect f, in order to identify values that need to be avoided in a test subsequence for f. These values are used in the construction of c for f. The paper also discusses the applicability of the fault-dependent primary input cubes to the built-in generation of functional broadside tests.
{"title":"FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input Cubes","authors":"I. Pomeranz","doi":"10.1109/ISVLSI.2014.23","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.23","url":null,"abstract":"A subclass of efficient simulation-based sequential test generation procedures are guided by information about primary input values that effective test subsequences should use. This information is represented by a primary input cube c. In all the earlier procedures that are based on this concept, the computation of c is fault-independent. This paper introduces an approach for a fault-dependent computation of c. This allows the test generation procedure to generate test subsequences that match the detection conditions of specific faults, thus increasing the fault coverage that it can achieve. The computation of the primary input cube c for a fault f is based on a process that unspecifies a primary input subsequence, which does not detect f, in order to identify values that need to be avoided in a test subsequence for f. These values are used in the construction of c for f. The paper also discusses the applicability of the fault-dependent primary input cubes to the built-in generation of functional broadside tests.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116138790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Firouzi, Fangming Ye, K. Chakrabarty, M. Tahoori
In nanoscale technology nodes, process and runtime variations have emerged as the major sources of timing uncertainties which may ultimately result in circuit failure due to timing violation. Therefore, in-field chip health monitoring is essential to track workload-induced variations at runtime in a per-chip basis. There exist a variety of monitoring circuits to track the delay changes of different on-chip components. However, existing techniques either need to stop normal execution of the chip or introduce a significant overhead unless they are carefully placed for very selective locations. Another challenge is to infer the information regarding the health of every critical paths of the chip with limited information obtained by the monitoring system. We address these challenges in this work using a representative path-selection technique based on machine learning. This technique allows us to measure the delay of a small subset of paths and assess the circuit-level impact of workload for a larger pool of reliability-critical paths.
{"title":"Chip Health Monitoring Using Machine Learning","authors":"F. Firouzi, Fangming Ye, K. Chakrabarty, M. Tahoori","doi":"10.1109/ISVLSI.2014.119","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.119","url":null,"abstract":"In nanoscale technology nodes, process and runtime variations have emerged as the major sources of timing uncertainties which may ultimately result in circuit failure due to timing violation. Therefore, in-field chip health monitoring is essential to track workload-induced variations at runtime in a per-chip basis. There exist a variety of monitoring circuits to track the delay changes of different on-chip components. However, existing techniques either need to stop normal execution of the chip or introduce a significant overhead unless they are carefully placed for very selective locations. Another challenge is to infer the information regarding the health of every critical paths of the chip with limited information obtained by the monitoring system. We address these challenges in this work using a representative path-selection technique based on machine learning. This technique allows us to measure the delay of a small subset of paths and assess the circuit-level impact of workload for a larger pool of reliability-critical paths.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Karim Kanoun, M. Ruggiero, David Atienza Alonso, M. Schaar
In the last years the process of examining large amounts of different types of data, or Big-Data, in an effort to uncover hidden patterns or unknown correlations has become a major need in our society. In this context, stream mining applications are now widely used in several domains such as financial analysis, video annotation, surveillance, medical services, traffic prediction, etc. In order to cope with the Big-Data stream input and its high variability, modern stream mining applications implement systems with heterogeneous classifiers and adapt online to its input data stream characteristics variation. Moreover, unlike existing architectures for video processing and compression applications, where the processing units are reconfigurable in terms of parameters and possibly even functions as the input data is changing, in Big-Data stream mining applications the complete computing pipeline is changing, as entirely new classifiers and processing functions are invoked depending on the input stream. As a result, new approaches of reconfigurable hardware platform architectures are needed to handle Big-Data streams. However, hardware solutions that have been proposed so far for stream mining applications either target high performance computing without any power consideration (i.e., limiting their applicability in small-scale computing infrastructures or current embedded systems), or they are simply dedicated to a specific learning algorithm (i.e., limited to run with a single type of classifiers). Therefore, in this paper we propose a novel low-power many-core architecture for stream mining applications that is able to cope with the dynamic data-driven nature of stream mining applications while consuming limited power. Our exploration indicates that this new proposed architecture is able to adapt to different classifiers complexities thanks to its multiple scalable vector processing units and their re-configurability feature at run-time. Moreover, our platform architecture includes a memory hierarchy optimized for Big-Data streaming and implements modern fine-grained power management techniques over all the different types of cores allowing then minimum energy consumption for each type of executed classifier.
{"title":"Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing","authors":"Karim Kanoun, M. Ruggiero, David Atienza Alonso, M. Schaar","doi":"10.1109/ISVLSI.2014.77","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.77","url":null,"abstract":"In the last years the process of examining large amounts of different types of data, or Big-Data, in an effort to uncover hidden patterns or unknown correlations has become a major need in our society. In this context, stream mining applications are now widely used in several domains such as financial analysis, video annotation, surveillance, medical services, traffic prediction, etc. In order to cope with the Big-Data stream input and its high variability, modern stream mining applications implement systems with heterogeneous classifiers and adapt online to its input data stream characteristics variation. Moreover, unlike existing architectures for video processing and compression applications, where the processing units are reconfigurable in terms of parameters and possibly even functions as the input data is changing, in Big-Data stream mining applications the complete computing pipeline is changing, as entirely new classifiers and processing functions are invoked depending on the input stream. As a result, new approaches of reconfigurable hardware platform architectures are needed to handle Big-Data streams. However, hardware solutions that have been proposed so far for stream mining applications either target high performance computing without any power consideration (i.e., limiting their applicability in small-scale computing infrastructures or current embedded systems), or they are simply dedicated to a specific learning algorithm (i.e., limited to run with a single type of classifiers). Therefore, in this paper we propose a novel low-power many-core architecture for stream mining applications that is able to cope with the dynamic data-driven nature of stream mining applications while consuming limited power. Our exploration indicates that this new proposed architecture is able to adapt to different classifiers complexities thanks to its multiple scalable vector processing units and their re-configurability feature at run-time. Moreover, our platform architecture includes a memory hierarchy optimized for Big-Data streaming and implements modern fine-grained power management techniques over all the different types of cores allowing then minimum energy consumption for each type of executed classifier.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132370728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three-dimensional (3D) SoC is becoming one of the most promising approaches for extending Moore's Law. However, managing test optimized scheme to reduce the cost of 3D SoCs is a significant challenge. In this paper, we propose a cost-effective optimized scheme of 3D SoCs for pre-bond test based on a generic cost model we defined. Both test time and number of TSV are considered in our novel scheme. Experimental results on ITC'02 SoC benchmark circuits show that our scheme is superior to one baseline solution and can effectively achieve good performance on test optimization.
{"title":"Cost-Effective Test Optimized Scheme of TSV-Based 3D SoCs for Pre-Bond Test","authors":"Kele Shen, D. Xiang, Z. Jiang","doi":"10.1109/ISVLSI.2014.57","DOIUrl":"https://doi.org/10.1109/ISVLSI.2014.57","url":null,"abstract":"Three-dimensional (3D) SoC is becoming one of the most promising approaches for extending Moore's Law. However, managing test optimized scheme to reduce the cost of 3D SoCs is a significant challenge. In this paper, we propose a cost-effective optimized scheme of 3D SoCs for pre-bond test based on a generic cost model we defined. Both test time and number of TSV are considered in our novel scheme. Experimental results on ITC'02 SoC benchmark circuits show that our scheme is superior to one baseline solution and can effectively achieve good performance on test optimization.","PeriodicalId":405755,"journal":{"name":"2014 IEEE Computer Society Annual Symposium on VLSI","volume":"323 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113985522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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