Pub Date : 2016-10-01DOI: 10.1109/ICCCCM.2016.7918225
Aman Nag, Divesh Mittal, Avneet Kaur, Ekambir Sidhu
In this paper, the design and performance analysis of dual circular stacked microstrip patch antenna for S-band applications has been proposed. In the proposed antenna design, the substrate of material FR 4 having dielectric constant 4.4 have been used. The ground, patch and feedline are of copper material. The proposed antenna has two circular stackings on the patch and the antenna has impedance bandwidth of 110 MHz with operating frequency ranging from 3.34 GHz to 3.45 GHz. In the proposed antenna design, the stacking has been employed to enhance the directivity and return loss. The proposed antenna design has been fed by microstrip feedline having impedance of 49.36 Ω. The performance of antenna has been analyzed in terms of return loss (dB), impedance bandwidth (MHz), directivity (dBi), gain (dB), VSWR and impedance (ohms). The proposed antenna design resonates at 3.40 GHz frequency with minimum return loss of −41.55 dB, gain of 4.45 dB and directivity of 6.47 dBi. The proposed antenna can be used for S-band (2GHz–4 GHz) applications. The proposed antenna has been designed and simulated using CST Microwave Studio 2014. The proposed antenna has been successfully fabricated and tested using E5071C network analyzer and anechoic chamber. It has been observed that the CST simulated antenna results closely match with the practically fabricated results of the proposed antenna.
{"title":"Novel dual circular stacked microstrip patch antenna design for S-band UWB applications","authors":"Aman Nag, Divesh Mittal, Avneet Kaur, Ekambir Sidhu","doi":"10.1109/ICCCCM.2016.7918225","DOIUrl":"https://doi.org/10.1109/ICCCCM.2016.7918225","url":null,"abstract":"In this paper, the design and performance analysis of dual circular stacked microstrip patch antenna for S-band applications has been proposed. In the proposed antenna design, the substrate of material FR 4 having dielectric constant 4.4 have been used. The ground, patch and feedline are of copper material. The proposed antenna has two circular stackings on the patch and the antenna has impedance bandwidth of 110 MHz with operating frequency ranging from 3.34 GHz to 3.45 GHz. In the proposed antenna design, the stacking has been employed to enhance the directivity and return loss. The proposed antenna design has been fed by microstrip feedline having impedance of 49.36 Ω. The performance of antenna has been analyzed in terms of return loss (dB), impedance bandwidth (MHz), directivity (dBi), gain (dB), VSWR and impedance (ohms). The proposed antenna design resonates at 3.40 GHz frequency with minimum return loss of −41.55 dB, gain of 4.45 dB and directivity of 6.47 dBi. The proposed antenna can be used for S-band (2GHz–4 GHz) applications. The proposed antenna has been designed and simulated using CST Microwave Studio 2014. The proposed antenna has been successfully fabricated and tested using E5071C network analyzer and anechoic chamber. It has been observed that the CST simulated antenna results closely match with the practically fabricated results of the proposed antenna.","PeriodicalId":410488,"journal":{"name":"2016 International Conference on Control, Computing, Communication and Materials (ICCCCM)","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116066194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ICCCCM.2016.7918267
Kamta Nath Mishra
In voting based approach a process getting the majority of votes will only be allowed to enter into the critical section (CS). But, this method has a disadvantage as if no process remains in the situation of achieving majority of votes then the system will remain in idle state although a considerable amount of minority processes will remain in waiting queue. In order to solve the concurrency and starvation control problems of distributed systems, the voting and priority based optimal & feasible solution is presented in this research work. In the prioritized distributed mutual exclusion based algorithm, the process having highest priority amongst all the processes of distributed system is allowed to enter into the critical section (CS). Hence, leaving the other lower priority processes into the waiting queue which results an increase in the length of waiting queue. By keeping these mentioned reasons into considerations I have proposed a new algorithm which can provide a solution for voting and priority based algorithms. Here, I have presented a combined solution for voting and priority based approaches by including some other constraints like treatment for ‘non-maskable interrupts’ and ‘Shortest Job Scheduling First (SJSF)’ techniques. The proposed technique allows the creation of multiple critical sections in a distributed system and prevents the processors from entering into idle state which leads towards increase in throughput.
{"title":"An efficient voting and priority based mechanism for deadlock prevention in distributed systems","authors":"Kamta Nath Mishra","doi":"10.1109/ICCCCM.2016.7918267","DOIUrl":"https://doi.org/10.1109/ICCCCM.2016.7918267","url":null,"abstract":"In voting based approach a process getting the majority of votes will only be allowed to enter into the critical section (CS). But, this method has a disadvantage as if no process remains in the situation of achieving majority of votes then the system will remain in idle state although a considerable amount of minority processes will remain in waiting queue. In order to solve the concurrency and starvation control problems of distributed systems, the voting and priority based optimal & feasible solution is presented in this research work. In the prioritized distributed mutual exclusion based algorithm, the process having highest priority amongst all the processes of distributed system is allowed to enter into the critical section (CS). Hence, leaving the other lower priority processes into the waiting queue which results an increase in the length of waiting queue. By keeping these mentioned reasons into considerations I have proposed a new algorithm which can provide a solution for voting and priority based algorithms. Here, I have presented a combined solution for voting and priority based approaches by including some other constraints like treatment for ‘non-maskable interrupts’ and ‘Shortest Job Scheduling First (SJSF)’ techniques. The proposed technique allows the creation of multiple critical sections in a distributed system and prevents the processors from entering into idle state which leads towards increase in throughput.","PeriodicalId":410488,"journal":{"name":"2016 International Conference on Control, Computing, Communication and Materials (ICCCCM)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128415045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ICCCCM.2016.7918239
Anurag S. D. Rai, B. Awasthi, A. Dixit, C. Dwivedi
Solar Photovoltaic cell is the smallest unit of solar photovoltaic power system, it converts light energy in to electrical energy. The phenomenon of this conversion of light energy into electrical energy is termed as Photovoltaic effect. The aim of this study is to develop a model for photovoltaic module based on mathematical expression. The conventional single diode model for solar cell with series and shunt resistance is used for illustration. The effect of change in environmental condition like irradiance and temperature on output of photovoltaic module is shown, the effect of physical parameter variation such as shunt and series resistance is also consider. The characteristic of proposed model is compared with the reference photovoltaic module. The 250 watt photovoltaic module manufactured by Tata solar power is used as reference. The large solar array system can be modeled and simulate using this model. Simulation was performed at any and all step using MATLAB/ Simulink software.
{"title":"Modeling of solar photovoltaic module and study parameter variation effect using MATLAB/Simulink","authors":"Anurag S. D. Rai, B. Awasthi, A. Dixit, C. Dwivedi","doi":"10.1109/ICCCCM.2016.7918239","DOIUrl":"https://doi.org/10.1109/ICCCCM.2016.7918239","url":null,"abstract":"Solar Photovoltaic cell is the smallest unit of solar photovoltaic power system, it converts light energy in to electrical energy. The phenomenon of this conversion of light energy into electrical energy is termed as Photovoltaic effect. The aim of this study is to develop a model for photovoltaic module based on mathematical expression. The conventional single diode model for solar cell with series and shunt resistance is used for illustration. The effect of change in environmental condition like irradiance and temperature on output of photovoltaic module is shown, the effect of physical parameter variation such as shunt and series resistance is also consider. The characteristic of proposed model is compared with the reference photovoltaic module. The 250 watt photovoltaic module manufactured by Tata solar power is used as reference. The large solar array system can be modeled and simulate using this model. Simulation was performed at any and all step using MATLAB/ Simulink software.","PeriodicalId":410488,"journal":{"name":"2016 International Conference on Control, Computing, Communication and Materials (ICCCCM)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117042943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ICCCCM.2016.7918218
A. Anilkumar, N. Srikanth
This paper addresses adaptive fuzzy logic controller for load frequency control of a multi-source two area power system with different power generation sources viz hydro gas & thermal power plant. Expert knowledge is required for conventional fuzzy logic control in developing parameters. Whereas in this method rules are tuned online by adaptation algorithm according to operating condition. The robustness of adaptive fuzzy logic controller has been shown by comparing with conventional fuzzy logic controller and integral controller. The comparison is done based on various performance indices like settling times and peak overshoots for 1 percent step load perturbation.
{"title":"Load frequency control for diverse sources of interconnected two area power system: An adaptive fuzzy approach","authors":"A. Anilkumar, N. Srikanth","doi":"10.1109/ICCCCM.2016.7918218","DOIUrl":"https://doi.org/10.1109/ICCCCM.2016.7918218","url":null,"abstract":"This paper addresses adaptive fuzzy logic controller for load frequency control of a multi-source two area power system with different power generation sources viz hydro gas & thermal power plant. Expert knowledge is required for conventional fuzzy logic control in developing parameters. Whereas in this method rules are tuned online by adaptation algorithm according to operating condition. The robustness of adaptive fuzzy logic controller has been shown by comparing with conventional fuzzy logic controller and integral controller. The comparison is done based on various performance indices like settling times and peak overshoots for 1 percent step load perturbation.","PeriodicalId":410488,"journal":{"name":"2016 International Conference on Control, Computing, Communication and Materials (ICCCCM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128831960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/ICCCCM.2016.7918263
S. Archana, Sujatha Hiremath, B. P. Kumar, C. Ananda
Most of the systems rely on Fiber Channel link to stream large volumes of varied data at high speed and low latency. Due to the critical nature of these systems, verifying the data flow in the network is vital and hence avoiding transfer of deluding or false data that may prompt hazardous conditions in the system. This paper describes a design for a custom made protocol analyzer that receives, decodes, displays and validates the data transmission over the Fiber Channel. The protocol analyzer consists of a receiver block implemented on Xilinx Spartan 6 board which is interfaced to a customised GUI implemented on a Host PC on windows platform. As a case study, the paper describes the application of the proposed analyzer system with Avionics Digital Video Bus (ADVB) protocol that transmits video data with a video resolution of 1400×1050 (SXGA+) RGB at a standard link rate of 3.1875Gbps. At an instance the analyzer can capture and analyse a defined length of data in ADVB frame. The results of case study show the detailed data types and error status of each decoded ADVB frame.
{"title":"Design and implementation of fiber channel data analyzer","authors":"S. Archana, Sujatha Hiremath, B. P. Kumar, C. Ananda","doi":"10.1109/ICCCCM.2016.7918263","DOIUrl":"https://doi.org/10.1109/ICCCCM.2016.7918263","url":null,"abstract":"Most of the systems rely on Fiber Channel link to stream large volumes of varied data at high speed and low latency. Due to the critical nature of these systems, verifying the data flow in the network is vital and hence avoiding transfer of deluding or false data that may prompt hazardous conditions in the system. This paper describes a design for a custom made protocol analyzer that receives, decodes, displays and validates the data transmission over the Fiber Channel. The protocol analyzer consists of a receiver block implemented on Xilinx Spartan 6 board which is interfaced to a customised GUI implemented on a Host PC on windows platform. As a case study, the paper describes the application of the proposed analyzer system with Avionics Digital Video Bus (ADVB) protocol that transmits video data with a video resolution of 1400×1050 (SXGA+) RGB at a standard link rate of 3.1875Gbps. At an instance the analyzer can capture and analyse a defined length of data in ADVB frame. The results of case study show the detailed data types and error status of each decoded ADVB frame.","PeriodicalId":410488,"journal":{"name":"2016 International Conference on Control, Computing, Communication and Materials (ICCCCM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127352863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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