Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962345
J. Wen, Andrea Baroni, E. Pérez, Markus Ulbricht, C. Wenger, M. Krstic
RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel conductance states and input voltages. Device-to-device variability is also taken into consideration to assess the accuracy drop. Two convolutional neural networks, LeNet-5 and VGG-7, are benchmarked with MNIST and CIFAR-10 datasets, respectively. Our results show that mapping weights with differential pairs yields better robustness to read disturb and variability effects.
{"title":"Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages","authors":"J. Wen, Andrea Baroni, E. Pérez, Markus Ulbricht, C. Wenger, M. Krstic","doi":"10.1109/DFT56152.2022.9962345","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962345","url":null,"abstract":"RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel conductance states and input voltages. Device-to-device variability is also taken into consideration to assess the accuracy drop. Two convolutional neural networks, LeNet-5 and VGG-7, are benchmarked with MNIST and CIFAR-10 datasets, respectively. Our results show that mapping weights with differential pairs yields better robustness to read disturb and variability effects.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962355
Anmol Singh Narwariya, Pabitra Das, S. Khursheed, A. Acharyya
Electronic systems life is an essential aspect of ensuring reliability and safety. An accurate age estimation could assimilate, which is helpful for any electronics system. It would also positively impact the minimisation of electronics waste and support the endeavour of green computing. In this paper, we propose a methodology for age estimation using the Gaussian Process Regression (GPR) model. Our methodology requires an RO sensor, temperature sensor, and trained GPR model for the age prediction. The Ring Oscillator (RO) output frequency relies on the trackable path, temperature, voltage and ageing. These dependencies are utilized for the training of the GPR model. We exhibit the output frequency degradation of the ring oscillator through the Synopsys PrimeSim Hspice tool with the 32nm Predictive Technology Model (PTM). We consider variations from 0 °C to 100 °C in temperature and 0. 8V to 1. 05V in the voltage. Our methodology predicts age precisely, showing average prediction accuracy in 85.35% cases with a deviation of one month for 13-stage RO and 90.42% cases in 21-stage RO. Our proposed methodology is more accurate than the state-of-the-art techniques in terms of prediction accuracy as well as age estimation deviation. The prediction accuracy improvement got 9.59% for 13-stage and 9.17% for 21-stage RO on our dataset than the state-of-the-art technique with a month deviation, respectively, as opposed to 2.4 months for the state-of-the-art method.
{"title":"Operational Age Estimation of ICs using Gaussian Process Regression","authors":"Anmol Singh Narwariya, Pabitra Das, S. Khursheed, A. Acharyya","doi":"10.1109/DFT56152.2022.9962355","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962355","url":null,"abstract":"Electronic systems life is an essential aspect of ensuring reliability and safety. An accurate age estimation could assimilate, which is helpful for any electronics system. It would also positively impact the minimisation of electronics waste and support the endeavour of green computing. In this paper, we propose a methodology for age estimation using the Gaussian Process Regression (GPR) model. Our methodology requires an RO sensor, temperature sensor, and trained GPR model for the age prediction. The Ring Oscillator (RO) output frequency relies on the trackable path, temperature, voltage and ageing. These dependencies are utilized for the training of the GPR model. We exhibit the output frequency degradation of the ring oscillator through the Synopsys PrimeSim Hspice tool with the 32nm Predictive Technology Model (PTM). We consider variations from 0 °C to 100 °C in temperature and 0. 8V to 1. 05V in the voltage. Our methodology predicts age precisely, showing average prediction accuracy in 85.35% cases with a deviation of one month for 13-stage RO and 90.42% cases in 21-stage RO. Our proposed methodology is more accurate than the state-of-the-art techniques in terms of prediction accuracy as well as age estimation deviation. The prediction accuracy improvement got 9.59% for 13-stage and 9.17% for 21-stage RO on our dataset than the state-of-the-art technique with a month deviation, respectively, as opposed to 2.4 months for the state-of-the-art method.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133958558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962368
G. Chapman, Klinsmann J. Coelho Silva Meneses, I. Koren, Z. Koren
Hot Pixels are cosmic ray induced digital imaging sensor defects that accumulate as the camera ages at rates that are highly dependent on pixel size. We previously developed an empirical formula projecting hot pixel defect density (defects/year/mm2) growth rates via a power law, with the inverse of the pixel size raised to the power of $sim $3, multiplied by the square root of the ISO (gain). We show in this paper that this increasing defect rate results in a higher probability that two defects will occur within a 5x5 pixel square. Under these conditions, the color demosaicing and JPEG image compression algorithms required for picture creation greatly amplify the impact of these two defective pixels, spreading damage to a 16x16 pixel area and creating significant color changes resulting in a very noticeable image degradation. We develop an analytical generalized birthday problem formula in order to estimate the number of hot pixels needed to achieve a given probability of having two defective pixels within a 5x5 square. For a 20 Mpixel DSLR camera, only 128 hot pixels generate a 4.5% probability of such interacting defective pixels, or 1 in 22 cameras. For 4 micron pixels this would occur in 1.4 years at ISO 6400, and in 3.2 years at ISO 3200.
{"title":"Image Degradation due to Interacting Adjacent Hot Pixels","authors":"G. Chapman, Klinsmann J. Coelho Silva Meneses, I. Koren, Z. Koren","doi":"10.1109/DFT56152.2022.9962368","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962368","url":null,"abstract":"Hot Pixels are cosmic ray induced digital imaging sensor defects that accumulate as the camera ages at rates that are highly dependent on pixel size. We previously developed an empirical formula projecting hot pixel defect density (defects/year/mm2) growth rates via a power law, with the inverse of the pixel size raised to the power of $sim $3, multiplied by the square root of the ISO (gain). We show in this paper that this increasing defect rate results in a higher probability that two defects will occur within a 5x5 pixel square. Under these conditions, the color demosaicing and JPEG image compression algorithms required for picture creation greatly amplify the impact of these two defective pixels, spreading damage to a 16x16 pixel area and creating significant color changes resulting in a very noticeable image degradation. We develop an analytical generalized birthday problem formula in order to estimate the number of hot pixels needed to achieve a given probability of having two defective pixels within a 5x5 square. For a 20 Mpixel DSLR camera, only 128 hot pixels generate a 4.5% probability of such interacting defective pixels, or 1 in 22 cameras. For 4 micron pixels this would occur in 1.4 years at ISO 6400, and in 3.2 years at ISO 3200.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114985663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962354
Stéphane Burel, A. Evans, L. Anghel
Semantic segmentation of images is essential for autonomous driving and modern DNNs now achieve high accuracy. Automotive systems must comply with safety standards, requiring hardware fault detection. We present an analysis of the effect of faults using Google’s DeepLabV3+ network processing an industrial data-set. A new symptom-based fault detection algorithm is shown to detect >99% of critical faults with zero false positives and a compute overhead of 0.2%. Further, these faults can be masked, virtually eliminating all critical errors. To the authors’ knowledge this is the first fault tolerance study of a DNN semantic segmentation application.
{"title":"Improving DNN Fault Tolerance in Semantic Segmentation Applications","authors":"Stéphane Burel, A. Evans, L. Anghel","doi":"10.1109/DFT56152.2022.9962354","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962354","url":null,"abstract":"Semantic segmentation of images is essential for autonomous driving and modern DNNs now achieve high accuracy. Automotive systems must comply with safety standards, requiring hardware fault detection. We present an analysis of the effect of faults using Google’s DeepLabV3+ network processing an industrial data-set. A new symptom-based fault detection algorithm is shown to detect >99% of critical faults with zero false positives and a compute overhead of 0.2%. Further, these faults can be masked, virtually eliminating all critical errors. To the authors’ knowledge this is the first fault tolerance study of a DNN semantic segmentation application.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125363054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attack, however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at gate level. In this paper, we propose a logic locking method based on SAT attack and FALL attack resistance at register transfer level.
{"title":"CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level","authors":"Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa","doi":"10.1109/DFT56152.2022.9962349","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962349","url":null,"abstract":"In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attack, however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at gate level. In this paper, we propose a logic locking method based on SAT attack and FALL attack resistance at register transfer level.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131012819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962353
Raghda El Shehaby, A. Steininger
In the presence of permanent faults, QDI circuits exhibit the beneficial property of halting their operation until a repair procedure has been conducted. The state in which the circuit resides, however, does not always remain clean, i.e., a recovery process might be needed. This depends on how the circuit reacts in these situations. In this study, we investigate the effect a permanent fault has on the different components of the pipeline, the logic function unit and the butter. Our aim is to identify the weaknesses of each component and try to enhance each one accordingly. We perform extensive fault-injection simulations on different circuits following the famous 4-phase communication protocol, while varying the logic function and butter style for comparison. Our results show that the logic function does not affect the resilience of a specific butter type, and hence we can deduce which butter should perform better for a specific application based on parameters we extract from our experiments. On a parallel note, the implementation style of the logic also has an impact on the block’s ability to hold out against faults. We investigate two of these styles.
{"title":"Study and Comparison of QDI Pipeline Components’ Sensitivity to Permanent Faults","authors":"Raghda El Shehaby, A. Steininger","doi":"10.1109/DFT56152.2022.9962353","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962353","url":null,"abstract":"In the presence of permanent faults, QDI circuits exhibit the beneficial property of halting their operation until a repair procedure has been conducted. The state in which the circuit resides, however, does not always remain clean, i.e., a recovery process might be needed. This depends on how the circuit reacts in these situations. In this study, we investigate the effect a permanent fault has on the different components of the pipeline, the logic function unit and the butter. Our aim is to identify the weaknesses of each component and try to enhance each one accordingly. We perform extensive fault-injection simulations on different circuits following the famous 4-phase communication protocol, while varying the logic function and butter style for comparison. Our results show that the logic function does not affect the resilience of a specific butter type, and hence we can deduce which butter should perform better for a specific application based on parameters we extract from our experiments. On a parallel note, the implementation style of the logic also has an impact on the block’s ability to hold out against faults. We investigate two of these styles.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128455326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962337
Zhen Gao, Ying-Sheng Cheng, P. Reviriego
LDPC codes are widely used in wireless communication systems for reliable data transmission due to their excellent error correction capabilities. SRAM-FPGAs are a popular option for the implementation of LDPC decoders due to their excellent computing capabilities and re-configurability. However, when applied in critical environments, e.g. space platforms, the SRAM-FPGA based LDPC decoders will suffer single-event upsets (SEUs) that can cause failures and disrupt communications. Therefore, analyzing the reliability of LDPC decoders to SEUs on the FPGA is important. This paper first analyzes the effects of SEUs on different parts of the FPGA implemented LDPC decoder based on the module functions, including the influence of the parallelism on the decoder reliability. Then fault injection experiments are performed to validate the conclusions of the analysis. Experiment results show that about 98% of SEUs on the configuration memories can be tolerated by the decoder itself, and the modules with more interconnections are less robust to SEUs. In addition, the reliability of LDPC decoders decreases for lower levels of parallelism due to the larger computation load of each unit. These results will be a valuable input to design efficient SEU protection schemes for LDPC decoders.
{"title":"Evaluation of the Effects of SEUs on Configuration Memories in FPGA Implemented QC-LDPC Decoders","authors":"Zhen Gao, Ying-Sheng Cheng, P. Reviriego","doi":"10.1109/DFT56152.2022.9962337","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962337","url":null,"abstract":"LDPC codes are widely used in wireless communication systems for reliable data transmission due to their excellent error correction capabilities. SRAM-FPGAs are a popular option for the implementation of LDPC decoders due to their excellent computing capabilities and re-configurability. However, when applied in critical environments, e.g. space platforms, the SRAM-FPGA based LDPC decoders will suffer single-event upsets (SEUs) that can cause failures and disrupt communications. Therefore, analyzing the reliability of LDPC decoders to SEUs on the FPGA is important. This paper first analyzes the effects of SEUs on different parts of the FPGA implemented LDPC decoder based on the module functions, including the influence of the parallelism on the decoder reliability. Then fault injection experiments are performed to validate the conclusions of the analysis. Experiment results show that about 98% of SEUs on the configuration memories can be tolerated by the decoder itself, and the modules with more interconnections are less robust to SEUs. In addition, the reliability of LDPC decoders decreases for lower levels of parallelism due to the larger computation load of each unit. These results will be a valuable input to design efficient SEU protection schemes for LDPC decoders.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"417 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122850858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962340
Edian B. Annink, G. Rauwerda, E. Hakkennes, A. Menicucci, Stefano Di Mascio, G. Furano, M. Ottavi
Soft errors in embedded systems’ memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.
{"title":"Preventing Soft Errors and Hardware Trojans in RISC-V Cores","authors":"Edian B. Annink, G. Rauwerda, E. Hakkennes, A. Menicucci, Stefano Di Mascio, G. Furano, M. Ottavi","doi":"10.1109/DFT56152.2022.9962340","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962340","url":null,"abstract":"Soft errors in embedded systems’ memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115793038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962367
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen
Parallel (multi-site) testing has become one of the semiconductor industry’s standards for testing chips. The method tests multiple chips in parallel, increasing throughput and cutting test time and costs. In digital IC testing, the number of sites has currently reached the level of thousands. However, the site count is still significantly lower when accurate analog testing is required. Due to the increased complexity involved in managing multiple test sites, variations are now being observed in the measurements from site to site for analog and mixed-signal testing. Some test sites’ measurements no longer reflect the true performance of the device under test (DUT) and can lead to yield loss and possible test escapes. As it is a recent issue, very little work has been done on robust and accurate detection of issue sites. We project that it will be an important issue in the future, especially as the number of test sites in multi-site analog testing continues to increase. A method capable of effectively detecting test sites exhibiting pronounced multi-site variation is presented. The proposed method utilizes the cross-correlation similarity between the distribution of each test site and a reference distribution to detect issue sites. Boundary conditions are derived for the method using a significance level, and a site is considered an issue site if the proposed method scores for that site fall outside the derived boundary for each measured specification. The method is applied to real test data from the industry. The presented results demonstrate the effectiveness of the approach.
{"title":"Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing","authors":"Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen","doi":"10.1109/DFT56152.2022.9962367","DOIUrl":"https://doi.org/10.1109/DFT56152.2022.9962367","url":null,"abstract":"Parallel (multi-site) testing has become one of the semiconductor industry’s standards for testing chips. The method tests multiple chips in parallel, increasing throughput and cutting test time and costs. In digital IC testing, the number of sites has currently reached the level of thousands. However, the site count is still significantly lower when accurate analog testing is required. Due to the increased complexity involved in managing multiple test sites, variations are now being observed in the measurements from site to site for analog and mixed-signal testing. Some test sites’ measurements no longer reflect the true performance of the device under test (DUT) and can lead to yield loss and possible test escapes. As it is a recent issue, very little work has been done on robust and accurate detection of issue sites. We project that it will be an important issue in the future, especially as the number of test sites in multi-site analog testing continues to increase. A method capable of effectively detecting test sites exhibiting pronounced multi-site variation is presented. The proposed method utilizes the cross-correlation similarity between the distribution of each test site and a reference distribution to detect issue sites. Boundary conditions are derived for the method using a significance level, and a site is considered an issue site if the proposed method scores for that site fall outside the derived boundary for each measured specification. The method is applied to real test data from the industry. The presented results demonstrate the effectiveness of the approach.","PeriodicalId":411011,"journal":{"name":"2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120945192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-19DOI: 10.1109/DFT56152.2022.9962346
Shanshan Liu, Jing Guo, Xiaochen Tang, P. Reviriego, Fabrizio Lombardi
The ability of tolerating a radiation-induced single event upset (SEU) is required for nanoscale latches in most dependable applications. This is becoming a strict requirement, because an SEU in a latch node may corrupt its outcome and then, possibly cause a system failure. Moreover, the impact of an SEU further deteriorates for latch designs at reduced CMOS nano-scaled technology because it can result in double node upset (DNU) in addition to single node upset (SNU). Existing approaches of designing a radiation-hardened latch do not achieve complete SNU/DNU tolerance at low hardware overhead. The goal of this paper is to propose a high-performance latch design for SEU tolerance. By exploiting the polarity of the upset in different types of transistors, the proposed design has a small number of sensitive nodes, so incurring in a low protection overhead. Moreover, due to its configuration, the proposed design achieves SEU tolerance at circuit-level without requiring additional layout protection. These advantages make the proposed design superior to all existing hardened latches found in the technical literature; simulation results using 65 nm CMOS technology show that the proposed design achieves a reduction in the range of 14.53% to 98.76% in hardware overhead while providing a complete SNU/DNU recovery.
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