Michael L. Case, Victor N. Kravets, A. Mishchenko, R. Brayton
This paper presents a new type of sequential technology independent synthesis. Building on the previous notions of combinational observability and sequential equivalence, sequential observability is introduced and discussed. By considering both the sequential nature of the design and observability simultaneously, better results can be obtained than with either algorithm alone. The experimental results show that this method can reduce the technology-independent gate count up to 10% more than the previously best known synthesis techniques.
{"title":"Merging nodes under sequential observability","authors":"Michael L. Case, Victor N. Kravets, A. Mishchenko, R. Brayton","doi":"10.1145/1391469.1391605","DOIUrl":"https://doi.org/10.1145/1391469.1391605","url":null,"abstract":"This paper presents a new type of sequential technology independent synthesis. Building on the previous notions of combinational observability and sequential equivalence, sequential observability is introduced and discussed. By considering both the sequential nature of the design and observability simultaneously, better results can be obtained than with either algorithm alone. The experimental results show that this method can reduce the technology-independent gate count up to 10% more than the previously best known synthesis techniques.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128444718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The problem attacked in this paper is one of automatically mapping an application onto a network-on-chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, processor mapping, data mapping, and packet routing. In the first step, the application code is parallelized and the resulting parallel threads are assigned to virtual processors. The second step implements a virtual processor-to-physical processor mapping. The goal of this mapping is to ensure that the threads that are expected to communicate frequently with each other are assigned to neighboring processors as much as possible. In the third step, data elements are mapped to memories attached to CMP nodes. The main objective of this mapping is to place a given data item into a node which is close to the nodes that access it. The last step of our approach determines the paths (between memories and processors) for data to travel in an energy efficient manner. In this paper, we describe the compiler algorithms we implemented in detail and present an experimental evaluation of the framework. In our evaluation, we test our entire framework as well as the impact of omitting some of its steps. This experimental analysis clearly shows that the proposed framework reduces energy consumption of our applications significantly (27.41% on average over a pure performance oriented application mapping strategy) as a result of improved locality of data accesses.
{"title":"Application mapping for chip multiprocessors","authors":"Guangyu Chen, Feihui Li, S. Son, M. Kandemir","doi":"10.1145/1391469.1391628","DOIUrl":"https://doi.org/10.1145/1391469.1391628","url":null,"abstract":"The problem attacked in this paper is one of automatically mapping an application onto a network-on-chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, processor mapping, data mapping, and packet routing. In the first step, the application code is parallelized and the resulting parallel threads are assigned to virtual processors. The second step implements a virtual processor-to-physical processor mapping. The goal of this mapping is to ensure that the threads that are expected to communicate frequently with each other are assigned to neighboring processors as much as possible. In the third step, data elements are mapped to memories attached to CMP nodes. The main objective of this mapping is to place a given data item into a node which is close to the nodes that access it. The last step of our approach determines the paths (between memories and processors) for data to travel in an energy efficient manner. In this paper, we describe the compiler algorithms we implemented in detail and present an experimental evaluation of the framework. In our evaluation, we test our entire framework as well as the impact of omitting some of its steps. This experimental analysis clearly shows that the proposed framework reduces energy consumption of our applications significantly (27.41% on average over a pure performance oriented application mapping strategy) as a result of improved locality of data accesses.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129107571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is non- deterministic. To leverage testing of a SystemC TLM design, we focus on automatically exploring all possible behaviors of the design for a given data input. We combine static and dynamic partial order reduction techniques with SystemC semantics to intelligently explore a subset of the possible traces, while still being provably sufficient for detecting deadlocks and safety property violations. We have implemented our exploration algorithm in a framework called Satya and have applied it to a variety of examples including the TAC benchmark. Using Satya, we automatically found an assertion violation in a benchmark distributed as a part of the OSCI repository.
{"title":"Partial order reduction for scalable testing of SystemC TLM designs","authors":"Sudipta Kundu, Malay K. Ganai, Rajesh K. Gupta","doi":"10.1145/1391469.1391706","DOIUrl":"https://doi.org/10.1145/1391469.1391706","url":null,"abstract":"A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is non- deterministic. To leverage testing of a SystemC TLM design, we focus on automatically exploring all possible behaviors of the design for a given data input. We combine static and dynamic partial order reduction techniques with SystemC semantics to intelligently explore a subset of the possible traces, while still being provably sufficient for detecting deadlocks and safety property violations. We have implemented our exploration algorithm in a framework called Satya and have applied it to a variety of examples including the TAC benchmark. Using Satya, we automatically found an assertion violation in a benchmark distributed as a part of the OSCI repository.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129127292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3 dB, and the within-chip process-induced variation is reduced by 3 dB, which improves chip-limited yield. The parallel VCOs trade off circuit area and power in exchange. The parallelism advantages in analog and digital systems are compared.
{"title":"Analog parallelism in ring-based VCOs","authors":"Daeik D. Kim, Choongyeun Cho, Jonghae Kim","doi":"10.1145/1391469.1391557","DOIUrl":"https://doi.org/10.1145/1391469.1391557","url":null,"abstract":"The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3 dB, and the within-chip process-induced variation is reduced by 3 dB, which improves chip-limited yield. The parallel VCOs trade off circuit area and power in exchange. The parallelism advantages in analog and digital systems are compared.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116979954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shreyas Sen, Vishwanath Natarajan, R. Senguttuvan, A. Chatterjee
In this paper, a process tunable, continuously adaptive wireless front end architecture and related adaptation algorithms are presented that allow an RF transceiver to function at minimum power irrespective of channel conditions and process variability induced performance loss in the RF front end and baseband interface. Current wireless transceiver front ends are designed for worst case channel conditions and a limited degree of post manufacture tuning is performed to compensate for process variations. It is shown how the proposed architecture can result in significant power savings over current practice without compromising system-level bit error rate. The adaptation methodology is applied to a WLAN transceiver design and hardware measurement data for an adaptive receiver is presented.
{"title":"Pro-VIZOR: Process tunable virtually zero margin low power adaptive RF for wireless systems","authors":"Shreyas Sen, Vishwanath Natarajan, R. Senguttuvan, A. Chatterjee","doi":"10.1145/1391469.1391595","DOIUrl":"https://doi.org/10.1145/1391469.1391595","url":null,"abstract":"In this paper, a process tunable, continuously adaptive wireless front end architecture and related adaptation algorithms are presented that allow an RF transceiver to function at minimum power irrespective of channel conditions and process variability induced performance loss in the RF front end and baseband interface. Current wireless transceiver front ends are designed for worst case channel conditions and a limited degree of post manufacture tuning is performed to compensate for process variations. It is shown how the proposed architecture can result in significant power savings over current practice without compromising system-level bit error rate. The adaptation methodology is applied to a WLAN transceiver design and hardware measurement data for an adaptive receiver is presented.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127331537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better write- ability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance -- a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130 nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher write- trip-point and 120 mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.
{"title":"Process variation tolerant SRAM array for ultra low voltage applications","authors":"J. Kulkarni, Keejong Kim, S. P. Park, K. Roy","doi":"10.1145/1391469.1391498","DOIUrl":"https://doi.org/10.1145/1391469.1391498","url":null,"abstract":"In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better write- ability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance -- a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130 nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher write- trip-point and 120 mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128093290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Mohalik, A. Rajeev, Manoj G. Dixit, S. Ramesh, P. Suman, P. Pandya, Shengbing Jiang
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In this paper we give a formal definition of end-to-end latency, and use this as the basis for checking whether a stipulated deadline is violated within a bounded time. For unbounded verification, we model the system as a set of communicating timed automata, and perform reachability analysis. The proposed method takes into account the drift of clocks which is shown to affect the latency appreciably. The method has been tested on a medium sized automotive example.
{"title":"Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts","authors":"S. Mohalik, A. Rajeev, Manoj G. Dixit, S. Ramesh, P. Suman, P. Pandya, Shengbing Jiang","doi":"10.1145/1391469.1391544","DOIUrl":"https://doi.org/10.1145/1391469.1391544","url":null,"abstract":"End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In this paper we give a formal definition of end-to-end latency, and use this as the basis for checking whether a stipulated deadline is violated within a bounded time. For unbounded verification, we model the system as a set of communicating timed automata, and perform reachability analysis. The proposed method takes into account the drift of clocks which is shown to affect the latency appreciably. The method has been tested on a medium sized automotive example.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127497295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Chaudhuri, S. Guilley, Florent Flament, P. Hoogvorst, J. Danger
This paper presents a RTR FPGA embedded in a system on chip fabricated in 130 nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(hardware blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.
{"title":"An 8×8 run-time reconfigurable FPGA embedded in a SoC","authors":"S. Chaudhuri, S. Guilley, Florent Flament, P. Hoogvorst, J. Danger","doi":"10.1145/1391469.1391500","DOIUrl":"https://doi.org/10.1145/1391469.1391500","url":null,"abstract":"This paper presents a RTR FPGA embedded in a system on chip fabricated in 130 nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(hardware blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126333940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power gating is a technique for efficiently reducing leakage power by disconnecting idle blocks from the power grid. When gated blocks are woken up, large amounts of switching currents are drawn in a short period of time that may introduce severe noise on the power delivery mesh. In this paper, we propose a GA-based approach to schedule power gating considering power/ground noise. We introduce a simulation-based method to accurately and efficiently estimate the worst case noise, taking all the current sources, inductance and decaps' effects into consideration. We also present an incremental scheduling procedure considering the dynamic changes of decap configuration. Experimental results show that by optimally scheduling the wake-up order under time constraints, our technique can reduce noise up to 50% compared to waking gated blocks simultaneously. The quality of results depends upon the total wake-up time constraint, locations of gated blocks, current densities of gated blocks, and decap distribution.
{"title":"Power gating scheduling for power/ground noise reduction","authors":"Hailin Jiang, M. Marek-Sadowska","doi":"10.1145/1391469.1391716","DOIUrl":"https://doi.org/10.1145/1391469.1391716","url":null,"abstract":"Power gating is a technique for efficiently reducing leakage power by disconnecting idle blocks from the power grid. When gated blocks are woken up, large amounts of switching currents are drawn in a short period of time that may introduce severe noise on the power delivery mesh. In this paper, we propose a GA-based approach to schedule power gating considering power/ground noise. We introduce a simulation-based method to accurately and efficiently estimate the worst case noise, taking all the current sources, inductance and decaps' effects into consideration. We also present an incremental scheduling procedure considering the dynamic changes of decap configuration. Experimental results show that by optimally scheduling the wake-up order under time constraints, our technique can reduce noise up to 50% compared to waking gated blocks simultaneously. The quality of results depends upon the total wake-up time constraint, locations of gated blocks, current densities of gated blocks, and decap distribution.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123470091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Eshel Haritan, T. Hattori, Hiroyuki Yagi, P. Paulin, W. Wolf, A. Nohl, D. Wingard, M. Muller
Multi Processor SoC (MPSoC) are being designed today. MPSoC design can help achieve aggressive performance and low power targets but it creates new design challenges: How to design the interconnect fabric and memory sub-system to allow the massive data movement required in a multi processor SoC environment? How to develop, debug and verify HW and SW functionality in a MPSoC design? Is MPSoC design an inflection point that will require new design methods including ESL methodologies?
{"title":"Multicore design is the challenge! What is the solution?","authors":"Eshel Haritan, T. Hattori, Hiroyuki Yagi, P. Paulin, W. Wolf, A. Nohl, D. Wingard, M. Muller","doi":"10.1145/1391469.1391504","DOIUrl":"https://doi.org/10.1145/1391469.1391504","url":null,"abstract":"Multi Processor SoC (MPSoC) are being designed today. MPSoC design can help achieve aggressive performance and low power targets but it creates new design challenges: How to design the interconnect fabric and memory sub-system to allow the massive data movement required in a multi processor SoC environment? How to develop, debug and verify HW and SW functionality in a MPSoC design? Is MPSoC design an inflection point that will require new design methods including ESL methodologies?","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121541560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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